1 2-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc 3 4-- This file is part of VESTs (Vhdl tESTs). 5 6-- VESTs is free software; you can redistribute it and/or modify it 7-- under the terms of the GNU General Public License as published by the 8-- Free Software Foundation; either version 2 of the License, or (at 9-- your option) any later version. 10 11-- VESTs is distributed in the hope that it will be useful, but WITHOUT 12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14-- for more details. 15 16-- You should have received a copy of the GNU General Public License 17-- along with VESTs; if not, write to the Free Software Foundation, 18-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 20-- --------------------------------------------------------------------- 21-- 22-- $Id: ch_08_fg_08_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $ 23-- $Revision: 1.2 $ 24-- 25-- --------------------------------------------------------------------- 26 27-- not in book 28 29library ieee; use ieee.std_logic_1164.all; 30 31 entity phase_locked_clock_gen is 32 port ( reference : in std_ulogic; 33 phi1, phi2 : out std_ulogic ); 34 end entity phase_locked_clock_gen; 35 36 37 architecture std_cell of phase_locked_clock_gen is 38 39 --use work.clock_pkg.Tpw; 40 use work.clock_pkg.all; 41 42 begin 43 44 phi1_gen : phi1 <= '1', '0' after Tpw when rising_edge(reference); 45 46 phi2_gen : phi2 <= '1', '0' after Tpw when falling_edge(reference); 47 48 end architecture std_cell; 49 50-- end not in book 51 52 53 54 library ieee; use ieee.std_logic_1164.all; 55 56 entity io_controller is 57 port ( ref_clock : in std_ulogic; -- . . . ); 58 -- not in book 59 other_port : in std_ulogic ); 60 -- end not in book 61 end entity io_controller; 62 63-------------------------------------------------- 64 65 architecture top_level of io_controller is 66 67 -- . . . 68 69 -- not in book 70 signal rd, wr, sel, width, burst : std_ulogic; 71 signal addr : std_ulogic_vector(1 downto 0); 72 signal ready : std_ulogic; 73 signal control_reg_wr, status_reg_rd, data_fifo_wr, data_fifo_rd, 74 other_signal : std_ulogic; 75 -- end not in book 76 77 begin 78 79 internal_clock_gen : entity work.phase_locked_clock_gen(std_cell) 80 port map ( reference => ref_clock, 81 phi1 => work.clock_pkg.clock_phase1, 82 phi2 => work.clock_pkg.clock_phase2 ); 83 84 the_bus_sequencer : entity work.bus_sequencer(fsm) 85 port map ( rd, wr, sel, width, burst, addr(1 downto 0), ready, 86 control_reg_wr, status_reg_rd, data_fifo_wr, data_fifo_rd, 87 -- . . . ); 88 other_signal ); 89 -- not in book 90 91 -- . . . 92 93 end architecture top_level; 94