1 2-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc 3 4-- This file is part of VESTs (Vhdl tESTs). 5 6-- VESTs is free software; you can redistribute it and/or modify it 7-- under the terms of the GNU General Public License as published by the 8-- Free Software Foundation; either version 2 of the License, or (at 9-- your option) any later version. 10 11-- VESTs is distributed in the hope that it will be useful, but WITHOUT 12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14-- for more details. 15 16-- You should have received a copy of the GNU General Public License 17-- along with VESTs; if not, write to the Free Software Foundation, 18-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 20-- --------------------------------------------------------------------- 21-- 22-- $Id: ch_21_fg_21_06.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $ 23-- $Revision: 1.2 $ 24-- 25-- --------------------------------------------------------------------- 26 27entity multiprocessor is 28end entity multiprocessor; 29 30 31-- code from book 32 33architecture instrumented of multiprocessor is 34 35 -- not in book 36 constant num_processors : positive := 2; 37 -- end not in book 38 39 shared variable bus_ifetch_count, 40 bus_read_count, 41 bus_write_count : natural := 0; 42 43 signal bus_request, bus_grant : bit_vector(0 to num_processors - 1); 44 -- . . . -- other signal declarations 45 46begin 47 48 processor_array : 49 for processor_id in 0 to num_processors - 1 generate 50 51 processor : process is 52 -- . . . 53 begin 54 -- . . . -- initialize 55 loop 56 bus_request(processor_id) <= '1'; 57 wait until bus_grant(processor_id) = '1'; 58 bus_ifetch_count := bus_ifetch_count + 1; 59 -- . . . -- fetch instruction 60 bus_request(processor_id) <= '0'; 61 -- . . . -- decode and execute instruction 62 -- not in book 63 wait until bus_grant(processor_id) = '0'; 64 -- end not in book 65 end loop; 66 end process processor; 67 68 end generate processor_array; 69 70 arbiter : process is 71 begin 72 -- . . . 73 -- not in book 74 loop 75 for i in bus_request'range loop 76 if bus_request(i) = '1' then 77 bus_grant(i) <= '1' after 5 ns; 78 wait until bus_request(i) = '0'; 79 bus_grant(i) <= '0' after 5 ns; 80 end if; 81 end loop; 82 wait for 5 ns; 83 end loop; 84 -- end not in book 85 end process arbiter; 86 87 -- . . . -- other processes for memory, etc 88 89end architecture instrumented; 90 91-- end code from book 92