1
2-- Copyright (C) 2001 Bill Billowitch.
3
4-- Some of the work to develop this test suite was done with Air Force
5-- support.  The Air Force and Bill Billowitch assume no
6-- responsibilities for this software.
7
8-- This file is part of VESTs (Vhdl tESTs).
9
10-- VESTs is free software; you can redistribute it and/or modify it
11-- under the terms of the GNU General Public License as published by the
12-- Free Software Foundation; either version 2 of the License, or (at
13-- your option) any later version.
14
15-- VESTs is distributed in the hope that it will be useful, but WITHOUT
16-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
18-- for more details.
19
20-- You should have received a copy of the GNU General Public License
21-- along with VESTs; if not, write to the Free Software Foundation,
22-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
23
24-- ---------------------------------------------------------------------
25--
26-- $Id: tc1658.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
27-- $Revision: 1.2 $
28--
29-- ---------------------------------------------------------------------
30
31entity E  is
32  port ( S_in : in bit; S_out : out bit) ;
33end E;
34
35entity C1  is
36  port ( A : bit; B :out bit) ;
37end C1;
38
39use work.c1;
40
41ENTITY c09s01b00x00p02n01i01658ent IS
42  port ( B : bit ) ;
43END c09s01b00x00p02n01i01658ent;
44
45ARCHITECTURE c09s01b00x00p02n01i01658arch OF c09s01b00x00p02n01i01658ent IS
46
47BEGIN
48
49  lab : block
50    component C1
51      port ( A : bit; B : out bit );
52    end component ; -- C1
53
54    for all : C1 use entity work.E
55      port map ( S_in => A, S_out => B ) ;
56
57    type    T1 is ('0', '1');
58    subtype T2 is integer range 0 to 7;
59
60    signal S1    : real;
61    alias  S1_too    : real is S1;
62
63    attribute ATTR : T1;
64    attribute ATTR of ALL : signal is '1';
65
66  begin
67    TESTING: PROCESS
68    BEGIN
69      assert FALSE
70        report "***PASSED TEST: c09s01b00x00p02n01i01658"
71        severity NOTE;
72      wait;
73    END PROCESS TESTING;
74  end block lab;
75
76
77END c09s01b00x00p02n01i01658arch;
78