1
2-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
3
4-- This file is part of VESTs (Vhdl tESTs).
5
6-- VESTs is free software; you can redistribute it and/or modify it
7-- under the terms of the GNU General Public License as published by the
8-- Free Software Foundation; either version 2 of the License, or (at
9-- your option) any later version.
10
11-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14-- for more details.
15
16-- You should have received a copy of the GNU General Public License
17-- along with VESTs; if not, write to the Free Software Foundation,
18-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19
20use work.resolve.all;
21
22-- code from book (in text)
23
24entity tri_state_reg is
25  port ( d : in resolved_byte;
26         q : out resolved_byte bus;
27         clock, out_enable : in bit );
28end entity tri_state_reg;
29
30-- end code from book
31
32
33
34-- code from book
35
36architecture behavioral of tri_state_reg is
37begin
38
39  reg_behavior : process (d, clock, out_enable) is
40    variable stored_byte : byte;
41  begin
42    if clock'event and clock = '1' then
43      stored_byte := d;
44    end if;
45    if out_enable = '1' then
46      q <= stored_byte;
47    else
48      q <= null;
49    end if;
50  end process reg_behavior;
51
52end architecture behavioral;
53
54-- end code from book
55