1// DA Solutions LFSR model used for sizing tests
2// Created by D. J. Wharton, 1-Sep-94
3// Model equivalent to 50,000 gates
4// Equivalent model in VHDL
5
6/* ---
7copied primitive from library to here
8--- */
9
10`timescale 1ns / 1ns
11
12module fd2xl(d, cp, cd, q, qn);
13 input d, cp, cd;
14 output q, qn;
15 wire xxx;
16
17 xl_fd2 #10 i0(xxx, d, cp, cd);
18 buf i1(q, xxx);
19 not i2(qn, xxx);
20endmodule
21
22primitive xl_fd2(q, d, cp, cd);
23 output q; reg q;
24 input d, cp, cd;
25
26 table
27  // d  cp  cd  :  q  :  q
28  // -  --  --  -  -  -  -
29     ?   ?   0  :  ?  :  0 ;
30     ?   ?   x  :  ?  :  x ;
31
32     0   r   1  :  ?  :  0 ;
33     1   r   1  :  ?  :  1 ;
34     x   r   1  :  ?  :  x ;
35
36     ?   f   1  :  ?  :  - ;
37     *   ?   1  :  ?  :  - ;
38     ?   ?   r  :  ?  :  - ;
39 endtable
40endprimitive
41
42module	EN (a, b, z);
43
44input	a, b;
45output	z;
46
47xnor #1 g1(z, a, b);
48
49endmodule
50
51/* --- end of library --- */
52
53module lfsr (d, clk, reset, q);
54
55  input d, clk, reset;
56  output q;
57
58  EN  	en_1 (d, q7, xout);
59
60  fd2xl 	fd2_1 (xout, clk, reset, q1, q1b),
61        fd2_2 (q1, clk, reset, q2, q2b),
62        fd2_3 (q2, clk, reset, q3, q3b),
63        fd2_4 (q3, clk, reset, q4, q4b),
64        fd2_5 (q4, clk, reset, q5, q5b),
65        fd2_6 (q5, clk, reset, q6, q6b),
66        fd2_7 (q6, clk, reset, q7, q7b),
67        fd2_8 (q7, clk, reset, q8, q8b),
68        fd2_9 (q8, clk, reset, q9, q9b),
69        fd2_10 (q9, clk, reset, q, q10b);
70
71endmodule
72
73
74module lfsr10 (d, clk, reset, q);
75
76  input d, clk, reset;
77  output q;
78
79  lfsr	 lfsr_1 (d,  clk, reset, d1),
80         lfsr_2 (d1, clk, reset, d2),
81         lfsr_3 (d2, clk, reset, d3),
82         lfsr_4 (d3, clk, reset, d4),
83         lfsr_5 (d4, clk, reset, d5),
84         lfsr_6 (d5, clk, reset, d6),
85         lfsr_7 (d6, clk, reset, d7),
86         lfsr_8 (d7, clk, reset, d8),
87         lfsr_9 (d8, clk, reset, d9),
88         lfsr_10(d9, clk, reset, q );
89
90endmodule
91
92
93module lfsr100 (d, clk, reset, q);
94
95  input d, clk, reset;
96  output q;
97
98  lfsr10 lfsr10_1 (d , clk, reset, d1),
99         lfsr10_2 (d1, clk, reset, d2),
100         lfsr10_3 (d2, clk, reset, d3),
101         lfsr10_4 (d3, clk, reset, d4),
102         lfsr10_5 (d4, clk, reset, d5),
103         lfsr10_6 (d5, clk, reset, d6),
104         lfsr10_7 (d6, clk, reset, d7),
105         lfsr10_8 (d7, clk, reset, d8),
106         lfsr10_9 (d8, clk, reset, d9),
107         lfsr10_10(d9, clk, reset, q );
108
109
110endmodule
111
112
113module lfsr500 (d, clk, reset, q);
114
115  input d, clk, reset;
116  output q;
117
118  lfsr100 lfsr100_1(d , clk, reset, d1),
119         lfsr100_2 (d1, clk, reset, d2),
120         lfsr100_3 (d2, clk, reset, d3),
121         lfsr100_4 (d3, clk, reset, d4),
122         lfsr100_5 (d4, clk, reset, q);
123
124
125endmodule
126
127
128module test;
129
130wire	d;
131
132reg 		reset, creset;
133wire		clk_out;
134wire		clk_in;
135
136reg	[0:31] 	tempword;
137reg	[0:4]	j;
138
139lfsr500	lfsr500_1 (d, clk_out, reset, q);
140
141buf		buf_1 (d,q);
142
143not 	#50	clk_1 (clk_in, clk_out);
144and		clk_2 (clk_out, clk_in, creset);
145
146  initial
147  begin
148		reset = 1;
149	#25	reset = 0; creset = 0;
150	#25	reset = 1;
151	#50	creset = 1;
152    	#99900 	$finish(2);
153  end
154
155// Results display code
156
157initial
158begin
159	tempword = 0; j = 0;
160	#25 $write ("\n");
161	    $display ("Results display");
162end
163
164always
165begin
166	@ (posedge clk_out)
167	begin
168	tempword[j] = d;
169	j = j + 1;
170	if ( j == 0)
171	begin
172	$display ($time,,"%b",tempword[0:7],,"%b",tempword[8:15],,"%b",tempword[16:23],,"%b",tempword[24:31],);
173	tempword = 0;
174	end
175	end
176end
177
178endmodule
179