1#=========================================================================
2# YosysTranslator_L2_cases_test.py
3#=========================================================================
4"""Test the yosys-SystemVerilog translator."""
5
6import pytest
7
8from pymtl3.passes.backends.verilog.util.test_utility import check_eq
9from pymtl3.passes.rtlir.util.test_utility import get_parameter
10
11from ...testcases import (
12    CaseConnectPassThroughLongNameComp,
13    ThisIsABitStructWithSuperLongName,
14)
15from ..behavioral.test.YosysBehavioralTranslatorL2_test import test_yosys_behavioral_L2
16from ..behavioral.test.YosysBehavioralTranslatorL3_test import test_yosys_behavioral_L3
17from ..structural.test.YosysStructuralTranslatorL2_test import test_yosys_structural_L2
18from ..YosysTranslator import YosysTranslator
19
20
21def run_test( case, m ):
22  m.elaborate()
23  tr = YosysTranslator( m )
24  tr.translate( m )
25  check_eq( tr.hierarchy.src, case.REF_SRC )
26
27@pytest.mark.parametrize(
28  'case', get_parameter('case', test_yosys_behavioral_L2) + \
29          get_parameter('case', test_yosys_behavioral_L3) + \
30          get_parameter('case', test_yosys_structural_L2)
31)
32def test_yosys_L2( case ):
33  run_test( case, case.DUT() )
34
35def test_long_component_name():
36  args = [ThisIsABitStructWithSuperLongName]*7
37  run_test( CaseConnectPassThroughLongNameComp, CaseConnectPassThroughLongNameComp.DUT(*args) )
38
39@pytest.mark.xfail(run=False, reason="TODO: resolving BitStructs according to name AND fields")
40def test_struct_uniqueness():
41  class A:
42    @bitstruct
43    class ST:
44      a_foo: Bits16
45      a_bar: Bits32
46
47  class B:
48    @bitstruct
49    class ST:
50      b_foo: Bits16
51      b_bar: Bits32
52
53  @bitstruct
54  class COMB:
55    fst: A.ST
56    snd: B.ST
57
58  class Top( Component ):
59    def construct( s ):
60      s.out = OutPort( COMB )
61      connect( s.out, COMB(A.ST(1, 2), B.ST(3, 4)) )
62  a = Top()
63  a.REF_SRC = \
64"""
65typedef struct packed {
66  logic [15:0] foo;
67  logic [31:0] bar;
68} ST;
69
70typedef struct packed {
71  ST fst;
72  ST snd;
73} COMB;
74
75module Top
76(
77  input logic [0:0] clk,
78  output COMB out,
79  input logic [0:0] reset
80);
81
82  assign out = { { 16'd1, 32'd2 }, { 16'd3, 32'd4 } };
83
84endmodule
85"""
86  a.YOSYS_REF_SRC = \
87"""
88module Top
89(
90  input logic [0:0] clk,
91  output logic [15:0] out__fst__foo,
92  output logic [31:0] out__fst__bar,
93  output logic [15:0] out__snd__foo,
94  output logic [31:0] out__snd__bar,
95  input logic [0:0] reset
96);
97  logic [47:0]  out__fst;
98  logic [47:0]  out__snd;
99  logic [95:0]  out;
100
101  assign out__fst__foo = out__fst[47:32];
102  assign out__fst__bar = out__fst[31:0];
103  assign out__snd__foo = out__snd[47:32];
104  assign out__snd__bar = out__snd[31:0];
105  assign out__fst__foo = out[95:80];
106  assign out__fst__bar = out[79:48];
107  assign out__snd__foo = out[47:32];
108  assign out__snd__bar = out[31:0];
109  assign out = { { 16'd1, 32'd2 }, { 16'd3, 32'd4 } };
110
111endmodule
112"""
113  run_test( a, Top() )
114