1//: version "2.1" 2//: property encoding = "utf-8" 3//: property locale = "en" 4//: property prefix = "_GG" 5//: property title = "Tutorial page" 6//: property showSwitchNets = 0 7//: property discardChanges = 1 8//: property timingViolationMode = 2 9//: property initTime = "0 ns" 10 11`timescale 1ns/1ns 12 13//: /netlistBegin PAGE1 14module PAGE1; //: root_module 15//: enddecls 16 17 //: comment g1 @(475,291) /sn:0 /R:14 /anc:1 18 //: /line:"<a href=\"welcome.v\">Go back to the TkGate main page.</a>" 19 //: /end 20 //: comment g0 @(476,49) /sn:0 /anc:1 21 //: /line:"<a href=\"welcome.v\"><img src=\"biggatelogo.gif\"></a>" 22 //: /end 23 //: comment g18 @(10,10) /sn:0 /anc:1 24 //: /line:"<h1>Tutorial Chapters:</h1>" 25 //: /line:"" 26 //: /line:"<h3><a href=\"create.v\">1. Creating a Circuit</a></h3> - Get started by creating a simple circuit." 27 //: /line:"" 28 //: /line:"<h3><a href=\"gates.v\">2. Editing Gates</a></h3> - The basics of editing gates." 29 //: /line:"" 30 //: /line:"<h3><a href=\"wires.v\">3. Editing Wires</a></h3> - The basics of editing wires." 31 //: /line:"" 32 //: /line:"<h3><a href=\"group.v\">4. Group Editing Features</a></h3> - Operate on groups of gates." 33 //: /line:"" 34 //: /line:"<h3><a href=\"modules.v\">5. Using Modules</a></h3> - Using modules in your circuit." 35 //: /line:"" 36 //: /line:"<h3><a href=\"advanced.v\">6. Advanced Editing Techniques</a></h3> - Learn advanced editing tricks." 37 //: /line:"" 38 //: /line:"<h3><a href=\"combinational1.v\">7. Combinational Simulation</a></h3> - Simulate a circuit with" 39 //: /line:"combinational logic." 40 //: /line:"" 41 //: /line:"<h3><a href=\"sequential1.v\">8. Sequential Simulation</a></h3> - Simulate a circuit with sequential logic." 42 //: /line:"" 43 //: /line:"<h3><a href=\"verilog.v\">9. Textual Verilog</a></h3> - Create modules with textual Verilog descriptions." 44 //: /line:"" 45 //: /line:"<h3><a href=\"options.v\">10. Customizing TkGate</a></h3> - Customize TkGate to suit your tastes." 46 //: /line:"" 47 //: /end 48 49endmodule 50//: /netlistEnd 51 52