1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2006 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/
8   // Inputs
9   clk
10   );
11
12   input clk;
13
14   integer cyc; initial cyc = 0;
15   reg [63:0] crc;
16   reg [63:0] sum;
17
18   reg 	      out1;
19   reg [4:0]  out2;
20   sub sub (.in(crc[23:0]), .out1(out1), .out2(out2));
21
22   always @ (posedge clk) begin
23      //$write("[%0t] cyc==%0d crc=%x sum=%x out=%x,%x\n", $time, cyc, crc, sum, out1,out2);
24      cyc <= cyc + 1;
25      crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
26      sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2};
27      if (cyc==0) begin
28	 // Setup
29	 crc <= 64'h00000000_00000097;
30	 sum <= 64'h0;
31      end
32      else if (cyc==90) begin
33	 if (sum !== 64'hf0afc2bfa78277c5) $stop;
34      end
35      else if (cyc==91) begin
36      end
37      else if (cyc==92) begin
38      end
39      else if (cyc==93) begin
40      end
41      else if (cyc==94) begin
42      end
43      else if (cyc==99) begin
44	 $write("*-* All Finished *-*\n");
45	 $finish;
46      end
47   end
48
49endmodule
50
51module sub (/*AUTOARG*/
52   // Outputs
53   out1, out2,
54   // Inputs
55   in
56   );
57
58   input      [23:0] in;
59   output reg 	     out1;
60   output reg [4:0]  out2;
61
62   always @* begin
63      // Test empty cases
64      casez (in[0])
65      endcase
66      casez (in)
67	24'b0000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b0,5'h00};
68	24'b????_????_????_????_????_???1 : {out1,out2} = {1'b1,5'h00};
69	24'b????_????_????_????_????_??10 : {out1,out2} = {1'b1,5'h01};
70	24'b????_????_????_????_????_?100 : {out1,out2} = {1'b1,5'h02};
71	24'b????_????_????_????_????_1000 : {out1,out2} = {1'b1,5'h03};
72	24'b????_????_????_????_???1_0000 : {out1,out2} = {1'b1,5'h04};
73	24'b????_????_????_????_??10_0000 : {out1,out2} = {1'b1,5'h05};
74	24'b????_????_????_????_?100_0000 : {out1,out2} = {1'b1,5'h06};
75	24'b????_????_????_????_1000_0000 : {out1,out2} = {1'b1,5'h07};
76	// Same pattern, but reversed to test we work OK.
77	24'b1000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h17};
78	24'b?100_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h16};
79	24'b??10_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h15};
80	24'b???1_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h14};
81	24'b????_1000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h13};
82	24'b????_?100_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h12};
83	24'b????_??10_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h11};
84	24'b????_???1_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h10};
85	24'b????_????_1000_0000_0000_0000 : {out1,out2} = {1'b1,5'h0f};
86	24'b????_????_?100_0000_0000_0000 : {out1,out2} = {1'b1,5'h0e};
87	24'b????_????_??10_0000_0000_0000 : {out1,out2} = {1'b1,5'h0d};
88	24'b????_????_???1_0000_0000_0000 : {out1,out2} = {1'b1,5'h0c};
89	24'b????_????_????_1000_0000_0000 : {out1,out2} = {1'b1,5'h0b};
90	24'b????_????_????_?100_0000_0000 : {out1,out2} = {1'b1,5'h0a};
91	24'b????_????_????_??10_0000_0000 : {out1,out2} = {1'b1,5'h09};
92	24'b????_????_????_???1_0000_0000 : {out1,out2} = {1'b1,5'h08};
93      endcase
94   end
95
96endmodule
97