1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2020 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7class Cls;
8   function int rand_mode(bit onoff);
9      return 1;
10   endfunction
11   function int constraint_mode(bit onoff);
12      return 1;
13   endfunction
14endclass
15
16module t (/*AUTOARG*/);
17   initial begin
18      Cls c;
19   end
20endmodule
21