1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2020 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7class Base0; 8 int baseonly; 9 int baseover; 10 11 function void b_set_bo(int v); baseover = v; endfunction 12 function int b_get_bo(); return baseover; endfunction 13 function int get_bo(); return baseover; endfunction 14endclass 15 16class Ext extends Base0; 17 int baseover; 18 int extonly; 19 20 function void e_set_bo(int v); baseover = v; endfunction 21 function int e_get_bo(); return baseover; endfunction 22 function int get_bo(); return baseover; endfunction 23endclass 24 25module t (/*AUTOARG*/); 26 initial begin 27 Ext c; 28 c = new; 29 c.baseonly = 10; 30 c.baseover = 20; 31 c.extonly = 30; 32 if (c.baseonly != 10) $stop; 33 if (c.baseover != 20) $stop; 34 if (c.extonly != 30) $stop; 35 36 c.b_set_bo(100); 37 c.e_set_bo(200); 38 if (c.b_get_bo() != 100) $stop; 39 if (c.e_get_bo() != 200) $stop; 40 if (c.get_bo() != 200) $stop; 41 42 $write("*-* All Finished *-*\n"); 43 $finish; 44 end 45endmodule 46