1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2021 by Iru Cai.
5// SPDX-License-Identifier: CC0-1.0
6
7class Cls1;
8   int ctr;
9   task run();
10      $display("%d", ctr);
11      ctr = ctr + 1;
12   endtask: run
13endclass;
14
15class Cls2 extends Cls1;
16   task runtask();
17      run();
18      run();
19      run();
20      run();
21      run();
22      run();
23   endtask: runtask
24endclass
25
26module top;
27   Cls2 o;
28   initial begin
29      o = new;
30      o.runtask();
31      $write("*-* All Finished *-*\n");
32      $finish;
33   end
34endmodule
35