1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2020 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t;
8   task main;
9      integer varintask;
10      varintask = 0;
11      while (varintask < 4) begin
12         varintask = varintask + 1;
13      end
14      if (varintask != 4) $stop;
15   endtask
16   initial begin
17      main;
18      $write("*-* All Finished *-*\n");
19      $finish;
20   end
21endmodule
22