1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2011 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/); 8 9 initial begin 10 // verilator lint_off IGNOREDRETURN 11 func(0, 1'b1); 12 end 13 14 function automatic int func 15 ( 16 input int a, 17 output bit b ); 18 return 0; 19 endfunction 20 21endmodule 22