1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2004 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/ 8 // Inputs 9 clk 10 ); 11 12 input clk; 13 integer cyc; initial cyc=1; 14 15 reg [31:0] a; 16 reg [31:0] b; 17 18 wire [2:0] bf; buf BF0 (bf[0], a[0]), 19 BF1 (bf[1], a[1]), 20 BF2 (bf[2], a[2]); 21 22 // verilator lint_off IMPLICIT 23 not #(0.108) NT0 (nt0, a[0]); 24 and #1 AN0 (an0, a[0], b[0]); 25 nand #(2,3) ND0 (nd0, a[0], b[0], b[1]); 26 or OR0 (or0, a[0], b[0]); 27 nor NR0 (nr0, a[0], b[0], b[2]); 28 xor (xo0, a[0], b[0]); 29 xnor (xn0, a[0], b[0], b[2]); 30 // verilator lint_on IMPLICIT 31 32 parameter BITS=32; 33 wire [BITS-1:0] ba; 34 buf BARRAY [BITS-1:0] (ba, a); 35 36`ifdef verilator 37 specify 38 specparam CDS_LIBNAME = "foobar"; 39 (nt0 *> nt0) = (0, 0); 40 endspecify 41 42 specify 43 // delay parameters 44 specparam 45 a$A1$Y = 1.0, 46 b$A0$Z = 1.0; 47 48 // path delays 49 (A1 *> Q) = (a$A1$Y, a$A1$Y); 50 (A0 *> Q) = (b$A0$Y, a$A0$Z); 51 52 if (C1) (IN => OUT) = (1,1); 53 ifnone (IN => OUT) = (2,2); 54 55 showcancelled Q; 56 noshowcancelled Q; 57 pulsestyle_ondetect Q; 58 pulsestyle_onevent Q; 59 60 // other unimplemented stuff 61 $fullskew(); 62 $hold(); 63 $nochange(); 64 $period(); 65 $recovery(); 66 $recrem(); 67 $removal(); 68 $setup(); 69 $setuphold(); 70 $skew(); 71 $timeskew(); 72 $width(); 73 74 endspecify 75`endif 76 77 always @ (posedge clk) begin 78 if (cyc!=0) begin 79 cyc <= cyc + 1; 80 if (cyc==1) begin 81 a <= 32'h18f6b034; 82 b <= 32'h834bf892; 83 end 84 if (cyc==2) begin 85 a <= 32'h529ab56f; 86 b <= 32'h7835a237; 87 if (bf !== 3'b100) $stop; 88 if (nt0 !== 1'b1) $stop; 89 if (an0 !== 1'b0) $stop; 90 if (nd0 !== 1'b1) $stop; 91 if (or0 !== 1'b0) $stop; 92 if (nr0 !== 1'b1) $stop; 93 if (xo0 !== 1'b0) $stop; 94 if (xn0 !== 1'b1) $stop; 95 if (ba != 32'h18f6b034) $stop; 96 end 97 if (cyc==3) begin 98 if (bf !== 3'b111) $stop; 99 if (nt0 !== 1'b0) $stop; 100 if (an0 !== 1'b1) $stop; 101 if (nd0 !== 1'b0) $stop; 102 if (or0 !== 1'b1) $stop; 103 if (nr0 !== 1'b0) $stop; 104 if (xo0 !== 1'b0) $stop; 105 if (xn0 !== 1'b0) $stop; 106 end 107 if (cyc==4) begin 108 $write("*-* All Finished *-*\n"); 109 $finish; 110 end 111 end 112 end 113 114endmodule 115