1// DESCRIPTION: Verilator: Verilog Test module 2// 3// A test of the import parameter used with modport 4// 5// This file ONLY is placed into the Public Domain, for any use, 6// without warranty, 2013 by Jeremy Bennett. 7// SPDX-License-Identifier: CC0-1.0 8 9interface test_if; 10 11 // Interface variable 12 logic data; 13 14 // Modport 15 modport mp( 16 import myfunc, 17 output data 18 ); 19 20 function automatic logic myfunc (input logic val); 21 begin 22 myfunc = (val == 1'b0); 23 end 24 endfunction 25 26endinterface // test_if 27 28 29module t (/*AUTOARG*/ 30 // Inputs 31 clk 32 ); 33 input clk; 34 35 test_if i (); 36 37 testmod testmod_i (.clk (clk), 38 .i (i.mp)); 39 40endmodule 41 42 43module testmod 44 ( 45 input clk, 46 test_if.mp i 47 ); 48 49 always @(posedge clk) begin 50 i.data = 1'b0; 51 if (i.myfunc (1'b0)) begin 52 $write("*-* All Finished *-*\n"); 53 $finish; 54 end 55 else begin 56 $stop; 57 end 58 end 59endmodule 60