1// DESCRIPTION: Verilator: Verilog Test module for Issue#1609 2// 3// This file ONLY is placed into the Public Domain, for any use, 4// without warranty, 2020 by Julien Margetts. 5 6module t (/*AUTOARG*/ out, out2, in ); 7 8 input [9:0] in; 9 output reg [3:0] out; 10 output reg [3:0] out2; 11 12 // Should be no latch here since the input space is fully covered 13 14 always @* begin 15 casez (in) 16 10'b0000000000 : out = 4'h0; 17 10'b?????????1 : out = 4'h0; 18 10'b????????10 : out = 4'h1; 19 10'b???????100 : out = 4'h2; 20 10'b??????1000 : out = 4'h3; 21 10'b?????10000 : out = 4'h4; 22 10'b????100000 : out = 4'h5; 23 10'b???1000000 : out = 4'h6; 24 10'b??10000000 : out = 4'h7; 25 10'b?100000000 : out = 4'h8; 26 10'b1000000000 : out = 4'h9; 27 endcase 28 end 29 30 // Should detect a latch here since not all paths assign 31 // BUT we don't because warnOff(LATCH) is set for any always containing a 32 // complex case statement 33 34 always @* begin 35 casez (in) 36 10'b0000000000 : out2 = 4'h0; 37 10'b?????????1 : out2 = 4'h0; 38 10'b????????10 : out2 = 4'h1; 39 10'b???????100 : out2 = 4'h2; 40 10'b??????1000 : out2 = 4'h3; 41 10'b?????10000 : /* No assignement */ ; 42 10'b????100000 : out2 = 4'h5; 43 10'b???1000000 : out2 = 4'h6; 44 10'b??10000000 : out2 = 4'h7; 45 10'b?100000000 : out2 = 4'h8; 46 10'b1000000000 : out2 = 4'h9; 47 endcase 48 end 49 50endmodule 51