1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2010 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7`define STRINGIFY(x) `"x`"
8
9module t (/*AUTOARG*/
10   // Outputs
11   out,
12   // Inputs
13   in
14   );
15
16   input in;  // inputs don't get flagged as undriven
17   output out;  // outputs don't get flagged as unused
18
19   sub sub ();
20
21   // Check we don't warn about unused UDP signals
22   udp_mux2 udpsub (out, in, in, in);
23
24   // Check ignoreds mark as used
25   reg    sysused;
26   initial $bboxed(sysused);
27
28   // Check file IO.  The fopen is the "driver" all else a usage.
29   integer infile;
30   integer outfile;
31   initial begin
32      outfile = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/open.log"}, "w");
33      $fwrite(outfile, "1\n");
34      $fclose(outfile);
35      infile = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/open.log"}, "r");
36      if ($fgetc(infile) != "1") begin end
37   end
38
39   wire   _unused_ok;
40
41endmodule
42
43module sub;
44
45   wire pub /*verilator public*/;   // Ignore publics
46
47endmodule
48
49primitive udp_mux2 (q, a, b, s);
50   output q;
51   input  a, b, s;
52   table
53      //a b  s  :  out
54      1   ?  0  :  1 ;
55      0   ?  0  :  0 ;
56      ?   1  1  :  1 ;
57      ?   0  1  :  0 ;
58      0   0  x  :  0 ;
59      1   1  x  :  1 ;
60   endtable
61endprimitive
62