1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2017 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7interface dummy_if ();
8   logic sig_udrv;
9   logic sig_uusd;
10endinterface: dummy_if
11
12module sub
13  (
14   dummy_if dummy
15   );
16
17   assign dummy.sig_uusd = 1'b0 | dummy.sig_udrv;
18endmodule
19
20
21module t (/*AUTOARG*/);
22
23   dummy_if dummy ();
24
25   sub sub
26     (.dummy(dummy)
27      );
28
29endmodule
30