1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2006 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/
8   // Inputs
9   clk
10   );
11
12   input clk;
13
14   integer cyc; initial cyc = 0;
15   reg [63:0] crc;
16
17   integer 		i;
18   reg [63:0] 		mem [7:0];
19
20   always @ (posedge clk) begin
21      if (cyc==1) begin
22	 for (i=0; i<8; i=i+1) begin
23	    mem[i] <= 64'h0;
24	 end
25      end
26      else begin
27	 mem[0] <= crc;
28	 for (i=1; i<8; i=i+1) begin
29	    mem[i] <= mem[i-1];
30	 end
31      end
32   end
33
34   wire [63:0] outData = mem[7];
35
36   always @ (posedge clk) begin
37      //$write("[%0t] cyc==%0d crc=%b q=%x\n", $time, cyc, crc, outData);
38      cyc <= cyc + 1;
39      crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
40      if (cyc==0) begin
41	 // Setup
42	 crc <= 64'h5aef0c8d_d70a4497;
43      end
44      else if (cyc==90) begin
45	 if (outData != 64'h1265e3bddcd9bc27) $stop;
46      end
47      else if (cyc==91) begin
48	 if (outData != 64'h24cbc77bb9b3784e) $stop;
49      end
50      else if (cyc==92) begin
51      end
52      else if (cyc==93) begin
53      end
54      else if (cyc==94) begin
55      end
56      else if (cyc==99) begin
57	 $write("*-* All Finished *-*\n");
58	 $finish;
59      end
60   end
61
62endmodule
63