1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed into the Public Domain, for any use, 4// without warranty, 2019 by Driss Hafdi. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/ 8 // Inputs 9 clk 10 ); 11 12 input clk; 13 14 test #(.param(32'd0)) test_i; 15 16 initial begin 17 $write("*-* All Finished *-*\n"); 18 $finish; 19 end 20endmodule 21 22module test 23 #( 24 parameter logic param = 1'b0 25 ) (); 26endmodule 27