1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2014 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) 8 9module t (/*AUTOARG*/ 10 // Inputs 11 clk 12 ); 13 input clk; 14 15 integer cyc = 0; 16 reg [63:0] crc; 17 reg [63:0] sum; 18 /*AUTOWIRE*/ 19 20 generate 21 for (genvar width=1; width<=16; width++) begin 22 for (genvar amt=1; amt<=width; amt++) begin 23 Test #(.WIDTH(width), 24 .AMT(amt)) 25 test (.ins(crc[width-1:0])); 26 end 27 end 28 endgenerate 29 30 // Test loop 31 always @ (posedge clk) begin 32`ifdef TEST_VERBOSE 33 $write("[%0t] cyc==%0d crc=%x\n", 34 $time, cyc, crc); 35`endif 36 cyc <= cyc + 1; 37 crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; 38 if (cyc==0) begin 39 // Setup 40 crc <= 64'h5aef0c8d_d70a4497; 41 sum <= 64'h0; 42 end 43 else if (cyc<10) begin 44 sum <= 64'h0; 45 end 46 else if (cyc<90) begin 47 end 48 else if (cyc==99) begin 49 $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); 50 if (crc !== 64'hc77bb9b3784ea091) $stop; 51 // What checksum will we end up with (above print should match) 52`define EXPECTED_SUM 64'h0 53 if (sum !== `EXPECTED_SUM) $stop; 54 $write("*-* All Finished *-*\n"); 55 $finish; 56 end 57 end 58 59endmodule 60 61module Test (/*AUTOARG*/ 62 // Inputs 63 ins 64 ); 65 66 parameter WIDTH = 1; 67 parameter AMT = 1; 68 69 input [WIDTH-1:0] ins; 70 reg [WIDTH-1:0] got; 71 reg [WIDTH-1:0] expec; 72 int istart; 73 int bitn; 74 int ostart; 75 76 always @* begin 77 got = { << AMT {ins}}; 78 79 // Note always starts with right-most bit 80 expec = 0; 81 for (istart=0; istart<WIDTH; istart+=AMT) begin 82 ostart = WIDTH - AMT - istart; 83 if (ostart<0) ostart = 0; 84 for (bitn=0; bitn<AMT; bitn++) begin 85 if ((istart+bitn) < WIDTH 86 && (istart+bitn) >= 0 87 && (ostart+bitn) < WIDTH 88 && (ostart+bitn) >= 0) begin 89 expec[ostart+bitn] = ins[istart+bitn]; 90 end 91 end 92 end 93 94`ifdef TEST_VERBOSE 95 $write("[%0t] exp %0d'b%b got %0d'b%b = { << %0d { %0d'b%b }}\n", $time, WIDTH, expec, WIDTH, got, AMT, WIDTH, ins); 96`endif 97 `checkh(got, expec); 98 end 99 100endmodule 101