1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2021 by wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t;
8   parameter string ES = "";
9   parameter EI = "";  // B is an integer of width 8
10   parameter string OS = "O";
11   parameter OI = "O";  // B is an integer of width 8
12
13   parameter bit [31:0] NEST = "NEST";
14   parameter bit [31:0] TEST = "TEST";
15   bit [31:0] rest;
16   string s;
17
18   initial begin
19      $display(">< == >%s<", "");
20      $display(">< == >%s<", ES);
21      $display("> < == >%s<", EI);
22
23      if ($bits("") != 0) $stop;
24      if ($bits("A") != 8) $stop;
25      if ($bits(ES) != 0) $stop;
26      if ($bits(EI) != 8) $stop;
27      if ($bits(OS) != 8) $stop;
28      if ($bits(OI) != 8) $stop;
29
30      if (ES == "TEST") $stop;  // Illegal in some simulators as not both strings
31      if (EI == "TEST") $stop;
32      if (OS == "TEST") $stop;  // Illegal in some simulators as not both strings
33      // verilator lint_off WIDTH
34      if (OI == "TEST") $stop;
35      if (rest == "TEST") $stop;
36
37      if (ES == TEST) $stop;
38      if (EI == TEST) $stop;
39      if (OS == TEST) $stop;
40      if (OI == TEST) $stop;
41      if (rest == TEST) $stop;
42
43      $write("*-* All Finished *-*\n");
44      $finish;
45   end
46endmodule
47