1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed into the Public Domain, for any use, 4// without warranty, 2014 by Jonathon Donaldson. 5// SPDX-License-Identifier: CC0-1.0 6 7package my_funcs; 8 function automatic int simple_func (input int value); 9 begin 10 simple_func = value; 11 end 12 endfunction 13endpackage 14 15package my_module_types; 16 import my_funcs::*; 17 18 localparam MY_PARAM = 3; 19 localparam MY_PARAM2 /*verilator public*/ = simple_func(12); 20endpackage 21 22module t 23 import my_module_types::*; 24 ( 25 input i_clk, 26 input [MY_PARAM-1:0] i_d, 27 output logic [MY_PARAM-1:0] o_q 28 ); 29 30 always_ff @(posedge i_clk) 31 o_q <= i_d; 32 33 initial begin 34 $write("*-* All Finished *-*\n"); 35 $finish; 36 end 37endmodule 38