1 2\section{Yosys by example -- Advanced Synthesis} 3 4\begin{frame} 5\sectionpage 6\end{frame} 7 8\begin{frame}{Overview} 9This section contains 4 subsections: 10\begin{itemize} 11\item Using selections 12\item Advanced uses of techmap 13\item Coarse-grain synthesis 14\item Automatic design changes 15\end{itemize} 16\end{frame} 17 18%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 19 20\subsection{Using selections} 21 22\begin{frame} 23\subsectionpage 24\subsectionpagesuffix 25\end{frame} 26 27\subsubsection{Simple selections} 28 29\begin{frame}[fragile]{\subsubsecname} 30Most Yosys commands make use of the ``selection framework'' of Yosys. It can be used 31to apply commands only to part of the design. For example: 32 33\medskip 34\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] 35delete # will delete the whole design, but 36 37delete foobar # will only delete the module foobar. 38\end{lstlisting} 39 40\bigskip 41The {\tt select} command can be used to create a selection for subsequent 42commands. For example: 43 44\medskip 45\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] 46select foobar # select the module foobar 47delete # delete selected objects 48select -clear # reset selection (select whole design) 49\end{lstlisting} 50\end{frame} 51 52\subsubsection{Selection by object name} 53 54\begin{frame}[fragile]{\subsubsecname} 55The easiest way to select objects is by object name. This is usually only done 56in synthesis scripts that are hand-tailored for a specific design. 57 58\bigskip 59\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] 60select foobar # select module foobar 61select foo* # select all modules whose names start with foo 62select foo*/bar* # select all objects matching bar* from modules matching foo* 63select */clk # select objects named clk from all modules 64\end{lstlisting} 65\end{frame} 66 67\subsubsection{Module and design context} 68 69\begin{frame}[fragile]{\subsubsecname} 70Commands can be executed in {\it module\/} or {\it design\/} context. Until now all 71commands have been executed in design context. The {\tt cd} command can be used 72to switch to module context. 73 74\bigskip 75In module context all commands only effect the active module. Objects in the module 76are selected without the {\tt <module\_name>/} prefix. For example: 77 78\bigskip 79\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] 80cd foo # switch to module foo 81delete bar # delete object foo/bar 82 83cd mycpu # switch to module mycpu 84dump reg_* # print details on all objects whose names start with reg_ 85 86cd .. # switch back to design 87\end{lstlisting} 88 89\bigskip 90Note: Most synthesis scripts never switch to module context. But it is a very powerful 91tool for interactive design investigation. 92\end{frame} 93 94\subsubsection{Selecting by object property or type} 95 96\begin{frame}[fragile]{\subsubsecname} 97Special patterns can be used to select by object property or type. For example: 98 99\bigskip 100\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] 101select w:reg_* # select all wires whose names start with reg_ 102select a:foobar # select all objects with the attribute foobar set 103select a:foobar=42 # select all objects with the attribute foobar set to 42 104select A:blabla # select all modules with the attribute blabla set 105select foo/t:$add # select all $add cells from the module foo 106\end{lstlisting} 107 108\bigskip 109A complete list of this pattern expressions can be found in the command 110reference to the {\tt select} command. 111\end{frame} 112 113\subsubsection{Combining selection} 114 115\begin{frame}[fragile]{\subsubsecname} 116When more than one selection expression is used in one statement, then they are 117pushed on a stack. The final elements on the stack are combined into a union: 118 119\medskip 120\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] 121select t:$dff r:WIDTH>1 # all cells of type $dff and/or with a parameter WIDTH > 1 122\end{lstlisting} 123 124\bigskip 125Special \%-commands can be used to combine the elements on the stack: 126 127\medskip 128\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] 129select t:$dff r:WIDTH>1 %i # all cells of type $dff *AND* with a parameter WIDTH > 1 130\end{lstlisting} 131 132\medskip 133\begin{block}{Examples for {\tt \%}-codes (see {\tt help select} for full list)} 134{\tt \%u} \dotfill union of top two elements on stack -- pop 2, push 1 \\ 135{\tt \%d} \dotfill difference of top two elements on stack -- pop 2, push 1 \\ 136{\tt \%i} \dotfill intersection of top two elements on stack -- pop 2, push 1 \\ 137{\tt \%n} \dotfill inverse of top element on stack -- pop 1, push 1 \\ 138\end{block} 139\end{frame} 140 141\subsubsection{Expanding selections} 142 143\begin{frame}[fragile]{\subsubsecname} 144Selections of cells and wires can be expanded along connections using {\tt \%}-codes 145for selecting input cones ({\tt \%ci}), output cones ({\tt \%co}), or both ({\tt \%x}). 146 147\medskip 148\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] 149# select all wires that are inputs to $add cells 150select t:$add %ci w:* %i 151\end{lstlisting} 152 153\bigskip 154Additional constraints such as port names can be specified. 155 156\medskip 157\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] 158# select all wires that connect a "Q" output with a "D" input 159select c:* %co:+[Q] w:* %i c:* %ci:+[D] w:* %i %i 160 161# select the multiplexer tree that drives the signal 'state' 162select state %ci*:+$mux,$pmux[A,B,Y] 163\end{lstlisting} 164 165\bigskip 166See {\tt help select} for full documentation of this expressions. 167\end{frame} 168 169\subsubsection{Incremental selection} 170 171\begin{frame}[fragile]{\subsubsecname} 172Sometimes a selection can most easily be described by a series of add/delete operations. 173The commands {\tt select -add} and {\tt select -del} respectively add or remove objects 174from the current selection instead of overwriting it. 175 176\medskip 177\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] 178select -none # start with an empty selection 179select -add reg_* # select a bunch of objects 180select -del reg_42 # but not this one 181select -add state %ci # and add mor stuff 182\end{lstlisting} 183 184\bigskip 185Within a select expression the token {\tt \%} can be used to push the previous selection 186on the stack. 187 188\medskip 189\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] 190select t:$add t:$sub # select all $add and $sub cells 191select % %ci % %d # select only the input wires to those cells 192\end{lstlisting} 193\end{frame} 194 195\subsubsection{Creating selection variables} 196 197\begin{frame}[fragile]{\subsubsecname} 198Selections can be stored under a name with the {\tt select -set <name>} 199command. The stored selections can be used in later select expressions 200using the syntax {\tt @<name>}. 201 202\medskip 203\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] 204select -set cone_a state_a %ci*:-$dff # set @cone_a to the input cone of state_a 205select -set cone_b state_b %ci*:-$dff # set @cone_b to the input cone of state_b 206select @cone_a @cone_b %i # select the objects that are in both cones 207\end{lstlisting} 208 209\bigskip 210Remember that select expressions can also be used directly as arguments to most 211commands. Some commands also except a single select argument to some options. 212In those cases selection variables must be used to capture more complex selections. 213 214\medskip 215\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] 216dump @cone_a @cone_b 217 218select -set cone_ab @cone_a @cone_b %i 219show -color red @cone_ab -color magenta @cone_a -color blue @cone_b 220\end{lstlisting} 221\end{frame} 222 223\begin{frame}[fragile]{\subsubsecname{} -- Example} 224\begin{columns} 225\column[t]{4cm} 226\lstinputlisting[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/select.v} 227\column[t]{7cm} 228\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExAdv/select.ys} 229\end{columns} 230\hfil\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/select.pdf} 231\end{frame} 232 233%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 234 235\subsection{Advanced uses of techmap} 236 237\begin{frame} 238\subsectionpage 239\subsectionpagesuffix 240\end{frame} 241 242\subsubsection{Introduction to techmap} 243 244\begin{frame}{\subsubsecname} 245\begin{itemize} 246\item 247The {\tt techmap} command replaces cells in the design with implementations given 248as Verilog code (called ``map files''). It can replace Yosys' internal cell 249types (such as {\tt \$or}) as well as user-defined cell types. 250\medskip\item 251Verilog parameters are used extensively to customize the internal cell types. 252\medskip\item 253Additional special parameters are used by techmap to communicate meta-data to the 254map files. 255\medskip\item 256Special wires are used to instruct techmap how to handle a module in the map file. 257\medskip\item 258Generate blocks and recursion are powerful tools for writing map files. 259\end{itemize} 260\end{frame} 261 262\begin{frame}[t]{\subsubsecname{} -- Example 1/2} 263\vskip-0.2cm 264To map the Verilog OR-reduction operator to 3-input OR gates: 265\vskip-0.2cm 266\begin{columns} 267\column[t]{0.35\linewidth} 268\lstinputlisting[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, lastline=24]{PRESENTATION_ExAdv/red_or3x1_map.v} 269\column[t]{0.65\linewidth} 270\lstinputlisting[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=25]{PRESENTATION_ExAdv/red_or3x1_map.v} 271\end{columns} 272\end{frame} 273 274\begin{frame}[t]{\subsubsecname{} -- Example 2/2} 275\vbox to 0cm{ 276\hfil\includegraphics[width=10cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/red_or3x1.pdf} 277\vss 278} 279\begin{columns} 280\column[t]{6cm} 281\column[t]{4cm} 282\vskip-0.6cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, firstline=4, lastline=4, frame=single]{PRESENTATION_ExAdv/red_or3x1_test.ys} 283\vskip-0.2cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/red_or3x1_test.v} 284\end{columns} 285\end{frame} 286 287\subsubsection{Conditional techmap} 288 289\begin{frame}{\subsubsecname} 290\begin{itemize} 291\item In some cases only cells with certain properties should be substituted. 292\medskip 293\item The special wire {\tt \_TECHMAP\_FAIL\_} can be used to disable a module 294in the map file for a certain set of parameters. 295\medskip 296\item The wire {\tt \_TECHMAP\_FAIL\_} must be set to a constant value. If it 297is non-zero then the module is disabled for this set of parameters. 298\medskip 299\item Example use-cases: 300\begin{itemize} 301\item coarse-grain cell types that only operate on certain bit widths 302\item memory resources for different memory geometries (width, depth, ports, etc.) 303\end{itemize} 304\end{itemize} 305\end{frame} 306 307\begin{frame}[t]{\subsubsecname{} -- Example} 308\vbox to 0cm{ 309\vskip-0.5cm 310\hfill\includegraphics[width=6cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/sym_mul.pdf} 311\vss 312} 313\vskip-0.5cm 314\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/sym_mul_map.v} 315\begin{columns} 316\column[t]{6cm} 317\vskip-0.5cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/sym_mul_test.v} 318\column[t]{4cm} 319\vskip-0.5cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=4]{PRESENTATION_ExAdv/sym_mul_test.ys} 320\end{columns} 321\end{frame} 322 323\subsubsection{Scripting in map modules} 324 325\begin{frame}{\subsubsecname} 326\begin{itemize} 327\item The special wires {\tt \_TECHMAP\_DO\_*} can be used to run Yosys scripts 328in the context of the replacement module. 329\medskip 330\item The wire that comes first in alphabetical oder is interpreted as string (must 331be connected to constants) that is executed as script. Then the wire is removed. Repeat. 332\medskip 333\item You can even call techmap recursively! 334\medskip 335\item Example use-cases: 336\begin{itemize} 337\item Using always blocks in map module: call {\tt proc} 338\item Perform expensive optimizations (such as {\tt freduce}) on cells where 339this is known to work well. 340\item Interacting with custom commands. 341\end{itemize} 342\end{itemize} 343 344\scriptsize 345PROTIP: Commands such as {\tt shell}, {\tt show -pause}, and {\tt dump} can be use 346in the {\tt \_TECHMAP\_DO\_*} scripts for debugging map modules. 347\end{frame} 348 349\begin{frame}[t]{\subsubsecname{} -- Example} 350\vbox to 0cm{ 351\vskip4.2cm 352\hskip0.5cm\includegraphics[width=10cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/mymul.pdf} 353\vss 354} 355\vskip-0.6cm 356\begin{columns} 357\column[t]{6cm} 358\vskip-0.6cm 359\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/mymul_map.v} 360\column[t]{4.2cm} 361\vskip-0.6cm 362\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/mymul_test.v} 363\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=5]{PRESENTATION_ExAdv/mymul_test.ys} 364\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, frame=single, language=ys, firstline=7, lastline=12]{PRESENTATION_ExAdv/mymul_test.ys} 365\end{columns} 366\end{frame} 367 368\subsubsection{Handling constant inputs} 369 370\begin{frame}{\subsubsecname} 371\begin{itemize} 372\item The special parameters {\tt \_TECHMAP\_CONSTMSK\_\it <port-name>\tt \_} and 373{\tt \_TECHMAP\_CONSTVAL\_\it <port-name>\tt \_} can be used to handle constant 374input values to cells. 375\medskip 376\item The former contains 1-bits for all constant input bits on the port. 377\medskip 378\item The latter contains the constant bits or undef (x) for non-constant bits. 379\medskip 380\item Example use-cases: 381\begin{itemize} 382\item Converting arithmetic (for example multiply to shift) 383\item Identify constant addresses or enable bits in memory interfaces. 384\end{itemize} 385\end{itemize} 386\end{frame} 387 388\begin{frame}[t]{\subsubsecname{} -- Example} 389\vbox to 0cm{ 390\vskip5.2cm 391\hskip6.5cm\includegraphics[width=5cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/mulshift.pdf} 392\vss 393} 394\vskip-0.6cm 395\begin{columns} 396\column[t]{6cm} 397\vskip-0.4cm 398\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/mulshift_map.v} 399\column[t]{4.2cm} 400\vskip-0.6cm 401\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/mulshift_test.v} 402\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=5]{PRESENTATION_ExAdv/mulshift_test.ys} 403\end{columns} 404\end{frame} 405 406\subsubsection{Handling shorted inputs} 407 408\begin{frame}{\subsubsecname} 409\begin{itemize} 410\item The special parameters {\tt \_TECHMAP\_BITS\_CONNMAP\_} and 411{\tt \_TECHMAP\_CONNMAP\_\it <port-name>\tt \_} can be used to handle shorted inputs. 412\medskip 413\item Each bit of the port correlates to an {\tt \_TECHMAP\_BITS\_CONNMAP\_} bits wide 414number in {\tt \_TECHMAP\_CONNMAP\_\it <port-name>\tt \_}. 415\medskip 416\item Each unique signal bit is assigned its own number. Identical fields in the {\tt 417\_TECHMAP\_CONNMAP\_\it <port-name>\tt \_} parameters mean shorted signal bits. 418\medskip 419\item The numbers 0-3 are reserved for {\tt 0}, {\tt 1}, {\tt x}, and {\tt z} respectively. 420\medskip 421\item Example use-cases: 422\begin{itemize} 423\item Detecting shared clock or control signals in memory interfaces. 424\item In some cases this can be used for for optimization. 425\end{itemize} 426\end{itemize} 427\end{frame} 428 429\begin{frame}[t]{\subsubsecname{} -- Example} 430\vbox to 0cm{ 431\vskip4.5cm 432\hskip6.5cm\includegraphics[width=5cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/addshift.pdf} 433\vss 434} 435\vskip-0.6cm 436\begin{columns} 437\column[t]{6cm} 438\vskip-0.4cm 439\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/addshift_map.v} 440\column[t]{4.2cm} 441\vskip-0.6cm 442\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/addshift_test.v} 443\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=5]{PRESENTATION_ExAdv/addshift_test.ys} 444\end{columns} 445\end{frame} 446 447\subsubsection{Notes on using techmap} 448 449\begin{frame}{\subsubsecname} 450\begin{itemize} 451\item Don't use positional cell parameters in map modules. 452\medskip 453\item Don't try to implement basic logic optimization with techmap. \\ 454{\small (So the OR-reduce using OR3X1 cells map was actually a bad example.)} 455\medskip 456\item You can use the {\tt \$\_\,\_}-prefix for internal cell types to avoid 457collisions with the user-namespace. But always use two underscores or the 458internal consistency checker will trigger on this cells. 459\medskip 460\item Techmap has two major use cases: 461\begin{itemize} 462\item Creating good logic-level representation of arithmetic functions. \\ 463This also means using dedicated hardware resources such as half- and full-adder 464cells in ASICS or dedicated carry logic in FPGAs. 465\smallskip 466\item Mapping of coarse-grain resources such as block memory or DSP cells. 467\end{itemize} 468\end{itemize} 469\end{frame} 470 471%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 472 473\subsection{Coarse-grain synthesis} 474 475\begin{frame} 476\subsectionpage 477\subsectionpagesuffix 478\end{frame} 479 480\subsubsection{Intro to coarse-grain synthesis} 481 482\begin{frame}[fragile]{\subsubsecname} 483In coarse-grain synthesis the target architecture has cells of the same 484complexity or larger complexity than the internal RTL representation. 485 486For example: 487\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog] 488 wire [15:0] a, b; 489 wire [31:0] c, y; 490 assign y = a * b + c; 491\end{lstlisting} 492 493This circuit contains two cells in the RTL representation: one multiplier and 494one adder. In some architectures this circuit can be implemented using 495a single circuit element, for example an FPGA DSP core. Coarse grain synthesis 496is this mapping of groups of circuit elements to larger components. 497 498\bigskip 499Fine-grain synthesis would be matching the circuit elements to smaller 500components, such as LUTs, gates, or half- and full-adders. 501\end{frame} 502 503\subsubsection{The extract pass} 504 505\begin{frame}{\subsubsecname} 506\begin{itemize} 507\item Like the {\tt techmap} pass, the {\tt extract} pass is called with 508a map file. It compares the circuits inside the modules of the map file 509with the design and looks for sub-circuits in the design that match any 510of the modules in the map file. 511\bigskip 512\item If a match is found, the {\tt extract} pass will replace the matching 513subcircuit with an instance of the module from the map file. 514\bigskip 515\item In a way the {\tt extract} pass is the inverse of the techmap pass. 516\end{itemize} 517\end{frame} 518 519\begin{frame}[t, fragile]{\subsubsecname{} -- Example 1/2} 520\vbox to 0cm{ 521\vskip2cm 522\begin{tikzpicture} 523 \node at (0,0) {\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_00a.pdf}}; 524 \node at (3,-3) {\includegraphics[width=8cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_00b.pdf}}; 525 \draw[yshift=0.2cm,thick,-latex] (1,-1) -- (2,-2); 526\end{tikzpicture} 527\vss} 528\vskip-1.2cm 529\begin{columns} 530\column[t]{5cm} 531\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/macc_simple_test.v} 532\column[t]{5cm} 533\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/macc_simple_xmap.v} 534\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys] 535read_verilog macc_simple_test.v 536hierarchy -check -top test 537 538extract -map macc_simple_xmap.v;; 539\end{lstlisting} 540\end{columns} 541\end{frame} 542 543\begin{frame}[fragile]{\subsubsecname{} -- Example 2/2} 544\hfil\begin{tabular}{cc} 545\fbox{\hbox to 5cm {\lstinputlisting[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/macc_simple_test_01.v}}} & 546\fbox{\hbox to 5cm {\lstinputlisting[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/macc_simple_test_02.v}}} \\ 547$\downarrow$ & $\downarrow$ \\ 548\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_01a.pdf}} & 549\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_02a.pdf}} \\ 550$\downarrow$ & $\downarrow$ \\ 551\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_01b.pdf}} & 552\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_02b.pdf}} \\ 553\end{tabular} 554\end{frame} 555 556\subsubsection{The wrap-extract-unwrap method} 557 558\begin{frame}{\subsubsecname} 559\scriptsize 560Often a coarse-grain element has a constant bit-width, but can be used to 561implement operations with a smaller bit-width. For example, a 18x25-bit multiplier 562can also be used to implement 16x20-bit multiplication. 563 564\bigskip 565A way of mapping such elements in coarse grain synthesis is the wrap-extract-unwrap method: 566 567\begin{itemize} 568\item {\bf wrap} \\ 569Identify candidate-cells in the circuit and wrap them in a cell with a constant 570wider bit-width using {\tt techmap}. The wrappers use the same parameters as the original cell, so 571the information about the original width of the ports is preserved. \\ 572Then use the {\tt connwrappers} command to connect up the bit-extended in- and 573outputs of the wrapper cells. 574\item {\bf extract} \\ 575Now all operations are encoded using the same bit-width as the coarse grain element. The {\tt 576extract} command can be used to replace circuits with cells of the target architecture. 577\item {\bf unwrap} \\ 578The remaining wrapper cell can be unwrapped using {\tt techmap}. 579\end{itemize} 580 581\bigskip 582The following sides detail an example that shows how to map MACC operations of 583arbitrary size to MACC cells with a 18x25-bit multiplier and a 48-bit adder (such as 584the Xilinx DSP48 cells). 585\end{frame} 586 587\subsubsection{Example: DSP48\_MACC} 588 589\begin{frame}[t, fragile]{\subsubsecname{} -- 1/13} 590Preconditioning: {\tt macc\_xilinx\_swap\_map.v} \\ 591Make sure {\tt A} is the smaller port on all multipliers 592 593\begin{columns} 594\column{5cm} 595\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, lastline=15]{PRESENTATION_ExAdv/macc_xilinx_swap_map.v} 596\column{5cm} 597\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=16]{PRESENTATION_ExAdv/macc_xilinx_swap_map.v} 598\end{columns} 599\end{frame} 600 601\begin{frame}[t, fragile]{\subsubsecname{} -- 2/13} 602Wrapping multipliers: {\tt macc\_xilinx\_wrap\_map.v} 603 604\begin{columns} 605\column[t]{5cm} 606\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, lastline=23]{PRESENTATION_ExAdv/macc_xilinx_wrap_map.v} 607\column[t]{5cm} 608\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=24, lastline=46]{PRESENTATION_ExAdv/macc_xilinx_wrap_map.v} 609\end{columns} 610\end{frame} 611 612\begin{frame}[t, fragile]{\subsubsecname{} -- 3/13} 613Wrapping adders: {\tt macc\_xilinx\_wrap\_map.v} 614 615\begin{columns} 616\column[t]{5cm} 617\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=48, lastline=67]{PRESENTATION_ExAdv/macc_xilinx_wrap_map.v} 618\column[t]{5cm} 619\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=68, lastline=89]{PRESENTATION_ExAdv/macc_xilinx_wrap_map.v} 620\end{columns} 621\end{frame} 622 623\begin{frame}[t, fragile]{\subsubsecname{} -- 4/13} 624Extract: {\tt macc\_xilinx\_xmap.v} 625 626\lstinputlisting[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=1, lastline=17]{PRESENTATION_ExAdv/macc_xilinx_xmap.v} 627 628.. simply use the same wrapping commands on this module as on the design to create a template for the {\tt extract} command. 629\end{frame} 630 631\begin{frame}[t, fragile]{\subsubsecname{} -- 5/13} 632Unwrapping multipliers: {\tt macc\_xilinx\_unwrap\_map.v} 633 634\begin{columns} 635\column[t]{5cm} 636\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=1, lastline=17]{PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v} 637\column[t]{5cm} 638\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=18, lastline=30]{PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v} 639\end{columns} 640\end{frame} 641 642\begin{frame}[t, fragile]{\subsubsecname{} -- 6/13} 643Unwrapping adders: {\tt macc\_xilinx\_unwrap\_map.v} 644 645\begin{columns} 646\column[t]{5cm} 647\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=32, lastline=48]{PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v} 648\column[t]{5cm} 649\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=49, lastline=61]{PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v} 650\end{columns} 651\end{frame} 652 653\begin{frame}[fragile]{\subsubsecname{} -- 7/13} 654\hfil\begin{tabular}{cc} 655{\tt test1} & {\tt test2} \\ 656\fbox{\hbox to 5cm {\lstinputlisting[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, firstline=1, lastline=6, language=verilog]{PRESENTATION_ExAdv/macc_xilinx_test.v}}} & 657\fbox{\hbox to 5cm {\lstinputlisting[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, firstline=8, lastline=13, language=verilog]{PRESENTATION_ExAdv/macc_xilinx_test.v}}} \\ 658$\downarrow$ & $\downarrow$ \\ 659\end{tabular} 660\vskip-0.5cm 661\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] 662 read_verilog macc_xilinx_test.v 663 hierarchy -check 664\end{lstlisting} 665\vskip-0.5cm 666\hfil\begin{tabular}{cc} 667$\downarrow$ & $\downarrow$ \\ 668\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1a.pdf}} & 669\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2a.pdf}} \\ 670\end{tabular} 671\end{frame} 672 673\begin{frame}[fragile]{\subsubsecname{} -- 8/13} 674\hfil\begin{tabular}{cc} 675{\tt test1} & {\tt test2} \\ 676\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1a.pdf}} & 677\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2a.pdf}} \\ 678$\downarrow$ & $\downarrow$ \\ 679\end{tabular} 680\vskip-0.2cm 681\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] 682 techmap -map macc_xilinx_swap_map.v ;; 683\end{lstlisting} 684\vskip-0.2cm 685\hfil\begin{tabular}{cc} 686$\downarrow$ & $\downarrow$ \\ 687\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1b.pdf}} & 688\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2b.pdf}} \\ 689\end{tabular} 690\end{frame} 691 692\begin{frame}[t, fragile]{\subsubsecname{} -- 9/13} 693Wrapping in {\tt test1}: 694\begin{columns} 695\column[t]{5cm} 696\vbox to 0cm{\fbox{\includegraphics[width=4.5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1b.pdf}}\vss} 697\column[t]{6cm} 698\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] 699techmap -map macc_xilinx_wrap_map.v 700 701connwrappers -unsigned $__mul_wrapper \ 702 Y Y_WIDTH \ 703 -unsigned $__add_wrapper \ 704 Y Y_WIDTH ;; 705\end{lstlisting} 706\end{columns} 707 708\vskip1cm 709\hfil\includegraphics[width=\linewidth,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1c.pdf} 710\end{frame} 711 712\begin{frame}[t, fragile]{\subsubsecname{} -- 10/13} 713Wrapping in {\tt test2}: 714\begin{columns} 715\column[t]{5cm} 716\vbox to 0cm{\fbox{\includegraphics[width=4.5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2b.pdf}}\vss} 717\column[t]{6cm} 718\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] 719techmap -map macc_xilinx_wrap_map.v 720 721connwrappers -unsigned $__mul_wrapper \ 722 Y Y_WIDTH \ 723 -unsigned $__add_wrapper \ 724 Y Y_WIDTH ;; 725\end{lstlisting} 726\end{columns} 727 728\vskip1cm 729\hfil\includegraphics[width=\linewidth,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2c.pdf} 730\end{frame} 731 732\begin{frame}[t, fragile]{\subsubsecname{} -- 11/13} 733Extract in {\tt test1}: 734\begin{columns} 735\column[t]{4.5cm} 736\vbox to 0cm{ 737\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] 738design -push 739read_verilog macc_xilinx_xmap.v 740techmap -map macc_xilinx_swap_map.v 741techmap -map macc_xilinx_wrap_map.v;; 742design -save __macc_xilinx_xmap 743design -pop 744\end{lstlisting} 745\vss} 746\column[t]{5.5cm} 747\vskip-1cm 748\begin{lstlisting}[linewidth=5.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] 749extract -constports -ignore_parameters \ 750 -map %__macc_xilinx_xmap \ 751 -swap $__add_wrapper A,B ;; 752\end{lstlisting} 753\vbox to 0cm{\fbox{\includegraphics[width=4.5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1c.pdf}}\vss} 754\end{columns} 755 756\vskip2cm 757\hfil\includegraphics[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1d.pdf} 758\end{frame} 759 760\begin{frame}[t, fragile]{\subsubsecname{} -- 12/13} 761Extract in {\tt test2}: 762\begin{columns} 763\column[t]{4.5cm} 764\vbox to 0cm{ 765\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] 766design -push 767read_verilog macc_xilinx_xmap.v 768techmap -map macc_xilinx_swap_map.v 769techmap -map macc_xilinx_wrap_map.v;; 770design -save __macc_xilinx_xmap 771design -pop 772\end{lstlisting} 773\vss} 774\column[t]{5.5cm} 775\vskip-1cm 776\begin{lstlisting}[linewidth=5.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] 777extract -constports -ignore_parameters \ 778 -map %__macc_xilinx_xmap \ 779 -swap $__add_wrapper A,B ;; 780\end{lstlisting} 781\vbox to 0cm{\fbox{\includegraphics[width=4.5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2c.pdf}}\vss} 782\end{columns} 783 784\vskip2cm 785\hfil\includegraphics[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2d.pdf} 786\end{frame} 787 788\begin{frame}[t, fragile]{\subsubsecname{} -- 13/13} 789Unwrap in {\tt test2}: 790 791\hfil\begin{tikzpicture} 792\node at (0,0) {\includegraphics[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2d.pdf}}; 793\node at (0,-4) {\includegraphics[width=8cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2e.pdf}}; 794\node at (1,-1.7) {\begin{lstlisting}[linewidth=5.5cm, frame=single, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] 795techmap -map macc_xilinx_unwrap_map.v ;; 796\end{lstlisting}}; 797\draw[-latex] (4,-0.7) .. controls (5,-1.7) .. (4,-2.7); 798\end{tikzpicture} 799\end{frame} 800 801 802%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 803 804\subsection{Automatic design changes} 805 806\begin{frame} 807\subsectionpage 808\subsectionpagesuffix 809\end{frame} 810 811\subsubsection{Changing the design from Yosys} 812 813\begin{frame}{\subsubsecname} 814Yosys commands can be used to change the design in memory. Examples of this are: 815 816\begin{itemize} 817\item {\bf Changes in design hierarchy} \\ 818Commands such as {\tt flatten} and {\tt submod} can be used to change the design hierarchy, i.e. 819flatten the hierarchy or moving parts of a module to a submodule. This has applications in synthesis 820scripts as well as in reverse engineering and analysis. 821 822\item {\bf Behavioral changes} \\ 823Commands such as {\tt techmap} can be used to make behavioral changes to the design, for example 824changing asynchronous resets to synchronous resets. This has applications in design space exploration 825(evaluation of various architectures for one circuit). 826\end{itemize} 827\end{frame} 828 829\subsubsection{Example: Async reset to sync reset} 830 831\begin{frame}[t, fragile]{\subsubsecname} 832The following techmap map file replaces all positive-edge async reset flip-flops with 833positive-edge sync reset flip-flops. The code is taken from the example Yosys script 834for ASIC synthesis of the Amber ARMv2 CPU. 835 836\begin{columns} 837\column[t]{6cm} 838\vbox to 0cm{ 839\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=Verilog] 840(* techmap_celltype = "$adff" *) 841module adff2dff (CLK, ARST, D, Q); 842 843 parameter WIDTH = 1; 844 parameter CLK_POLARITY = 1; 845 parameter ARST_POLARITY = 1; 846 parameter ARST_VALUE = 0; 847 848 input CLK, ARST; 849 input [WIDTH-1:0] D; 850 output reg [WIDTH-1:0] Q; 851 852 wire [1023:0] _TECHMAP_DO_ = "proc"; 853 854 wire _TECHMAP_FAIL_ = !CLK_POLARITY || !ARST_POLARITY; 855\end{lstlisting} 856\vss} 857\column[t]{4cm} 858\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=Verilog] 859// ..continued.. 860 861 862 always @(posedge CLK) 863 if (ARST) 864 Q <= ARST_VALUE; 865 else 866 <= D; 867 868endmodule 869\end{lstlisting} 870\end{columns} 871 872\end{frame} 873 874%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 875 876\subsection{Summary} 877 878\begin{frame}{\subsecname} 879\begin{itemize} 880\item A lot can be achieved in Yosys just with the standard set of commands. 881\item The commands {\tt techmap} and {\tt extract} can be used to prototype many complex synthesis tasks. 882\end{itemize} 883 884\bigskip 885\bigskip 886\begin{center} 887Questions? 888\end{center} 889 890\bigskip 891\bigskip 892\begin{center} 893\url{https://yosyshq.net/yosys/} 894\end{center} 895\end{frame} 896 897