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53pdftitle={Yosys Manual},%
54pdfauthor={Claire Xenia Wolf},%
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123\begin{document}
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136\begin{center}
137\bf\Huge Yosys Manual
138
139\bigskip
140\large Claire Xenia Wolf
141\end{center}
142
143\vfil\null
144\eject
145
146\chapter*{Abstract}
147Most of today's digital design is done in HDL code (mostly Verilog or VHDL) and
148with the help of HDL synthesis tools.
149
150In special cases such as synthesis for coarse-grain cell libraries or when
151testing new synthesis algorithms it might be necessary to write a custom HDL
152synthesis tool or add new features to an existing one. In these cases the
153availability of a Free and Open Source (FOSS) synthesis tool that can be used
154as basis for custom tools would be helpful.
155
156In the absence of such a tool, the Yosys Open SYnthesis Suite (Yosys) was
157developed. This document covers the design and implementation of this tool.
158At the moment the main focus of Yosys lies on the high-level aspects of
159digital synthesis. The pre-existing FOSS logic-synthesis tool ABC is used
160by Yosys to perform advanced gate-level optimizations.
161
162An evaluation of Yosys based on real-world designs is included. It is shown
163that Yosys can be used as-is to synthesize such designs. The results produced
164by Yosys in this tests where successfully verified using formal verification
165and are comparable in quality to the results produced by a commercial
166synthesis tool.
167
168\bigskip
169
170This document was originally published as bachelor thesis at the Vienna
171University of Technology \cite{BACC}.
172
173\chapter*{Abbreviations}
174\begin{tabular}{ll}
175AIG         & And-Inverter-Graph \\
176ASIC        & Application-Specific Integrated Circuit \\
177AST         & Abstract Syntax Tree \\
178BDD         & Binary Decision Diagram \\
179BLIF        & Berkeley Logic Interchange Format \\
180EDA         & Electronic Design Automation \\
181EDIF        & Electronic Design Interchange Format \\
182ER Diagram  & Entity-Relationship Diagram \\
183FOSS        & Free and Open-Source Software \\
184FPGA        & Field-Programmable Gate Array \\
185FSM         & Finite-state machine \\
186HDL         & Hardware Description Language \\
187LPM         & Library of Parameterized Modules \\
188RTLIL       & RTL Intermediate Language \\
189RTL         & Register Transfer Level \\
190SAT         & Satisfiability Problem \\
191% SSA       & Static Single Assignment Form \\
192VHDL        & VHSIC Hardware Description Language \\
193VHSIC       & Very-High-Speed Integrated Circuit \\
194YOSYS       & Yosys Open SYnthesis Suite \\
195\end{tabular}
196
197\tableofcontents
198
199\include{CHAPTER_Intro}
200\include{CHAPTER_Basics}
201\include{CHAPTER_Approach}
202\include{CHAPTER_Overview}
203\include{CHAPTER_CellLib}
204\include{CHAPTER_Prog}
205
206\include{CHAPTER_Verilog}
207\include{CHAPTER_Optimize}
208\include{CHAPTER_Techmap}
209% \include{CHAPTER_Eval}
210
211\appendix
212
213\include{CHAPTER_Auxlibs}
214\include{CHAPTER_Auxprogs}
215
216\chapter{Command Reference Manual}
217\label{commandref}
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230\end{document}
231