1\documentclass[oneside,a4paper]{book} 2 3\usepackage[T1]{fontenc} % required for luximono! 4\usepackage{lmodern} 5\usepackage[scaled=0.8]{luximono} % typewriter font with bold face 6 7% To install the luximono font files: 8% getnonfreefonts-sys --all or 9% getnonfreefonts-sys luximono 10% 11% when there are trouble you might need to: 12% - Create /etc/texmf/updmap.d/99local-luximono.cfg 13% containing the single line: Map ul9.map 14% - Run update-updmap followed by mktexlsr and updmap-sys 15% 16% This commands must be executed as root with a root environment 17% (i.e. run "sudo su" and then execute the commands in the root 18% shell, don't just prefix the commands with "sudo"). 19 20% formats the text according the set language 21\usepackage[english]{babel} 22\usepackage[table,usenames]{xcolor} 23% generates indices with the "\index" command 24\usepackage{makeidx} 25% enables import of graphics. We use pdflatex here so do the pdf optimisation. 26%\usepackage[dvips]{graphicx} 27\usepackage[pdftex]{graphicx} 28\usepackage{pdfpages} 29% includes floating objects like tables and figures. 30\usepackage{float} 31% for generating subfigures with ohne indented captions 32\usepackage[hang]{subfigure} 33% redefines and smartens captions of figures and tables (indentation, smaller and boldface) 34\usepackage[hang,small,bf,center]{caption} 35% enables tabstops and the numeration of lines 36\usepackage{moreverb} 37% enables user defined header and footer lines (former "fancyheadings") 38\usepackage{fancyhdr} 39% Some smart mathematical stuff 40\usepackage{amsmath} 41% Package for rotating several objects 42\usepackage{rotating} 43\usepackage{natbib} 44\usepackage{epsf} 45\usepackage{dsfont} 46\usepackage[algochapter, boxruled, vlined]{algorithm2e} 47%Activating and setting of character protruding - if you like 48%\usepackage[activate,DVIoutput]{pdfcprot} 49% If you really need special chars... 50\usepackage[latin1]{inputenc} 51% Hyperlinks 52\usepackage[colorlinks,hyperindex,plainpages=false,% 53pdftitle={Yosys Manual},% 54pdfauthor={Claire Xenia Wolf},% 55%pdfkeywords={keyword},% 56pdfpagelabels,% 57pagebackref,% 58bookmarksopen=false% 59]{hyperref} 60% For the two different reference lists ... 61\usepackage{multibib} 62\usepackage{multirow} 63\usepackage{booktabs} 64\usepackage{pdfpages} 65 66\usepackage{listings} 67\usepackage{pifont} 68\usepackage{skull} 69% \usepackage{draftwatermark} 70 71\usepackage{tikz} 72\usetikzlibrary{calc} 73\usetikzlibrary{arrows} 74\usetikzlibrary{scopes} 75\usetikzlibrary{through} 76\usetikzlibrary{shapes.geometric} 77 78\usepackage{calc} 79\usepackage[nounderscore]{syntax} 80 81\lstset{basicstyle=\ttfamily} 82 83\def\B#1{{\tt\textbackslash{}#1}} 84\def\C#1{\lstinline[language=C++]{#1}} 85\def\V#1{\lstinline[language=Verilog]{#1}} 86 87\newsavebox{\fixmebox} 88\newenvironment{fixme}% 89{\newcommand\colboxcolor{FFBBBB}% 90\begin{lrbox}{\fixmebox}% 91\begin{minipage}{\dimexpr\columnwidth-2\fboxsep\relax}} 92{\end{minipage}\end{lrbox}\textbf{FIXME: }\\% 93\colorbox[HTML]{\colboxcolor}{\usebox{\fixmebox}}} 94 95\newcites{weblink}{Internet References} 96 97\setcounter{secnumdepth}{3} 98\makeindex 99 100\setlength{\oddsidemargin}{4mm} 101\setlength{\evensidemargin}{-6mm} 102\setlength{\textwidth}{162mm} 103\setlength{\textheight}{230mm} 104\setlength{\topmargin}{-5mm} 105 106\setlength{\parskip}{1.5ex plus 1ex minus 0.5ex} 107\setlength{\parindent}{0pt} 108 109\lstdefinelanguage{liberty}{ 110 morecomment=[s]{/*}{*/}, 111 morekeywords={library,cell,area,pin,direction,function,clocked_on,next_state,clock,ff}, 112 morestring=[b]", 113} 114 115\lstdefinelanguage{rtlil}{ 116 morecomment=[l]{\#}, 117 morekeywords={module,attribute,parameter,wire,memory,auto,width,offset,size,input,output,inout,cell,connect,switch,case,assign,sync,low,high,posedge,negedge,edge,always,update,process,end}, 118 morestring=[b]", 119} 120 121 122 123\begin{document} 124 125\fancypagestyle{mypagestyle}{% 126\fancyhf{}% 127\fancyhead[C]{\leftmark}% 128\fancyfoot[C]{\thepage}% 129\renewcommand{\headrulewidth}{0pt}% 130\renewcommand{\footrulewidth}{0pt}} 131\pagestyle{mypagestyle} 132 133\thispagestyle{empty} 134\null\vfil 135 136\begin{center} 137\bf\Huge Yosys Manual 138 139\bigskip 140\large Claire Xenia Wolf 141\end{center} 142 143\vfil\null 144\eject 145 146\chapter*{Abstract} 147Most of today's digital design is done in HDL code (mostly Verilog or VHDL) and 148with the help of HDL synthesis tools. 149 150In special cases such as synthesis for coarse-grain cell libraries or when 151testing new synthesis algorithms it might be necessary to write a custom HDL 152synthesis tool or add new features to an existing one. In these cases the 153availability of a Free and Open Source (FOSS) synthesis tool that can be used 154as basis for custom tools would be helpful. 155 156In the absence of such a tool, the Yosys Open SYnthesis Suite (Yosys) was 157developed. This document covers the design and implementation of this tool. 158At the moment the main focus of Yosys lies on the high-level aspects of 159digital synthesis. The pre-existing FOSS logic-synthesis tool ABC is used 160by Yosys to perform advanced gate-level optimizations. 161 162An evaluation of Yosys based on real-world designs is included. It is shown 163that Yosys can be used as-is to synthesize such designs. The results produced 164by Yosys in this tests where successfully verified using formal verification 165and are comparable in quality to the results produced by a commercial 166synthesis tool. 167 168\bigskip 169 170This document was originally published as bachelor thesis at the Vienna 171University of Technology \cite{BACC}. 172 173\chapter*{Abbreviations} 174\begin{tabular}{ll} 175AIG & And-Inverter-Graph \\ 176ASIC & Application-Specific Integrated Circuit \\ 177AST & Abstract Syntax Tree \\ 178BDD & Binary Decision Diagram \\ 179BLIF & Berkeley Logic Interchange Format \\ 180EDA & Electronic Design Automation \\ 181EDIF & Electronic Design Interchange Format \\ 182ER Diagram & Entity-Relationship Diagram \\ 183FOSS & Free and Open-Source Software \\ 184FPGA & Field-Programmable Gate Array \\ 185FSM & Finite-state machine \\ 186HDL & Hardware Description Language \\ 187LPM & Library of Parameterized Modules \\ 188RTLIL & RTL Intermediate Language \\ 189RTL & Register Transfer Level \\ 190SAT & Satisfiability Problem \\ 191% SSA & Static Single Assignment Form \\ 192VHDL & VHSIC Hardware Description Language \\ 193VHSIC & Very-High-Speed Integrated Circuit \\ 194YOSYS & Yosys Open SYnthesis Suite \\ 195\end{tabular} 196 197\tableofcontents 198 199\include{CHAPTER_Intro} 200\include{CHAPTER_Basics} 201\include{CHAPTER_Approach} 202\include{CHAPTER_Overview} 203\include{CHAPTER_CellLib} 204\include{CHAPTER_Prog} 205 206\include{CHAPTER_Verilog} 207\include{CHAPTER_Optimize} 208\include{CHAPTER_Techmap} 209% \include{CHAPTER_Eval} 210 211\appendix 212 213\include{CHAPTER_Auxlibs} 214\include{CHAPTER_Auxprogs} 215 216\chapter{Command Reference Manual} 217\label{commandref} 218\input{command-reference-manual} 219 220\include{CHAPTER_TextRtlil} 221\include{CHAPTER_Appnotes} 222% \include{CHAPTER_StateOfTheArt} 223 224\bibliography{literature} 225\bibliographystyle{alphadin} 226 227\bibliographyweblink{weblinks} 228\bibliographystyleweblink{abbrv} 229 230\end{document} 231