1read_verilog ../common/lutram.v 2hierarchy -top lutram_1w1r 3proc 4memory -nomap 5equiv_opt -run :prove -map +/nexus/cells_sim.v synth_nexus 6memory 7opt -full 8 9miter -equiv -flatten -make_assert -make_outputs gold gate miter 10sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter 11 12design -load postopt 13cd lutram_1w1r 14stat 15select -assert-count 8 t:WIDEFN9 16select -assert-count 12 t:LUT4 17select -assert-count 8 t:DPR16X4 18select -assert-count 8 t:FD1P3IX 19select -assert-none t:DPR16X4 t:FD1P3IX t:WIDEFN9 t:LUT4 t:INV t:IB t:OB t:VLO t:VHI %% t:* %D 20