1// megafunction wizard: %ALTACCUMULATE%CBX%
2// GENERATION: STANDARD
3// VERSION: WM1.0
4// MODULE: altaccumulate
5
6// ============================================================
7// File Name: accum32.v
8// Megafunction Name(s):
9// 			altaccumulate
10// ============================================================
11// ************************************************************
12// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
13// ************************************************************
14
15
16//Copyright (C) 1991-2003 Altera Corporation
17//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
18//support information,  device programming or simulation file,  and any other
19//associated  documentation or information  provided by  Altera  or a partner
20//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
21//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
22//other  use  of such  megafunction  design,  netlist,  support  information,
23//device programming or simulation file,  or any other  related documentation
24//or information  is prohibited  for  any  other purpose,  including, but not
25//limited to  modification,  reverse engineering,  de-compiling, or use  with
26//any other  silicon devices,  unless such use is  explicitly  licensed under
27//a separate agreement with  Altera  or a megafunction partner.  Title to the
28//intellectual property,  including patents,  copyrights,  trademarks,  trade
29//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
30//support  information,  device programming or simulation file,  or any other
31//related documentation or information provided by  Altera  or a megafunction
32//partner, remains with Altera, the megafunction partner, or their respective
33//licensors. No other licenses, including any licenses needed under any third
34//party's intellectual property, are provided herein.
35
36
37//altaccumulate DEVICE_FAMILY=Cyclone LPM_REPRESENTATION=SIGNED WIDTH_IN=32 WIDTH_OUT=32 aclr clken clock data result
38//VERSION_BEGIN 3.0 cbx_altaccumulate 2003:04:08:16:04:48:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ  VERSION_END
39
40//synthesis_resources = lut 32
41module  accum32_accum_nta
42	(
43	aclr,
44	clken,
45	clock,
46	data,
47	result) /* synthesis synthesis_clearbox=1 */;
48	input   aclr;
49	input   clken;
50	input   clock;
51	input   [31:0]  data;
52	output   [31:0]  result;
53
54	wire  [0:0]   wire_acc_cella_0cout;
55	wire  [0:0]   wire_acc_cella_1cout;
56	wire  [0:0]   wire_acc_cella_2cout;
57	wire  [0:0]   wire_acc_cella_3cout;
58	wire  [0:0]   wire_acc_cella_4cout;
59	wire  [0:0]   wire_acc_cella_5cout;
60	wire  [0:0]   wire_acc_cella_6cout;
61	wire  [0:0]   wire_acc_cella_7cout;
62	wire  [0:0]   wire_acc_cella_8cout;
63	wire  [0:0]   wire_acc_cella_9cout;
64	wire  [0:0]   wire_acc_cella_10cout;
65	wire  [0:0]   wire_acc_cella_11cout;
66	wire  [0:0]   wire_acc_cella_12cout;
67	wire  [0:0]   wire_acc_cella_13cout;
68	wire  [0:0]   wire_acc_cella_14cout;
69	wire  [0:0]   wire_acc_cella_15cout;
70	wire  [0:0]   wire_acc_cella_16cout;
71	wire  [0:0]   wire_acc_cella_17cout;
72	wire  [0:0]   wire_acc_cella_18cout;
73	wire  [0:0]   wire_acc_cella_19cout;
74	wire  [0:0]   wire_acc_cella_20cout;
75	wire  [0:0]   wire_acc_cella_21cout;
76	wire  [0:0]   wire_acc_cella_22cout;
77	wire  [0:0]   wire_acc_cella_23cout;
78	wire  [0:0]   wire_acc_cella_24cout;
79	wire  [0:0]   wire_acc_cella_25cout;
80	wire  [0:0]   wire_acc_cella_26cout;
81	wire  [0:0]   wire_acc_cella_27cout;
82	wire  [0:0]   wire_acc_cella_28cout;
83	wire  [0:0]   wire_acc_cella_29cout;
84	wire  [0:0]   wire_acc_cella_30cout;
85	wire  [31:0]   wire_acc_cella_dataa;
86	wire  [31:0]   wire_acc_cella_datab;
87	wire  [31:0]   wire_acc_cella_datac;
88	wire  [31:0]   wire_acc_cella_regout;
89	wire sload;
90
91	stratix_lcell   acc_cella_0
92	(
93	.aclr(aclr),
94	.cin(1'b0),
95	.clk(clock),
96	.cout(wire_acc_cella_0cout[0:0]),
97	.dataa(wire_acc_cella_dataa[0:0]),
98	.datab(wire_acc_cella_datab[0:0]),
99	.datac(wire_acc_cella_datac[0:0]),
100	.ena(clken),
101	.regout(wire_acc_cella_regout[0:0]),
102	.sload(sload));
103	defparam
104		acc_cella_0.cin_used = "true",
105		acc_cella_0.lut_mask = "96e8",
106		acc_cella_0.operation_mode = "arithmetic",
107		acc_cella_0.sum_lutc_input = "cin",
108		acc_cella_0.synch_mode = "on",
109		acc_cella_0.lpm_type = "stratix_lcell";
110	stratix_lcell   acc_cella_1
111	(
112	.aclr(aclr),
113	.cin(wire_acc_cella_0cout[0:0]),
114	.clk(clock),
115	.cout(wire_acc_cella_1cout[0:0]),
116	.dataa(wire_acc_cella_dataa[1:1]),
117	.datab(wire_acc_cella_datab[1:1]),
118	.datac(wire_acc_cella_datac[1:1]),
119	.ena(clken),
120	.regout(wire_acc_cella_regout[1:1]),
121	.sload(sload));
122	defparam
123		acc_cella_1.cin_used = "true",
124		acc_cella_1.lut_mask = "96e8",
125		acc_cella_1.operation_mode = "arithmetic",
126		acc_cella_1.sum_lutc_input = "cin",
127		acc_cella_1.synch_mode = "on",
128		acc_cella_1.lpm_type = "stratix_lcell";
129	stratix_lcell   acc_cella_2
130	(
131	.aclr(aclr),
132	.cin(wire_acc_cella_1cout[0:0]),
133	.clk(clock),
134	.cout(wire_acc_cella_2cout[0:0]),
135	.dataa(wire_acc_cella_dataa[2:2]),
136	.datab(wire_acc_cella_datab[2:2]),
137	.datac(wire_acc_cella_datac[2:2]),
138	.ena(clken),
139	.regout(wire_acc_cella_regout[2:2]),
140	.sload(sload));
141	defparam
142		acc_cella_2.cin_used = "true",
143		acc_cella_2.lut_mask = "96e8",
144		acc_cella_2.operation_mode = "arithmetic",
145		acc_cella_2.sum_lutc_input = "cin",
146		acc_cella_2.synch_mode = "on",
147		acc_cella_2.lpm_type = "stratix_lcell";
148	stratix_lcell   acc_cella_3
149	(
150	.aclr(aclr),
151	.cin(wire_acc_cella_2cout[0:0]),
152	.clk(clock),
153	.cout(wire_acc_cella_3cout[0:0]),
154	.dataa(wire_acc_cella_dataa[3:3]),
155	.datab(wire_acc_cella_datab[3:3]),
156	.datac(wire_acc_cella_datac[3:3]),
157	.ena(clken),
158	.regout(wire_acc_cella_regout[3:3]),
159	.sload(sload));
160	defparam
161		acc_cella_3.cin_used = "true",
162		acc_cella_3.lut_mask = "96e8",
163		acc_cella_3.operation_mode = "arithmetic",
164		acc_cella_3.sum_lutc_input = "cin",
165		acc_cella_3.synch_mode = "on",
166		acc_cella_3.lpm_type = "stratix_lcell";
167	stratix_lcell   acc_cella_4
168	(
169	.aclr(aclr),
170	.cin(wire_acc_cella_3cout[0:0]),
171	.clk(clock),
172	.cout(wire_acc_cella_4cout[0:0]),
173	.dataa(wire_acc_cella_dataa[4:4]),
174	.datab(wire_acc_cella_datab[4:4]),
175	.datac(wire_acc_cella_datac[4:4]),
176	.ena(clken),
177	.regout(wire_acc_cella_regout[4:4]),
178	.sload(sload));
179	defparam
180		acc_cella_4.cin_used = "true",
181		acc_cella_4.lut_mask = "96e8",
182		acc_cella_4.operation_mode = "arithmetic",
183		acc_cella_4.sum_lutc_input = "cin",
184		acc_cella_4.synch_mode = "on",
185		acc_cella_4.lpm_type = "stratix_lcell";
186	stratix_lcell   acc_cella_5
187	(
188	.aclr(aclr),
189	.cin(wire_acc_cella_4cout[0:0]),
190	.clk(clock),
191	.cout(wire_acc_cella_5cout[0:0]),
192	.dataa(wire_acc_cella_dataa[5:5]),
193	.datab(wire_acc_cella_datab[5:5]),
194	.datac(wire_acc_cella_datac[5:5]),
195	.ena(clken),
196	.regout(wire_acc_cella_regout[5:5]),
197	.sload(sload));
198	defparam
199		acc_cella_5.cin_used = "true",
200		acc_cella_5.lut_mask = "96e8",
201		acc_cella_5.operation_mode = "arithmetic",
202		acc_cella_5.sum_lutc_input = "cin",
203		acc_cella_5.synch_mode = "on",
204		acc_cella_5.lpm_type = "stratix_lcell";
205	stratix_lcell   acc_cella_6
206	(
207	.aclr(aclr),
208	.cin(wire_acc_cella_5cout[0:0]),
209	.clk(clock),
210	.cout(wire_acc_cella_6cout[0:0]),
211	.dataa(wire_acc_cella_dataa[6:6]),
212	.datab(wire_acc_cella_datab[6:6]),
213	.datac(wire_acc_cella_datac[6:6]),
214	.ena(clken),
215	.regout(wire_acc_cella_regout[6:6]),
216	.sload(sload));
217	defparam
218		acc_cella_6.cin_used = "true",
219		acc_cella_6.lut_mask = "96e8",
220		acc_cella_6.operation_mode = "arithmetic",
221		acc_cella_6.sum_lutc_input = "cin",
222		acc_cella_6.synch_mode = "on",
223		acc_cella_6.lpm_type = "stratix_lcell";
224	stratix_lcell   acc_cella_7
225	(
226	.aclr(aclr),
227	.cin(wire_acc_cella_6cout[0:0]),
228	.clk(clock),
229	.cout(wire_acc_cella_7cout[0:0]),
230	.dataa(wire_acc_cella_dataa[7:7]),
231	.datab(wire_acc_cella_datab[7:7]),
232	.datac(wire_acc_cella_datac[7:7]),
233	.ena(clken),
234	.regout(wire_acc_cella_regout[7:7]),
235	.sload(sload));
236	defparam
237		acc_cella_7.cin_used = "true",
238		acc_cella_7.lut_mask = "96e8",
239		acc_cella_7.operation_mode = "arithmetic",
240		acc_cella_7.sum_lutc_input = "cin",
241		acc_cella_7.synch_mode = "on",
242		acc_cella_7.lpm_type = "stratix_lcell";
243	stratix_lcell   acc_cella_8
244	(
245	.aclr(aclr),
246	.cin(wire_acc_cella_7cout[0:0]),
247	.clk(clock),
248	.cout(wire_acc_cella_8cout[0:0]),
249	.dataa(wire_acc_cella_dataa[8:8]),
250	.datab(wire_acc_cella_datab[8:8]),
251	.datac(wire_acc_cella_datac[8:8]),
252	.ena(clken),
253	.regout(wire_acc_cella_regout[8:8]),
254	.sload(sload));
255	defparam
256		acc_cella_8.cin_used = "true",
257		acc_cella_8.lut_mask = "96e8",
258		acc_cella_8.operation_mode = "arithmetic",
259		acc_cella_8.sum_lutc_input = "cin",
260		acc_cella_8.synch_mode = "on",
261		acc_cella_8.lpm_type = "stratix_lcell";
262	stratix_lcell   acc_cella_9
263	(
264	.aclr(aclr),
265	.cin(wire_acc_cella_8cout[0:0]),
266	.clk(clock),
267	.cout(wire_acc_cella_9cout[0:0]),
268	.dataa(wire_acc_cella_dataa[9:9]),
269	.datab(wire_acc_cella_datab[9:9]),
270	.datac(wire_acc_cella_datac[9:9]),
271	.ena(clken),
272	.regout(wire_acc_cella_regout[9:9]),
273	.sload(sload));
274	defparam
275		acc_cella_9.cin_used = "true",
276		acc_cella_9.lut_mask = "96e8",
277		acc_cella_9.operation_mode = "arithmetic",
278		acc_cella_9.sum_lutc_input = "cin",
279		acc_cella_9.synch_mode = "on",
280		acc_cella_9.lpm_type = "stratix_lcell";
281	stratix_lcell   acc_cella_10
282	(
283	.aclr(aclr),
284	.cin(wire_acc_cella_9cout[0:0]),
285	.clk(clock),
286	.cout(wire_acc_cella_10cout[0:0]),
287	.dataa(wire_acc_cella_dataa[10:10]),
288	.datab(wire_acc_cella_datab[10:10]),
289	.datac(wire_acc_cella_datac[10:10]),
290	.ena(clken),
291	.regout(wire_acc_cella_regout[10:10]),
292	.sload(sload));
293	defparam
294		acc_cella_10.cin_used = "true",
295		acc_cella_10.lut_mask = "96e8",
296		acc_cella_10.operation_mode = "arithmetic",
297		acc_cella_10.sum_lutc_input = "cin",
298		acc_cella_10.synch_mode = "on",
299		acc_cella_10.lpm_type = "stratix_lcell";
300	stratix_lcell   acc_cella_11
301	(
302	.aclr(aclr),
303	.cin(wire_acc_cella_10cout[0:0]),
304	.clk(clock),
305	.cout(wire_acc_cella_11cout[0:0]),
306	.dataa(wire_acc_cella_dataa[11:11]),
307	.datab(wire_acc_cella_datab[11:11]),
308	.datac(wire_acc_cella_datac[11:11]),
309	.ena(clken),
310	.regout(wire_acc_cella_regout[11:11]),
311	.sload(sload));
312	defparam
313		acc_cella_11.cin_used = "true",
314		acc_cella_11.lut_mask = "96e8",
315		acc_cella_11.operation_mode = "arithmetic",
316		acc_cella_11.sum_lutc_input = "cin",
317		acc_cella_11.synch_mode = "on",
318		acc_cella_11.lpm_type = "stratix_lcell";
319	stratix_lcell   acc_cella_12
320	(
321	.aclr(aclr),
322	.cin(wire_acc_cella_11cout[0:0]),
323	.clk(clock),
324	.cout(wire_acc_cella_12cout[0:0]),
325	.dataa(wire_acc_cella_dataa[12:12]),
326	.datab(wire_acc_cella_datab[12:12]),
327	.datac(wire_acc_cella_datac[12:12]),
328	.ena(clken),
329	.regout(wire_acc_cella_regout[12:12]),
330	.sload(sload));
331	defparam
332		acc_cella_12.cin_used = "true",
333		acc_cella_12.lut_mask = "96e8",
334		acc_cella_12.operation_mode = "arithmetic",
335		acc_cella_12.sum_lutc_input = "cin",
336		acc_cella_12.synch_mode = "on",
337		acc_cella_12.lpm_type = "stratix_lcell";
338	stratix_lcell   acc_cella_13
339	(
340	.aclr(aclr),
341	.cin(wire_acc_cella_12cout[0:0]),
342	.clk(clock),
343	.cout(wire_acc_cella_13cout[0:0]),
344	.dataa(wire_acc_cella_dataa[13:13]),
345	.datab(wire_acc_cella_datab[13:13]),
346	.datac(wire_acc_cella_datac[13:13]),
347	.ena(clken),
348	.regout(wire_acc_cella_regout[13:13]),
349	.sload(sload));
350	defparam
351		acc_cella_13.cin_used = "true",
352		acc_cella_13.lut_mask = "96e8",
353		acc_cella_13.operation_mode = "arithmetic",
354		acc_cella_13.sum_lutc_input = "cin",
355		acc_cella_13.synch_mode = "on",
356		acc_cella_13.lpm_type = "stratix_lcell";
357	stratix_lcell   acc_cella_14
358	(
359	.aclr(aclr),
360	.cin(wire_acc_cella_13cout[0:0]),
361	.clk(clock),
362	.cout(wire_acc_cella_14cout[0:0]),
363	.dataa(wire_acc_cella_dataa[14:14]),
364	.datab(wire_acc_cella_datab[14:14]),
365	.datac(wire_acc_cella_datac[14:14]),
366	.ena(clken),
367	.regout(wire_acc_cella_regout[14:14]),
368	.sload(sload));
369	defparam
370		acc_cella_14.cin_used = "true",
371		acc_cella_14.lut_mask = "96e8",
372		acc_cella_14.operation_mode = "arithmetic",
373		acc_cella_14.sum_lutc_input = "cin",
374		acc_cella_14.synch_mode = "on",
375		acc_cella_14.lpm_type = "stratix_lcell";
376	stratix_lcell   acc_cella_15
377	(
378	.aclr(aclr),
379	.cin(wire_acc_cella_14cout[0:0]),
380	.clk(clock),
381	.cout(wire_acc_cella_15cout[0:0]),
382	.dataa(wire_acc_cella_dataa[15:15]),
383	.datab(wire_acc_cella_datab[15:15]),
384	.datac(wire_acc_cella_datac[15:15]),
385	.ena(clken),
386	.regout(wire_acc_cella_regout[15:15]),
387	.sload(sload));
388	defparam
389		acc_cella_15.cin_used = "true",
390		acc_cella_15.lut_mask = "96e8",
391		acc_cella_15.operation_mode = "arithmetic",
392		acc_cella_15.sum_lutc_input = "cin",
393		acc_cella_15.synch_mode = "on",
394		acc_cella_15.lpm_type = "stratix_lcell";
395	stratix_lcell   acc_cella_16
396	(
397	.aclr(aclr),
398	.cin(wire_acc_cella_15cout[0:0]),
399	.clk(clock),
400	.cout(wire_acc_cella_16cout[0:0]),
401	.dataa(wire_acc_cella_dataa[16:16]),
402	.datab(wire_acc_cella_datab[16:16]),
403	.datac(wire_acc_cella_datac[16:16]),
404	.ena(clken),
405	.regout(wire_acc_cella_regout[16:16]),
406	.sload(sload));
407	defparam
408		acc_cella_16.cin_used = "true",
409		acc_cella_16.lut_mask = "96e8",
410		acc_cella_16.operation_mode = "arithmetic",
411		acc_cella_16.sum_lutc_input = "cin",
412		acc_cella_16.synch_mode = "on",
413		acc_cella_16.lpm_type = "stratix_lcell";
414	stratix_lcell   acc_cella_17
415	(
416	.aclr(aclr),
417	.cin(wire_acc_cella_16cout[0:0]),
418	.clk(clock),
419	.cout(wire_acc_cella_17cout[0:0]),
420	.dataa(wire_acc_cella_dataa[17:17]),
421	.datab(wire_acc_cella_datab[17:17]),
422	.datac(wire_acc_cella_datac[17:17]),
423	.ena(clken),
424	.regout(wire_acc_cella_regout[17:17]),
425	.sload(sload));
426	defparam
427		acc_cella_17.cin_used = "true",
428		acc_cella_17.lut_mask = "96e8",
429		acc_cella_17.operation_mode = "arithmetic",
430		acc_cella_17.sum_lutc_input = "cin",
431		acc_cella_17.synch_mode = "on",
432		acc_cella_17.lpm_type = "stratix_lcell";
433	stratix_lcell   acc_cella_18
434	(
435	.aclr(aclr),
436	.cin(wire_acc_cella_17cout[0:0]),
437	.clk(clock),
438	.cout(wire_acc_cella_18cout[0:0]),
439	.dataa(wire_acc_cella_dataa[18:18]),
440	.datab(wire_acc_cella_datab[18:18]),
441	.datac(wire_acc_cella_datac[18:18]),
442	.ena(clken),
443	.regout(wire_acc_cella_regout[18:18]),
444	.sload(sload));
445	defparam
446		acc_cella_18.cin_used = "true",
447		acc_cella_18.lut_mask = "96e8",
448		acc_cella_18.operation_mode = "arithmetic",
449		acc_cella_18.sum_lutc_input = "cin",
450		acc_cella_18.synch_mode = "on",
451		acc_cella_18.lpm_type = "stratix_lcell";
452	stratix_lcell   acc_cella_19
453	(
454	.aclr(aclr),
455	.cin(wire_acc_cella_18cout[0:0]),
456	.clk(clock),
457	.cout(wire_acc_cella_19cout[0:0]),
458	.dataa(wire_acc_cella_dataa[19:19]),
459	.datab(wire_acc_cella_datab[19:19]),
460	.datac(wire_acc_cella_datac[19:19]),
461	.ena(clken),
462	.regout(wire_acc_cella_regout[19:19]),
463	.sload(sload));
464	defparam
465		acc_cella_19.cin_used = "true",
466		acc_cella_19.lut_mask = "96e8",
467		acc_cella_19.operation_mode = "arithmetic",
468		acc_cella_19.sum_lutc_input = "cin",
469		acc_cella_19.synch_mode = "on",
470		acc_cella_19.lpm_type = "stratix_lcell";
471	stratix_lcell   acc_cella_20
472	(
473	.aclr(aclr),
474	.cin(wire_acc_cella_19cout[0:0]),
475	.clk(clock),
476	.cout(wire_acc_cella_20cout[0:0]),
477	.dataa(wire_acc_cella_dataa[20:20]),
478	.datab(wire_acc_cella_datab[20:20]),
479	.datac(wire_acc_cella_datac[20:20]),
480	.ena(clken),
481	.regout(wire_acc_cella_regout[20:20]),
482	.sload(sload));
483	defparam
484		acc_cella_20.cin_used = "true",
485		acc_cella_20.lut_mask = "96e8",
486		acc_cella_20.operation_mode = "arithmetic",
487		acc_cella_20.sum_lutc_input = "cin",
488		acc_cella_20.synch_mode = "on",
489		acc_cella_20.lpm_type = "stratix_lcell";
490	stratix_lcell   acc_cella_21
491	(
492	.aclr(aclr),
493	.cin(wire_acc_cella_20cout[0:0]),
494	.clk(clock),
495	.cout(wire_acc_cella_21cout[0:0]),
496	.dataa(wire_acc_cella_dataa[21:21]),
497	.datab(wire_acc_cella_datab[21:21]),
498	.datac(wire_acc_cella_datac[21:21]),
499	.ena(clken),
500	.regout(wire_acc_cella_regout[21:21]),
501	.sload(sload));
502	defparam
503		acc_cella_21.cin_used = "true",
504		acc_cella_21.lut_mask = "96e8",
505		acc_cella_21.operation_mode = "arithmetic",
506		acc_cella_21.sum_lutc_input = "cin",
507		acc_cella_21.synch_mode = "on",
508		acc_cella_21.lpm_type = "stratix_lcell";
509	stratix_lcell   acc_cella_22
510	(
511	.aclr(aclr),
512	.cin(wire_acc_cella_21cout[0:0]),
513	.clk(clock),
514	.cout(wire_acc_cella_22cout[0:0]),
515	.dataa(wire_acc_cella_dataa[22:22]),
516	.datab(wire_acc_cella_datab[22:22]),
517	.datac(wire_acc_cella_datac[22:22]),
518	.ena(clken),
519	.regout(wire_acc_cella_regout[22:22]),
520	.sload(sload));
521	defparam
522		acc_cella_22.cin_used = "true",
523		acc_cella_22.lut_mask = "96e8",
524		acc_cella_22.operation_mode = "arithmetic",
525		acc_cella_22.sum_lutc_input = "cin",
526		acc_cella_22.synch_mode = "on",
527		acc_cella_22.lpm_type = "stratix_lcell";
528	stratix_lcell   acc_cella_23
529	(
530	.aclr(aclr),
531	.cin(wire_acc_cella_22cout[0:0]),
532	.clk(clock),
533	.cout(wire_acc_cella_23cout[0:0]),
534	.dataa(wire_acc_cella_dataa[23:23]),
535	.datab(wire_acc_cella_datab[23:23]),
536	.datac(wire_acc_cella_datac[23:23]),
537	.ena(clken),
538	.regout(wire_acc_cella_regout[23:23]),
539	.sload(sload));
540	defparam
541		acc_cella_23.cin_used = "true",
542		acc_cella_23.lut_mask = "96e8",
543		acc_cella_23.operation_mode = "arithmetic",
544		acc_cella_23.sum_lutc_input = "cin",
545		acc_cella_23.synch_mode = "on",
546		acc_cella_23.lpm_type = "stratix_lcell";
547	stratix_lcell   acc_cella_24
548	(
549	.aclr(aclr),
550	.cin(wire_acc_cella_23cout[0:0]),
551	.clk(clock),
552	.cout(wire_acc_cella_24cout[0:0]),
553	.dataa(wire_acc_cella_dataa[24:24]),
554	.datab(wire_acc_cella_datab[24:24]),
555	.datac(wire_acc_cella_datac[24:24]),
556	.ena(clken),
557	.regout(wire_acc_cella_regout[24:24]),
558	.sload(sload));
559	defparam
560		acc_cella_24.cin_used = "true",
561		acc_cella_24.lut_mask = "96e8",
562		acc_cella_24.operation_mode = "arithmetic",
563		acc_cella_24.sum_lutc_input = "cin",
564		acc_cella_24.synch_mode = "on",
565		acc_cella_24.lpm_type = "stratix_lcell";
566	stratix_lcell   acc_cella_25
567	(
568	.aclr(aclr),
569	.cin(wire_acc_cella_24cout[0:0]),
570	.clk(clock),
571	.cout(wire_acc_cella_25cout[0:0]),
572	.dataa(wire_acc_cella_dataa[25:25]),
573	.datab(wire_acc_cella_datab[25:25]),
574	.datac(wire_acc_cella_datac[25:25]),
575	.ena(clken),
576	.regout(wire_acc_cella_regout[25:25]),
577	.sload(sload));
578	defparam
579		acc_cella_25.cin_used = "true",
580		acc_cella_25.lut_mask = "96e8",
581		acc_cella_25.operation_mode = "arithmetic",
582		acc_cella_25.sum_lutc_input = "cin",
583		acc_cella_25.synch_mode = "on",
584		acc_cella_25.lpm_type = "stratix_lcell";
585	stratix_lcell   acc_cella_26
586	(
587	.aclr(aclr),
588	.cin(wire_acc_cella_25cout[0:0]),
589	.clk(clock),
590	.cout(wire_acc_cella_26cout[0:0]),
591	.dataa(wire_acc_cella_dataa[26:26]),
592	.datab(wire_acc_cella_datab[26:26]),
593	.datac(wire_acc_cella_datac[26:26]),
594	.ena(clken),
595	.regout(wire_acc_cella_regout[26:26]),
596	.sload(sload));
597	defparam
598		acc_cella_26.cin_used = "true",
599		acc_cella_26.lut_mask = "96e8",
600		acc_cella_26.operation_mode = "arithmetic",
601		acc_cella_26.sum_lutc_input = "cin",
602		acc_cella_26.synch_mode = "on",
603		acc_cella_26.lpm_type = "stratix_lcell";
604	stratix_lcell   acc_cella_27
605	(
606	.aclr(aclr),
607	.cin(wire_acc_cella_26cout[0:0]),
608	.clk(clock),
609	.cout(wire_acc_cella_27cout[0:0]),
610	.dataa(wire_acc_cella_dataa[27:27]),
611	.datab(wire_acc_cella_datab[27:27]),
612	.datac(wire_acc_cella_datac[27:27]),
613	.ena(clken),
614	.regout(wire_acc_cella_regout[27:27]),
615	.sload(sload));
616	defparam
617		acc_cella_27.cin_used = "true",
618		acc_cella_27.lut_mask = "96e8",
619		acc_cella_27.operation_mode = "arithmetic",
620		acc_cella_27.sum_lutc_input = "cin",
621		acc_cella_27.synch_mode = "on",
622		acc_cella_27.lpm_type = "stratix_lcell";
623	stratix_lcell   acc_cella_28
624	(
625	.aclr(aclr),
626	.cin(wire_acc_cella_27cout[0:0]),
627	.clk(clock),
628	.cout(wire_acc_cella_28cout[0:0]),
629	.dataa(wire_acc_cella_dataa[28:28]),
630	.datab(wire_acc_cella_datab[28:28]),
631	.datac(wire_acc_cella_datac[28:28]),
632	.ena(clken),
633	.regout(wire_acc_cella_regout[28:28]),
634	.sload(sload));
635	defparam
636		acc_cella_28.cin_used = "true",
637		acc_cella_28.lut_mask = "96e8",
638		acc_cella_28.operation_mode = "arithmetic",
639		acc_cella_28.sum_lutc_input = "cin",
640		acc_cella_28.synch_mode = "on",
641		acc_cella_28.lpm_type = "stratix_lcell";
642	stratix_lcell   acc_cella_29
643	(
644	.aclr(aclr),
645	.cin(wire_acc_cella_28cout[0:0]),
646	.clk(clock),
647	.cout(wire_acc_cella_29cout[0:0]),
648	.dataa(wire_acc_cella_dataa[29:29]),
649	.datab(wire_acc_cella_datab[29:29]),
650	.datac(wire_acc_cella_datac[29:29]),
651	.ena(clken),
652	.regout(wire_acc_cella_regout[29:29]),
653	.sload(sload));
654	defparam
655		acc_cella_29.cin_used = "true",
656		acc_cella_29.lut_mask = "96e8",
657		acc_cella_29.operation_mode = "arithmetic",
658		acc_cella_29.sum_lutc_input = "cin",
659		acc_cella_29.synch_mode = "on",
660		acc_cella_29.lpm_type = "stratix_lcell";
661	stratix_lcell   acc_cella_30
662	(
663	.aclr(aclr),
664	.cin(wire_acc_cella_29cout[0:0]),
665	.clk(clock),
666	.cout(wire_acc_cella_30cout[0:0]),
667	.dataa(wire_acc_cella_dataa[30:30]),
668	.datab(wire_acc_cella_datab[30:30]),
669	.datac(wire_acc_cella_datac[30:30]),
670	.ena(clken),
671	.regout(wire_acc_cella_regout[30:30]),
672	.sload(sload));
673	defparam
674		acc_cella_30.cin_used = "true",
675		acc_cella_30.lut_mask = "96e8",
676		acc_cella_30.operation_mode = "arithmetic",
677		acc_cella_30.sum_lutc_input = "cin",
678		acc_cella_30.synch_mode = "on",
679		acc_cella_30.lpm_type = "stratix_lcell";
680	stratix_lcell   acc_cella_31
681	(
682	.aclr(aclr),
683	.cin(wire_acc_cella_30cout[0:0]),
684	.clk(clock),
685	.dataa(wire_acc_cella_dataa[31:31]),
686	.datab(wire_acc_cella_datab[31:31]),
687	.datac(wire_acc_cella_datac[31:31]),
688	.ena(clken),
689	.regout(wire_acc_cella_regout[31:31]),
690	.sload(sload));
691	defparam
692		acc_cella_31.cin_used = "true",
693		acc_cella_31.lut_mask = "9696",
694		acc_cella_31.operation_mode = "normal",
695		acc_cella_31.sum_lutc_input = "cin",
696		acc_cella_31.synch_mode = "on",
697		acc_cella_31.lpm_type = "stratix_lcell";
698	assign
699		wire_acc_cella_dataa = data,
700		wire_acc_cella_datab = wire_acc_cella_regout,
701		wire_acc_cella_datac = data;
702	assign
703		result = wire_acc_cella_regout,
704		sload = 1'b0;
705endmodule //accum32_accum_nta
706//VALID FILE
707
708
709module accum32 (
710	data,
711	clock,
712	clken,
713	aclr,
714	result)/* synthesis synthesis_clearbox = 1 */;
715
716	input	[31:0]  data;
717	input	  clock;
718	input	  clken;
719	input	  aclr;
720	output	[31:0]  result;
721
722	wire [31:0] sub_wire0;
723	wire [31:0] result = sub_wire0[31:0];
724
725	accum32_accum_nta	accum32_accum_nta_component (
726				.clken (clken),
727				.aclr (aclr),
728				.clock (clock),
729				.data (data),
730				.result (sub_wire0));
731
732endmodule
733
734// ============================================================
735// CNX file retrieval info
736// ============================================================
737// Retrieval info: PRIVATE: WIDTH_IN NUMERIC "32"
738// Retrieval info: PRIVATE: WIDTH_OUT NUMERIC "32"
739// Retrieval info: PRIVATE: LPM_REPRESENTATION NUMERIC "0"
740// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
741// Retrieval info: PRIVATE: ADD_SUB NUMERIC "0"
742// Retrieval info: PRIVATE: CIN NUMERIC "0"
743// Retrieval info: PRIVATE: CLKEN NUMERIC "1"
744// Retrieval info: PRIVATE: ACLR NUMERIC "1"
745// Retrieval info: PRIVATE: COUT NUMERIC "0"
746// Retrieval info: PRIVATE: OVERFLOW NUMERIC "0"
747// Retrieval info: PRIVATE: LATENCY NUMERIC "0"
748// Retrieval info: PRIVATE: EXTRA_LATENCY NUMERIC "0"
749// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
750// Retrieval info: CONSTANT: WIDTH_IN NUMERIC "32"
751// Retrieval info: CONSTANT: WIDTH_OUT NUMERIC "32"
752// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
753// Retrieval info: CONSTANT: LPM_TYPE STRING "altaccumulate"
754// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
755// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
756// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
757// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND clock
758// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
759// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
760// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
761// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
762// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
763// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
764// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
765// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
766