1// -*- verilog -*-
2//
3//  USRP - Universal Software Radio Peripheral
4//
5//  Copyright (C) 2003 Matt Ettus
6//
7//  This program is free software; you can redistribute it and/or modify
8//  it under the terms of the GNU General Public License as published by
9//  the Free Software Foundation; either version 2 of the License, or
10//  (at your option) any later version.
11//
12//  This program is distributed in the hope that it will be useful,
13//  but WITHOUT ANY WARRANTY; without even the implied warranty of
14//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15//  GNU General Public License for more details.
16//
17//  You should have received a copy of the GNU General Public License
18//  along with this program; if not, write to the Free Software
19//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
20//
21
22// Following defines conditionally include RX path circuitry
23
24`include "config.vh"	// resolved relative to project root
25
26module rx_chain
27  (input clock,
28   input reset,
29   input enable,
30   input wire [7:0] decim_rate,
31   input sample_strobe,
32   input decimator_strobe,
33   output wire hb_strobe,
34   input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe,
35   input wire [15:0] i_in,
36   input wire [15:0] q_in,
37   output wire [15:0] i_out,
38   output wire [15:0] q_out,
39   output wire [15:0] debugdata,output wire [15:0] debugctrl
40   );
41
42   parameter FREQADDR = 0;
43   parameter PHASEADDR = 0;
44
45   wire [31:0] phase;
46   wire [15:0] bb_i, bb_q;
47   wire [15:0] hb_in_i, hb_in_q;
48
49   assign      debugdata = hb_in_i;
50
51`ifdef RX_NCO_ON
52    phase_acc #(FREQADDR,PHASEADDR,32) rx_phase_acc
53     (.clk(clock),.reset(reset),.enable(enable),
54      .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
55      .strobe(sample_strobe),.phase(phase) );
56
57   cordic rx_cordic
58     ( .clock(clock),.reset(reset),.enable(enable),
59       .xi(i_in),.yi(q_in),.zi(phase[31:16]),
60       .xo(bb_i),.yo(bb_q),.zo() );
61`else
62   assign bb_i = i_in;
63   assign bb_q = q_in;
64   assign sample_strobe = 1;
65`endif // !`ifdef RX_NCO_ON
66
67`ifdef RX_CIC_ON
68   cic_decim cic_decim_i_0
69     ( .clock(clock),.reset(reset),.enable(enable),
70       .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
71       .signal_in(bb_i),.signal_out(hb_in_i) );
72`else
73   assign hb_in_i = bb_i;
74   assign decimator_strobe = sample_strobe;
75`endif
76
77`ifdef RX_HB_ON
78   halfband_decim hbd_i_0
79     ( .clock(clock),.reset(reset),.enable(enable),
80       .strobe_in(decimator_strobe),.strobe_out(hb_strobe),
81       .data_in(hb_in_i),.data_out(i_out),.debugctrl(debugctrl) );
82`else
83   assign i_out = hb_in_i;
84   assign hb_strobe = decimator_strobe;
85`endif
86
87`ifdef RX_CIC_ON
88   cic_decim cic_decim_q_0
89     ( .clock(clock),.reset(reset),.enable(enable),
90       .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
91       .signal_in(bb_q),.signal_out(hb_in_q) );
92`else
93   assign hb_in_q = bb_q;
94`endif
95
96`ifdef RX_HB_ON
97   halfband_decim hbd_q_0
98     ( .clock(clock),.reset(reset),.enable(enable),
99       .strobe_in(decimator_strobe),.strobe_out(),
100       .data_in(hb_in_q),.data_out(q_out) );
101`else
102   assign q_out = hb_in_q;
103`endif
104
105
106endmodule // rx_chain
107