1// 2// Copyright 2011 Ettus Research LLC 3// 4// This program is free software: you can redistribute it and/or modify 5// it under the terms of the GNU General Public License as published by 6// the Free Software Foundation, either version 3 of the License, or 7// (at your option) any later version. 8// 9// This program is distributed in the hope that it will be useful, 10// but WITHOUT ANY WARRANTY; without even the implied warranty of 11// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12// GNU General Public License for more details. 13// 14// You should have received a copy of the GNU General Public License 15// along with this program. If not, see <http://www.gnu.org/licenses/>. 16// 17 18 19 20module test_hbd(); 21 22 reg clock; 23 initial clock = 1'b0; 24 always #5 clock <= ~clock; 25 26 reg reset; 27 initial reset = 1'b1; 28 initial #1000 reset = 1'b0; 29 30 initial $dumpfile("test_hbd.vcd"); 31 initial $dumpvars(0,test_hbd); 32 33 reg [15:0] i_in, q_in; 34 wire [15:0] i_out, q_out; 35 36 reg strobe_in; 37 wire strobe_out; 38 reg coeff_write; 39 reg [15:0] coeff_data; 40 reg [4:0] coeff_addr; 41 42 halfband_decim halfband_decim 43 ( .clock(clock),.reset(reset),.enable(),.strobe_in(strobe_in),.strobe_out(strobe_out), 44 .data_in(i_in),.data_out(i_out) ); 45 46 always @(posedge strobe_out) 47 if(i_out[15]) 48 $display("-%d",65536-i_out); 49 else 50 $display("%d",i_out); 51 52 initial 53 begin 54 strobe_in = 1'b0; 55 @(negedge reset); 56 @(posedge clock); 57 while(1) 58 begin 59 strobe_in <= #1 1'b1; 60 @(posedge clock); 61 strobe_in <= #1 1'b0; 62 repeat (`RATE) 63 @(posedge clock); 64 end 65 end 66 67 initial #10000000 $finish; // Just in case... 68 69 initial 70 begin 71 i_in <= #1 16'd0; 72 repeat (40) @(posedge strobe_in); 73 i_in <= #1 16'd16384; 74 @(posedge strobe_in); 75 i_in <= #1 16'd0; 76 repeat (40) @(posedge strobe_in); 77 i_in <= #1 16'd16384; 78 @(posedge strobe_in); 79 i_in <= #1 16'd0; 80 repeat (40) @(posedge strobe_in); 81 i_in <= #1 16'd16384; 82 repeat (40) @(posedge strobe_in); 83 i_in <= #1 16'd0; 84 repeat (41) @(posedge strobe_in); 85 i_in <= #1 16'd16384; 86 repeat (40) @(posedge strobe_in); 87 i_in <= #1 16'd0; 88 repeat (40) @(posedge strobe_in); 89 repeat (7) @(posedge clock); 90 $finish; 91 end // initial begin 92endmodule // test_hb 93