1//
2// Copyright 2014 Ettus Research LLC
3// Copyright 2018 Ettus Research, a National Instruments Company
4//
5// SPDX-License-Identifier: LGPL-3.0-or-later
6//
7// Discard silently packets which don't match this SID
8
9module filter_bad_sid
10  (
11   input clk,
12   input reset,
13   input clear,
14   //
15   input [64:0] i_tdata,
16   input i_tvalid,
17   output i_tready,
18   //
19   output [64:0] o_tdata,
20   output o_tvalid,
21   input  o_tready,
22   //
23   output reg [15:0] count
24   );
25
26   reg [1:0] state;
27   wire      good_sid;
28   wire      qualify_i_tvalid;
29
30   localparam IDLE = 0;
31   localparam ACCEPT = 1;
32   localparam DISCARD = 2;
33
34
35   always @(posedge clk)
36     if (reset | clear) begin
37	state <= IDLE;
38	count <= 0;
39     end else
40       case(state)
41	 //
42	 IDLE: begin
43	    if  (i_tvalid && i_tready)
44	      if (good_sid)
45		state <= ACCEPT;
46	      else begin
47		 count <= count + 1;
48		 state <= DISCARD;
49	      end
50	 end
51	 //
52	 ACCEPT: begin
53	    if (i_tvalid && i_tready && i_tdata[64])
54	      state <= IDLE;
55	 end
56	 //
57	 DISCARD: begin
58	    if (i_tvalid && i_tready && i_tdata[64])
59	      state <= IDLE;
60	 end
61       endcase // case(state)
62
63   assign good_sid = ((i_tdata[15:0] == 16'h00A0) || (i_tdata[15:0] == 16'h00B0));
64
65   assign qualify_i_tvalid = (state == IDLE) ? good_sid : ((state == DISCARD) ? 1'b0 : 1'b1);
66
67   //
68   // Buffer output, break combinatorial timing paths
69   //
70   axi_fifo_short #(.WIDTH(65)) fifo_short
71     (
72      .clk(clk), .reset(reset), .clear(clear),
73      .i_tdata(i_tdata), .i_tvalid(i_tvalid && qualify_i_tvalid), .i_tready(i_tready),
74      .o_tdata(o_tdata), .o_tvalid(o_tvalid), .o_tready(o_tready),
75      .space(), .occupied()
76      );
77
78endmodule // filter_bad_sid
79