1// -*- verilog -*-
2//
3//  USRP - Universal Software Radio Peripheral
4//
5//  Copyright (C) 2003 Matt Ettus
6//
7//  SPDX-License-Identifier: LGPL-3.0-or-later
8//
9
10//
11
12
13// Sign extension "macro"
14// bits_out should be greater than bits_in
15
16module sign_extend (in,out);
17	parameter bits_in=0;  // FIXME Quartus insists on a default
18	parameter bits_out=0;
19
20	input [bits_in-1:0] in;
21	output [bits_out-1:0] out;
22
23	assign out = {{(bits_out-bits_in){in[bits_in-1]}},in};
24
25endmodule
26