1// *************************************************************************** 2// *************************************************************************** 3// Copyright 2013(c) Analog Devices, Inc. 4// Author: Lars-Peter Clausen <lars@metafoo.de> 5// 6// All rights reserved. 7// 8// Redistribution and use in source and binary forms, with or without modification, 9// are permitted provided that the following conditions are met: 10// - Redistributions of source code must retain the above copyright 11// notice, this list of conditions and the following disclaimer. 12// - Redistributions in binary form must reproduce the above copyright 13// notice, this list of conditions and the following disclaimer in 14// the documentation and/or other materials provided with the 15// distribution. 16// - Neither the name of Analog Devices, Inc. nor the names of its 17// contributors may be used to endorse or promote products derived 18// from this software without specific prior written permission. 19// - The use of this software may or may not infringe the patent rights 20// of one or more patent holders. This license does not release you 21// from the requirement that you obtain separate licenses from these 22// patent holders to use this software. 23// - Use of the software either in source or binary form, must be run 24// on or directly connected to an Analog Devices Inc. component. 25// 26// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 27// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A 28// PARTICULAR PURPOSE ARE DISCLAIMED. 29// 30// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY 32// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 33// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 34// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 35// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36// *************************************************************************** 37// *************************************************************************** 38 39module dmac_dest_mm_axi ( 40 input m_axi_aclk, 41 input m_axi_aresetn, 42 43 input req_valid, 44 output req_ready, 45 input [31:BYTES_PER_BEAT_WIDTH] req_address, 46 input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, 47 input [BYTES_PER_BEAT_WIDTH-1:0] req_last_beat_bytes, 48 49 input enable, 50 output enabled, 51 input pause, 52 input sync_id, 53 output sync_id_ret, 54 55 output response_valid, 56 input response_ready, 57 output [1:0] response_resp, 58 output response_resp_eot, 59 60 input [ID_WIDTH-1:0] request_id, 61 output [ID_WIDTH-1:0] response_id, 62 63 output [ID_WIDTH-1:0] data_id, 64 output [ID_WIDTH-1:0] address_id, 65 input data_eot, 66 input address_eot, 67 input response_eot, 68 69 input fifo_valid, 70 output fifo_ready, 71 input [DMA_DATA_WIDTH-1:0] fifo_data, 72 73 // Write address 74 input m_axi_awready, 75 output m_axi_awvalid, 76 output [31:0] m_axi_awaddr, 77 output [ 7:0] m_axi_awlen, 78 output [ 2:0] m_axi_awsize, 79 output [ 1:0] m_axi_awburst, 80 output [ 2:0] m_axi_awprot, 81 output [ 3:0] m_axi_awcache, 82 83 // Write data 84 output [DMA_DATA_WIDTH-1:0] m_axi_wdata, 85 output [(DMA_DATA_WIDTH/8)-1:0] m_axi_wstrb, 86 input m_axi_wready, 87 output m_axi_wvalid, 88 output m_axi_wlast, 89 90 // Write response 91 input m_axi_bvalid, 92 input [ 1:0] m_axi_bresp, 93 output m_axi_bready 94); 95 96parameter ID_WIDTH = 3; 97parameter DMA_DATA_WIDTH = 64; 98parameter BYTES_PER_BEAT_WIDTH = $clog2(DMA_DATA_WIDTH/8); 99parameter BEATS_PER_BURST_WIDTH = 4; 100 101reg [(DMA_DATA_WIDTH/8)-1:0] wstrb; 102 103wire address_req_valid; 104wire address_req_ready; 105wire data_req_valid; 106wire data_req_ready; 107 108wire address_enabled; 109wire data_enabled; 110assign sync_id_ret = sync_id; 111 112wire _fifo_ready; 113assign fifo_ready = _fifo_ready | ~enabled; 114 115splitter #( 116 .NUM_M(2) 117) i_req_splitter ( 118 .clk(m_axi_aclk), 119 .resetn(m_axi_aresetn), 120 .s_valid(req_valid), 121 .s_ready(req_ready), 122 .m_valid({ 123 address_req_valid, 124 data_req_valid 125 }), 126 .m_ready({ 127 address_req_ready, 128 data_req_ready 129 }) 130); 131 132dmac_address_generator #( 133 .ID_WIDTH(ID_WIDTH), 134 .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH), 135 .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH), 136 .DMA_DATA_WIDTH(DMA_DATA_WIDTH) 137) i_addr_gen ( 138 .clk(m_axi_aclk), 139 .resetn(m_axi_aresetn), 140 141 .enable(enable), 142 .enabled(address_enabled), 143 .pause(pause), 144 145 .id(address_id), 146 .request_id(request_id), 147 .sync_id(sync_id), 148 149 .req_valid(address_req_valid), 150 .req_ready(address_req_ready), 151 .req_address(req_address), 152 .req_last_burst_length(req_last_burst_length), 153 154 .eot(address_eot), 155 156 .addr_ready(m_axi_awready), 157 .addr_valid(m_axi_awvalid), 158 .addr(m_axi_awaddr), 159 .len(m_axi_awlen), 160 .size(m_axi_awsize), 161 .burst(m_axi_awburst), 162 .prot(m_axi_awprot), 163 .cache(m_axi_awcache) 164); 165 166dmac_data_mover # ( 167 .ID_WIDTH(ID_WIDTH), 168 .DATA_WIDTH(DMA_DATA_WIDTH), 169 .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH) 170) i_data_mover ( 171 .clk(m_axi_aclk), 172 .resetn(m_axi_aresetn), 173 174 .enable(address_enabled), 175 .enabled(data_enabled), 176 177 .xfer_req(), 178 179 .request_id(address_id), 180 .response_id(data_id), 181 .sync_id(sync_id), 182 .eot(data_eot), 183 184 .req_valid(data_req_valid), 185 .req_ready(data_req_ready), 186 .req_last_burst_length(req_last_burst_length), 187 188 .s_axi_valid(fifo_valid), 189 .s_axi_ready(_fifo_ready), 190 .s_axi_data(fifo_data), 191 .m_axi_valid(m_axi_wvalid), 192 .m_axi_ready(m_axi_wready), 193 .m_axi_data(m_axi_wdata), 194 .m_axi_last(m_axi_wlast) 195); 196 197always @(*) 198begin 199 if (data_eot & m_axi_wlast) begin 200 wstrb <= (1 << (req_last_beat_bytes + 1)) - 1; 201 end else begin 202 wstrb <= {(DMA_DATA_WIDTH/8){1'b1}}; 203 end 204end 205 206assign m_axi_wstrb = wstrb; 207 208dmac_response_handler #( 209 .ID_WIDTH(ID_WIDTH) 210) i_response_handler ( 211 .clk(m_axi_aclk), 212 .resetn(m_axi_aresetn), 213 .bvalid(m_axi_bvalid), 214 .bready(m_axi_bready), 215 .bresp(m_axi_bresp), 216 217 .enable(data_enabled), 218 .enabled(enabled), 219 220 .id(response_id), 221 .request_id(data_id), 222 .sync_id(sync_id), 223 224 .eot(response_eot), 225 226 .resp_valid(response_valid), 227 .resp_ready(response_ready), 228 .resp_resp(response_resp), 229 .resp_eot(response_resp_eot) 230); 231 232endmodule 233