1------------------------------------------------------------------------------- 2-- Title : Package for WR Steamers 3-- Project : WR Streamers 4-- URL : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers 5------------------------------------------------------------------------------- 6-- File : streamers_pkg.vhd 7-- Author : Tomasz Wlostowski <tomasz.wlostowski@cern.ch> 8-- Company : CERN 9-- Platform : FPGA-generics 10-- Standard : VHDL 11-- Created : 2012-10-01 12------------------------------------------------------------------------------- 13-- Description: 14-- 15-- Package with declaration of streamer components, types and constants. 16------------------------------------------------------------------------------- 17-- 18-- Copyright (c) 2012-2017 CERN/BE-CO-HT 19-- 20-- This source file is free software; you can redistribute it 21-- and/or modify it under the terms of the GNU Lesser General 22-- Public License as published by the Free Software Foundation; 23-- either version 2.1 of the License, or (at your option) any 24-- later version. 25-- 26-- This source is distributed in the hope that it will be 27-- useful, but WITHOUT ANY WARRANTY; without even the implied 28-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 29-- PURPOSE. See the GNU Lesser General Public License for more 30-- details. 31-- 32-- You should have received a copy of the GNU Lesser General 33-- Public License along with this source; if not, download it 34-- from http://www.gnu.org/licenses/lgpl-2.1.html 35-- 36------------------------------------------------------------------------------- 37 38library ieee; 39use ieee.std_logic_1164.all; 40use work.wr_fabric_pkg.all; 41use work.wrcore_pkg.all; 42use work.wishbone_pkg.all; -- needed for t_wishbone_slave_in, etc 43 44package streamers_pkg is 45 type t_streamers_op_mode is (RX_ONLY, TX_ONLY, TX_AND_RX); 46 ----------------------------------------------------------------------------------------- 47 -- Transmission parameters (tx) 48 ----------------------------------------------------------------------------------------- 49 type t_tx_streamer_params is record 50 -- Width of data words on tx_data_i, must be multiple of 16 bits. 51 data_width : integer; 52 53 -- Size of Tx buffer, in data words. 54 buffer_size : integer; 55 56 -- Minimum number of data words in the TX buffer that will trigger transmission of an 57 -- Ethernet frame. It cannot be breater than g_tx_buffer_size; it is recommended that 58 -- g_tx_buffer_size = 2 * g_tx_threshold. 59 -- Note that in order for a frame to be transmitted, the buffer must conatain at 60 -- least one complete block.ransmitted, the buffer must conatain at 61 -- least one complete block. 62 threshold : integer; 63 64 -- Maximum number of data words in a single Ethernet frame. It also defines 65 -- the maximum block size (since blocks can't be currently split across 66 -- multiple frames). It cannot be greater than g_tx_buffer_size 67 max_words_per_frame : integer; 68 69 -- Transmission timeout (in clk_sys_i cycles), after which the contents 70 -- of TX buffer are sent regardless of the amount of data that is currently 71 -- stored in the buffer, so that data in the buffer does not get stuck. 72 timeout : integer; 73 74 -- DO NOT USE unless you know what you are doing 75 -- legacy: the streamers initially used in Btrain did not check/insert the escape 76 -- code. This is justified if only one block of a known number of words is sent/expected 77 escape_code_disable : boolean; 78 end record; 79 80 ----------------------------------------------------------------------------------------- 81 -- Reception parameters (rx) 82 ----------------------------------------------------------------------------------------- 83 type t_rx_streamer_params is record 84 -- Width of the data words, must be multiple of 16 bits. This value set to this generic 85 -- on the receviving device must be the same as the value of g_tx_data_width set on the 86 -- transmitting node. The g_rx_data_width and g_tx_data_width can be set to different 87 -- values in the same device (i.e. instantiation of xwr_transmission entity). It is the 88 -- responsibility of a network designer to make sure these parameters are properly set 89 -- in the network. 90 data_width : integer; 91 92 -- Size of RX buffer, in data words. 93 buffer_size : integer; 94 95 -- DO NOT USE unless you know what you are doing 96 -- legacy: the streamers that were initially used in Btrain did not check/insert 97 -- the escape code. This is justified if only one block of a known number of words is 98 -- sent/expected. 99 escape_code_disable : boolean; 100 101 -- DO NOT USE unless you know what you are doing 102 -- legacy: the streamers that were initially used in Btrain accepted only a fixed 103 -- number of words, regardless of the frame content. If this generic is set to number 104 -- other than zero, only a fixed number of words is accepted. 105 -- In combination with the g_escape_code_disable generic set to TRUE, the behaviour of 106 -- the "Btrain streamers" can be recreated. 107 expected_words_number : integer; 108 end record; 109 110 constant c_tx_streamer_params_defaut: t_tx_streamer_params :=( 111 data_width => 32, 112 buffer_size => 256, 113 threshold => 128, 114 max_words_per_frame => 256, 115 timeout => 1024, 116 escape_code_disable => FALSE); 117 118 constant c_rx_streamer_params_defaut: t_rx_streamer_params :=( 119 data_width => 32, 120 buffer_size => 256, 121 escape_code_disable => FALSE, 122 expected_words_number => 0); 123 124 type t_rx_streamer_cfg is record 125 -- Local MAC address. Leave at 0x0...0 when using with the WR MAC/Core, it will 126 -- insert its own source MAC. 127 mac_local : std_logic_vector(47 downto 0); 128 -- Remote MAC address, i.e. MAC of the device from which the data should be accpated 129 mac_remote : std_logic_vector(47 downto 0); 130 -- Ethertype of our frames. Default value is accepted by standard 131 -- configuration of the WR PTP Core 132 ethertype : std_logic_vector(15 downto 0); 133 -- 1: accept all broadcast packets 134 -- 0: accept only unicasts 135 accept_broadcasts : std_logic; 136 -- filtering of streamer frames on reception by source MAC address 137 -- 0: accept frames from any source 138 -- 1: accept frames only from the source MAC address defined in cfg_mac_remote_i 139 filter_remote : std_logic; 140 -- value in cycles of fixed-latency enforced on data 141 fixed_latency : std_logic_vector(27 downto 0); 142 end record; 143 144 type t_tx_streamer_cfg is record 145 -- Local MAC address. Leave at 0x0...0 when using with the WR MAC/Core, it will 146 -- insert its own source MAC. 147 mac_local : std_logic_vector(47 downto 0); 148 -- Destination MAC address, i.e. MAC of a device to which data is streamed. 149 mac_target : std_logic_vector(47 downto 0); 150 -- Ethertype of our frames. Default value is accepted by standard 151 -- configuration of the WR PTP Core 152 ethertype : std_logic_vector(15 downto 0); 153 -- enable tagging with VLAN tags 154 qtag_ena : std_logic; 155 ---VLAN used to tag 156 qtag_vid : std_logic_vector(11 downto 0); 157 -- priority used to tag 158 qtag_prio : std_logic_vector(2 downto 0); 159 end record; 160 161 constant c_rx_streamer_cfg_default: t_rx_streamer_cfg :=( 162 mac_local => x"000000000000", 163 mac_remote => x"000000000000", 164 ethertype => x"dbff", 165 accept_broadcasts => '1', 166 filter_remote => '0', 167 fixed_latency => x"0000000"); 168 169 constant c_tx_streamer_cfg_default: t_tx_streamer_cfg :=( 170 mac_local => x"000000000000", 171 mac_target => x"ffffffffffff", 172 ethertype => x"dbff", 173 qtag_ena => '0', 174 qtag_vid => x"000", 175 qtag_prio => "000"); 176 177 component xtx_streamer 178 generic ( 179 g_data_width : integer := 32; 180 g_tx_buffer_size : integer := 256; 181 g_tx_threshold : integer := 128; 182 g_tx_max_words_per_frame : integer := 256; 183 g_tx_timeout : integer := 1024; 184 g_escape_code_disable : boolean := FALSE; 185 g_simulation : integer := 0; 186 g_sim_startup_cnt : integer := 6250);--100us 187 port ( 188 clk_sys_i : in std_logic; 189 rst_n_i : in std_logic; 190 src_i : in t_wrf_source_in; 191 src_o : out t_wrf_source_out; 192 clk_ref_i : in std_logic := '0'; 193 tm_time_valid_i : in std_logic := '0'; 194 tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000"; 195 tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000"; 196 link_ok_i : in std_logic := '1'; 197 tx_data_i : in std_logic_vector(g_data_width-1 downto 0); 198 tx_valid_i : in std_logic; 199 tx_dreq_o : out std_logic; 200 tx_last_p1_i : in std_logic := '1'; 201 tx_flush_p1_i : in std_logic := '0'; 202 tx_reset_seq_i : in std_logic := '0'; 203 tx_frame_p1_o : out std_logic; 204 tx_streamer_cfg_i: in t_tx_streamer_cfg := c_tx_streamer_cfg_default); 205 end component; 206 207 component xrx_streamer 208 generic ( 209 g_data_width : integer := 32; 210 g_buffer_size : integer := 256; 211 g_escape_code_disable : boolean := FALSE; 212 g_expected_words_number : integer := 0); 213 port ( 214 clk_sys_i : in std_logic; 215 rst_n_i : in std_logic; 216 snk_i : in t_wrf_sink_in; 217 snk_o : out t_wrf_sink_out; 218 clk_ref_i : in std_logic := '0'; 219 tm_time_valid_i : in std_logic := '0'; 220 tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000"; 221 tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000"; 222 rx_first_p1_o : out std_logic; 223 rx_last_p1_o : out std_logic; 224 rx_data_o : out std_logic_vector(g_data_width-1 downto 0); 225 rx_valid_o : out std_logic; 226 rx_dreq_i : in std_logic; 227 rx_lost_p1_o : out std_logic := '0'; 228 rx_lost_blocks_p1_o : out std_logic := '0'; 229 rx_lost_frames_p1_o : out std_logic := '0'; 230 rx_lost_frames_cnt_o : out std_logic_vector(14 downto 0); 231 rx_latency_o : out std_logic_vector(27 downto 0); 232 rx_latency_valid_o : out std_logic; 233 rx_frame_p1_o : out std_logic; 234 rx_streamer_cfg_i : in t_rx_streamer_cfg := c_rx_streamer_cfg_default); 235 end component; 236 237 constant c_WRS_STATS_ARR_SIZE_OUT : integer := 18; 238 constant c_WRS_STATS_ARR_SIZE_IN : integer := 1; 239 240 component xrtx_streamers_stats is 241 generic ( 242 g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX; 243 g_cnt_width : integer := 50; 244 g_acc_width : integer := 64 245 ); 246 port ( 247 clk_i : in std_logic; 248 rst_n_i : in std_logic; 249 sent_frame_i : in std_logic; 250 rcvd_frame_i : in std_logic; 251 lost_block_i : in std_logic; 252 lost_frame_i : in std_logic; 253 lost_frames_cnt_i : in std_logic_vector(14 downto 0); 254 rcvd_latency_i : in std_logic_vector(27 downto 0); 255 rcvd_latency_valid_i : in std_logic; 256 clk_ref_i : in std_logic; 257 tm_time_valid_i : in std_logic := '0'; 258 tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000"; 259 tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000"; 260 reset_stats_i : in std_logic; 261 snapshot_ena_i : in std_logic := '0'; 262 reset_time_tai_o : out std_logic_vector(39 downto 0) := x"0000000000"; 263 reset_time_cycles_o : out std_logic_vector(27 downto 0) := x"0000000"; 264 sent_frame_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0); 265 rcvd_frame_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0); 266 lost_frame_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0); 267 lost_block_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0); 268 latency_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0); 269 latency_acc_overflow_o : out std_logic; 270 latency_acc_o : out std_logic_vector(g_acc_width-1 downto 0); 271 latency_max_o : out std_logic_vector(27 downto 0); 272 latency_min_o : out std_logic_vector(27 downto 0); 273 snmp_array_o : out t_generic_word_array(c_WRS_STATS_ARR_SIZE_OUT-1 downto 0); 274 snmp_array_i : in t_generic_word_array(c_WRS_STATS_ARR_SIZE_IN -1 downto 0) := (others => (others=>'0')) 275 ); 276 end component; 277 278 constant c_WR_STREAMERS_ARR_SIZE_OUT : integer := c_WRS_STATS_ARR_SIZE_OUT+2; 279 constant c_WR_STREAMERS_ARR_SIZE_IN : integer := c_WRS_STATS_ARR_SIZE_IN; 280 281 component xwr_streamers is 282 generic ( 283 g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX; 284 --tx/rx 285 g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut; 286 g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut; 287 -- stats 288 g_stats_cnt_width : integer := 50; 289 g_stats_acc_width : integer := 64; 290 -- WB i/f 291 g_slave_mode : t_wishbone_interface_mode := CLASSIC; 292 g_slave_granularity : t_wishbone_address_granularity := BYTE; 293 g_simulation : integer := 0 294 ); 295 296 port ( 297 clk_sys_i : in std_logic; 298 rst_n_i : in std_logic; 299 -- WR tx/rx interface 300 src_i : in t_wrf_source_in; 301 src_o : out t_wrf_source_out; 302 snk_i : in t_wrf_sink_in; 303 snk_o : out t_wrf_sink_out; 304 -- User tx interface 305 tx_data_i : in std_logic_vector(g_tx_streamer_params.data_width-1 downto 0); 306 tx_valid_i : in std_logic; 307 tx_dreq_o : out std_logic; 308 tx_last_p1_i : in std_logic := '1'; 309 tx_flush_p1_i : in std_logic := '0'; 310 -- User rx interface 311 rx_first_p1_o : out std_logic; 312 rx_last_p1_o : out std_logic; 313 rx_data_o : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0); 314 rx_valid_o : out std_logic; 315 rx_dreq_i : in std_logic; 316 -- WRC Timing interface, used for latency measurement 317 clk_ref_i : in std_logic := '0'; 318 tm_time_valid_i : in std_logic := '0'; 319 tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000"; 320 tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000"; 321 link_ok_i : in std_logic := '1'; 322 wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in; 323 wb_slave_o : out t_wishbone_slave_out; 324 snmp_array_o : out t_generic_word_array(c_WR_STREAMERS_ARR_SIZE_OUT-1 downto 0); 325 snmp_array_i : in t_generic_word_array(c_WR_STREAMERS_ARR_SIZE_IN -1 downto 0); 326 -- Transmission (tx) configuration 327 tx_streamer_cfg_i : in t_tx_streamer_cfg := c_tx_streamer_cfg_default; 328 rx_streamer_cfg_i : in t_rx_streamer_cfg := c_rx_streamer_cfg_default 329 ); 330 end component; 331 332end streamers_pkg;