1--------------------------------------------------------------------------------
2--
3-- FIFO Generator Core Demo Testbench
4--
5--------------------------------------------------------------------------------
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52--------------------------------------------------------------------------------
53--
54-- Filename: fifo_4k_2clk_dverif.vhd
55--
56-- Description:
57--   Used for FIFO read interface stimulus generation and data checking
58--
59--------------------------------------------------------------------------------
60-- Library Declarations
61--------------------------------------------------------------------------------
62LIBRARY ieee;
63USE ieee.std_logic_1164.ALL;
64USE ieee.std_logic_unsigned.all;
65USE IEEE.std_logic_arith.all;
66USE IEEE.std_logic_misc.all;
67
68LIBRARY work;
69USE work.fifo_4k_2clk_pkg.ALL;
70
71ENTITY fifo_4k_2clk_dverif IS
72  GENERIC(
73   C_DIN_WIDTH        : INTEGER := 0;
74   C_DOUT_WIDTH       : INTEGER := 0;
75   C_USE_EMBEDDED_REG : INTEGER := 0;
76   C_CH_TYPE          : INTEGER := 0;
77   TB_SEED            : INTEGER := 2
78  );
79  PORT(
80       RESET          : IN STD_LOGIC;
81       RD_CLK         : IN STD_LOGIC;
82       PRC_RD_EN      : IN STD_LOGIC;
83       EMPTY          : IN STD_LOGIC;
84       DATA_OUT       : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
85       RD_EN          : OUT STD_LOGIC;
86       DOUT_CHK       : OUT STD_LOGIC
87      );
88END ENTITY;
89
90
91ARCHITECTURE fg_dv_arch OF fifo_4k_2clk_dverif IS
92
93 CONSTANT C_DATA_WIDTH    : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
94 CONSTANT EXTRA_WIDTH     : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
95 CONSTANT LOOP_COUNT      : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
96
97 SIGNAL expected_dout     : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
98 SIGNAL data_chk          : STD_LOGIC := '1';
99 SIGNAL rand_num          : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
100 SIGNAL rd_en_i           : STD_LOGIC := '0';
101 SIGNAL pr_r_en           : STD_LOGIC := '0';
102 SIGNAL rd_en_d1          : STD_LOGIC := '1';
103BEGIN
104
105
106  DOUT_CHK <= data_chk;
107  RD_EN    <= rd_en_i;
108  rd_en_i  <= PRC_RD_EN;
109  rd_en_d1 <= '1';
110
111
112  data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
113  -------------------------------------------------------
114  -- Expected data generation and checking for data_fifo
115  -------------------------------------------------------
116
117      pr_r_en       <= rd_en_i AND NOT EMPTY AND rd_en_d1;
118      expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
119
120    gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
121      rd_gen_inst2:fifo_4k_2clk_rng
122      GENERIC MAP(
123      	        WIDTH => 8,
124                SEED  => TB_SEED+N
125                 )
126      PORT MAP(
127                CLK        => RD_CLK,
128	        RESET      => RESET,
129                RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
130                ENABLE     => pr_r_en
131              );
132    END GENERATE;
133
134      PROCESS (RD_CLK,RESET)
135      BEGIN
136        IF(RESET = '1') THEN
137          data_chk <= '0';
138        ELSIF (RD_CLK'event AND RD_CLK='1') THEN
139          IF(EMPTY = '0') THEN
140            IF(DATA_OUT = expected_dout) THEN
141              data_chk <= '0';
142            ELSE
143              data_chk <= '1';
144            END IF;
145          END IF;
146        END IF;
147      END PROCESS;
148  END GENERATE data_fifo_chk;
149
150END ARCHITECTURE;
151