1-------------------------------------------------------------------------------- 2-- 3-- FIFO Generator Core - core top file for implementation 4-- 5-------------------------------------------------------------------------------- 6-- 7-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. 8-- 9-- This file contains confidential and proprietary information 10-- of Xilinx, Inc. and is protected under U.S. and 11-- international copyright and other intellectual property 12-- laws. 13-- 14-- DISCLAIMER 15-- This disclaimer is not a license and does not grant any 16-- rights to the materials distributed herewith. Except as 17-- otherwise provided in a valid license issued to you by 18-- Xilinx, and to the maximum extent permitted by applicable 19-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 20-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 21-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 22-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 23-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 24-- (2) Xilinx shall not be liable (whether in contract or tort, 25-- including negligence, or under any other theory of 26-- liability) for any loss or damage of any kind or nature 27-- related to, arising under or in connection with these 28-- materials, including for any direct, or any indirect, 29-- special, incidental, or consequential loss or damage 30-- (including loss of data, profits, goodwill, or any type of 31-- loss or damage suffered as a result of any action brought 32-- by a third party) even if such damage or loss was 33-- reasonably foreseeable or Xilinx had been advised of the 34-- possibility of the same. 35-- 36-- CRITICAL APPLICATIONS 37-- Xilinx products are not designed or intended to be fail- 38-- safe, or for use in any application requiring fail-safe 39-- performance, such as life-support or safety devices or 40-- systems, Class III medical devices, nuclear facilities, 41-- applications related to the deployment of airbags, or any 42-- other applications that could lead to death, personal 43-- injury, or severe property or environmental damage 44-- (individually and collectively, "Critical 45-- Applications"). Customer assumes the sole risk and 46-- liability of any use of Xilinx products in Critical 47-- Applications, subject only to applicable laws and 48-- regulations governing limitations on product liability. 49-- 50-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 51-- PART OF THIS FILE AT ALL TIMES. 52-------------------------------------------------------------------------------- 53-- 54-- Filename: fifo_4k_2clk_exdes.vhd 55-- 56-- Description: 57-- This is the FIFO core wrapper with BUFG instances for clock connections. 58-- 59-------------------------------------------------------------------------------- 60-- Library Declarations 61-------------------------------------------------------------------------------- 62 63library ieee; 64use ieee.std_logic_1164.all; 65use ieee.std_logic_arith.all; 66use ieee.std_logic_unsigned.all; 67 68library unisim; 69use unisim.vcomponents.all; 70 71-------------------------------------------------------------------------------- 72-- Entity Declaration 73-------------------------------------------------------------------------------- 74entity fifo_4k_2clk_exdes is 75 PORT ( 76 WR_CLK : IN std_logic; 77 RD_CLK : IN std_logic; 78 WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0); 79 RD_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0); 80 RST : IN std_logic; 81 WR_EN : IN std_logic; 82 RD_EN : IN std_logic; 83 DIN : IN std_logic_vector(72-1 DOWNTO 0); 84 DOUT : OUT std_logic_vector(72-1 DOWNTO 0); 85 FULL : OUT std_logic; 86 EMPTY : OUT std_logic); 87 88end fifo_4k_2clk_exdes; 89 90 91 92architecture xilinx of fifo_4k_2clk_exdes is 93 94 signal wr_clk_i : std_logic; 95 signal rd_clk_i : std_logic; 96 97 98 99 component fifo_4k_2clk is 100 PORT ( 101 WR_CLK : IN std_logic; 102 RD_CLK : IN std_logic; 103 WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0); 104 RD_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0); 105 RST : IN std_logic; 106 WR_EN : IN std_logic; 107 RD_EN : IN std_logic; 108 DIN : IN std_logic_vector(72-1 DOWNTO 0); 109 DOUT : OUT std_logic_vector(72-1 DOWNTO 0); 110 FULL : OUT std_logic; 111 EMPTY : OUT std_logic); 112 113 end component; 114 115 116begin 117 118 wr_clk_buf: bufg 119 PORT map( 120 i => WR_CLK, 121 o => wr_clk_i 122 ); 123 124 rd_clk_buf: bufg 125 PORT map( 126 i => RD_CLK, 127 o => rd_clk_i 128 ); 129 130 131 exdes_inst : fifo_4k_2clk 132 PORT MAP ( 133 WR_CLK => wr_clk_i, 134 RD_CLK => rd_clk_i, 135 WR_DATA_COUNT => wr_data_count, 136 RD_DATA_COUNT => rd_data_count, 137 RST => rst, 138 WR_EN => wr_en, 139 RD_EN => rd_en, 140 DIN => din, 141 DOUT => dout, 142 FULL => full, 143 EMPTY => empty); 144 145end xilinx; 146