1-------------------------------------------------------------------------------- 2-- 3-- FIFO Generator Core Demo Testbench 4-- 5-------------------------------------------------------------------------------- 6-- 7-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. 8-- 9-- This file contains confidential and proprietary information 10-- of Xilinx, Inc. and is protected under U.S. and 11-- international copyright and other intellectual property 12-- laws. 13-- 14-- DISCLAIMER 15-- This disclaimer is not a license and does not grant any 16-- rights to the materials distributed herewith. Except as 17-- otherwise provided in a valid license issued to you by 18-- Xilinx, and to the maximum extent permitted by applicable 19-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 20-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 21-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 22-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 23-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 24-- (2) Xilinx shall not be liable (whether in contract or tort, 25-- including negligence, or under any other theory of 26-- liability) for any loss or damage of any kind or nature 27-- related to, arising under or in connection with these 28-- materials, including for any direct, or any indirect, 29-- special, incidental, or consequential loss or damage 30-- (including loss of data, profits, goodwill, or any type of 31-- loss or damage suffered as a result of any action brought 32-- by a third party) even if such damage or loss was 33-- reasonably foreseeable or Xilinx had been advised of the 34-- possibility of the same. 35-- 36-- CRITICAL APPLICATIONS 37-- Xilinx products are not designed or intended to be fail- 38-- safe, or for use in any application requiring fail-safe 39-- performance, such as life-support or safety devices or 40-- systems, Class III medical devices, nuclear facilities, 41-- applications related to the deployment of airbags, or any 42-- other applications that could lead to death, personal 43-- injury, or severe property or environmental damage 44-- (individually and collectively, "Critical 45-- Applications"). Customer assumes the sole risk and 46-- liability of any use of Xilinx products in Critical 47-- Applications, subject only to applicable laws and 48-- regulations governing limitations on product liability. 49-- 50-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 51-- PART OF THIS FILE AT ALL TIMES. 52-------------------------------------------------------------------------------- 53-- 54-- Filename: fifo_short_2clk_synth.vhd 55-- 56-- Description: 57-- This is the demo testbench for fifo_generator core. 58-- 59-------------------------------------------------------------------------------- 60-- Library Declarations 61-------------------------------------------------------------------------------- 62 63 64LIBRARY ieee; 65USE ieee.STD_LOGIC_1164.ALL; 66USE ieee.STD_LOGIC_unsigned.ALL; 67USE IEEE.STD_LOGIC_arith.ALL; 68USE ieee.numeric_std.ALL; 69USE ieee.STD_LOGIC_misc.ALL; 70 71LIBRARY std; 72USE std.textio.ALL; 73 74LIBRARY work; 75USE work.fifo_short_2clk_pkg.ALL; 76 77-------------------------------------------------------------------------------- 78-- Entity Declaration 79-------------------------------------------------------------------------------- 80ENTITY fifo_short_2clk_synth IS 81 GENERIC( 82 FREEZEON_ERROR : INTEGER := 0; 83 TB_STOP_CNT : INTEGER := 0; 84 TB_SEED : INTEGER := 1 85 ); 86 PORT( 87 WR_CLK : IN STD_LOGIC; 88 RD_CLK : IN STD_LOGIC; 89 RESET : IN STD_LOGIC; 90 SIM_DONE : OUT STD_LOGIC; 91 STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) 92 ); 93END ENTITY; 94 95ARCHITECTURE simulation_arch OF fifo_short_2clk_synth IS 96 97 -- FIFO interface signal declarations 98 SIGNAL wr_clk_i : STD_LOGIC; 99 SIGNAL rd_clk_i : STD_LOGIC; 100 SIGNAL wr_data_count : STD_LOGIC_VECTOR(6-1 DOWNTO 0); 101 SIGNAL rd_data_count : STD_LOGIC_VECTOR(6-1 DOWNTO 0); 102 SIGNAL rst : STD_LOGIC; 103 SIGNAL wr_en : STD_LOGIC; 104 SIGNAL rd_en : STD_LOGIC; 105 SIGNAL din : STD_LOGIC_VECTOR(72-1 DOWNTO 0); 106 SIGNAL dout : STD_LOGIC_VECTOR(72-1 DOWNTO 0); 107 SIGNAL full : STD_LOGIC; 108 SIGNAL empty : STD_LOGIC; 109 -- TB Signals 110 SIGNAL wr_data : STD_LOGIC_VECTOR(72-1 DOWNTO 0); 111 SIGNAL dout_i : STD_LOGIC_VECTOR(72-1 DOWNTO 0); 112 SIGNAL wr_en_i : STD_LOGIC := '0'; 113 SIGNAL rd_en_i : STD_LOGIC := '0'; 114 SIGNAL full_i : STD_LOGIC := '0'; 115 SIGNAL empty_i : STD_LOGIC := '0'; 116 SIGNAL almost_full_i : STD_LOGIC := '0'; 117 SIGNAL almost_empty_i : STD_LOGIC := '0'; 118 SIGNAL prc_we_i : STD_LOGIC := '0'; 119 SIGNAL prc_re_i : STD_LOGIC := '0'; 120 SIGNAL dout_chk_i : STD_LOGIC := '0'; 121 SIGNAL rst_int_rd : STD_LOGIC := '0'; 122 SIGNAL rst_int_wr : STD_LOGIC := '0'; 123 SIGNAL rst_s_wr1 : STD_LOGIC := '0'; 124 SIGNAL rst_s_wr2 : STD_LOGIC := '0'; 125 SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); 126 SIGNAL rst_s_wr3 : STD_LOGIC := '0'; 127 SIGNAL rst_s_rd : STD_LOGIC := '0'; 128 SIGNAL reset_en : STD_LOGIC := '0'; 129 SIGNAL rst_async_wr1 : STD_LOGIC := '0'; 130 SIGNAL rst_async_wr2 : STD_LOGIC := '0'; 131 SIGNAL rst_async_wr3 : STD_LOGIC := '0'; 132 SIGNAL rst_async_rd1 : STD_LOGIC := '0'; 133 SIGNAL rst_async_rd2 : STD_LOGIC := '0'; 134 SIGNAL rst_async_rd3 : STD_LOGIC := '0'; 135 136 137 BEGIN 138 139 ---- Reset generation logic ----- 140 rst_int_wr <= rst_async_wr3 OR rst_s_wr3; 141 rst_int_rd <= rst_async_rd3 OR rst_s_rd; 142 143 --Testbench reset synchronization 144 PROCESS(rd_clk_i,RESET) 145 BEGIN 146 IF(RESET = '1') THEN 147 rst_async_rd1 <= '1'; 148 rst_async_rd2 <= '1'; 149 rst_async_rd3 <= '1'; 150 ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN 151 rst_async_rd1 <= RESET; 152 rst_async_rd2 <= rst_async_rd1; 153 rst_async_rd3 <= rst_async_rd2; 154 END IF; 155 END PROCESS; 156 157 PROCESS(wr_clk_i,RESET) 158 BEGIN 159 IF(RESET = '1') THEN 160 rst_async_wr1 <= '1'; 161 rst_async_wr2 <= '1'; 162 rst_async_wr3 <= '1'; 163 ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN 164 rst_async_wr1 <= RESET; 165 rst_async_wr2 <= rst_async_wr1; 166 rst_async_wr3 <= rst_async_wr2; 167 END IF; 168 END PROCESS; 169 170 --Soft reset for core and testbench 171 PROCESS(rd_clk_i) 172 BEGIN 173 IF(rd_clk_i'event AND rd_clk_i='1') THEN 174 rst_gen_rd <= rst_gen_rd + "1"; 175 IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN 176 rst_s_rd <= '1'; 177 assert false 178 report "Reset applied..Memory Collision checks are not valid" 179 severity note; 180 ELSE 181 IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN 182 rst_s_rd <= '0'; 183 END IF; 184 END IF; 185 END IF; 186 END PROCESS; 187 188 PROCESS(wr_clk_i) 189 BEGIN 190 IF(wr_clk_i'event AND wr_clk_i='1') THEN 191 rst_s_wr1 <= rst_s_rd; 192 rst_s_wr2 <= rst_s_wr1; 193 rst_s_wr3 <= rst_s_wr2; 194 IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN 195 assert false 196 report "Reset removed..Memory Collision checks are valid" 197 severity note; 198 END IF; 199 END IF; 200 END PROCESS; 201 ------------------ 202 203 ---- Clock buffers for testbench ---- 204 wr_clk_i <= WR_CLK; 205 rd_clk_i <= RD_CLK; 206 ------------------ 207 208 rst <= RESET OR rst_s_rd AFTER 12 ns; 209 din <= wr_data; 210 dout_i <= dout; 211 wr_en <= wr_en_i; 212 rd_en <= rd_en_i; 213 full_i <= full; 214 empty_i <= empty; 215 216 fg_dg_nv: fifo_short_2clk_dgen 217 GENERIC MAP ( 218 C_DIN_WIDTH => 72, 219 C_DOUT_WIDTH => 72, 220 TB_SEED => TB_SEED, 221 C_CH_TYPE => 0 222 ) 223 PORT MAP ( -- Write Port 224 RESET => rst_int_wr, 225 WR_CLK => wr_clk_i, 226 PRC_WR_EN => prc_we_i, 227 FULL => full_i, 228 WR_EN => wr_en_i, 229 WR_DATA => wr_data 230 ); 231 232 fg_dv_nv: fifo_short_2clk_dverif 233 GENERIC MAP ( 234 C_DOUT_WIDTH => 72, 235 C_DIN_WIDTH => 72, 236 C_USE_EMBEDDED_REG => 0, 237 TB_SEED => TB_SEED, 238 C_CH_TYPE => 0 239 ) 240 PORT MAP( 241 RESET => rst_int_rd, 242 RD_CLK => rd_clk_i, 243 PRC_RD_EN => prc_re_i, 244 RD_EN => rd_en_i, 245 EMPTY => empty_i, 246 DATA_OUT => dout_i, 247 DOUT_CHK => dout_chk_i 248 ); 249 250 fg_pc_nv: fifo_short_2clk_pctrl 251 GENERIC MAP ( 252 AXI_CHANNEL => "Native", 253 C_APPLICATION_TYPE => 0, 254 C_DOUT_WIDTH => 72, 255 C_DIN_WIDTH => 72, 256 C_WR_PNTR_WIDTH => 5, 257 C_RD_PNTR_WIDTH => 5, 258 C_CH_TYPE => 0, 259 FREEZEON_ERROR => FREEZEON_ERROR, 260 TB_SEED => TB_SEED, 261 TB_STOP_CNT => TB_STOP_CNT 262 ) 263 PORT MAP( 264 RESET_WR => rst_int_wr, 265 RESET_RD => rst_int_rd, 266 RESET_EN => reset_en, 267 WR_CLK => wr_clk_i, 268 RD_CLK => rd_clk_i, 269 PRC_WR_EN => prc_we_i, 270 PRC_RD_EN => prc_re_i, 271 FULL => full_i, 272 ALMOST_FULL => almost_full_i, 273 ALMOST_EMPTY => almost_empty_i, 274 DOUT_CHK => dout_chk_i, 275 EMPTY => empty_i, 276 DATA_IN => wr_data, 277 DATA_OUT => dout, 278 SIM_DONE => SIM_DONE, 279 STATUS => STATUS 280 ); 281 282 283 284 285 286 fifo_short_2clk_inst : fifo_short_2clk_exdes 287 PORT MAP ( 288 WR_CLK => wr_clk_i, 289 RD_CLK => rd_clk_i, 290 WR_DATA_COUNT => wr_data_count, 291 RD_DATA_COUNT => rd_data_count, 292 RST => rst, 293 WR_EN => wr_en, 294 RD_EN => rd_en, 295 DIN => din, 296 DOUT => dout, 297 FULL => full, 298 EMPTY => empty); 299 300END ARCHITECTURE; 301