1/////////////////////////////////// 2// 3// Copyright 2016-2017 Ettus Research LLC 4// Copyright 2017 Ettus Research, a National Instruments Company 5// 6// SPDX-License-Identifier: LGPL-3.0-or-later 7// 8// NOTE: A set of precompiler directives configure the features in an FPGA build 9// and are listed here. These should be set exclusively using the Makefile mechanism provided. 10// 11// SFP0_10GBE - Ethernet Port0 is configured for 10G (default is 1G) 12// SFP1_10GBE - Ethernet Port1 is configured for 10G (default is 1G) 13// DEBUG_UART - Adds 115kbaud UART to GPIO pins 10 & 11 for firmware debug 14// 15/////////////////////////////////// 16 17//Defines `LVFPGA_IFACE constants 18`include "../../lib/io_port2/LvFpga_Chinch_Interface.vh" 19 20module x300 21 22 ( 23 /////////////////////////////////// 24 // 25 // Clock sources for main FPGA clocks 26 // 27 /////////////////////////////////// 28 input FPGA_CLK_p, input FPGA_CLK_n, 29 input FPGA_125MHz_CLK, 30 31 /////////////////////////////////// 32 // 33 // High Speed SPF+ signals and clocking 34 // 35 /////////////////////////////////// 36 37`ifdef BUILD_1G 38 input ETH_CLK_p, input ETH_CLK_n, 39`endif 40 41`ifdef BUILD_10G 42 `define BUILD_10G_OR_AURORA 43`endif 44`ifdef BUILD_AURORA 45 `define BUILD_10G_OR_AURORA 46`endif 47`ifdef BUILD_10G_OR_AURORA 48 input XG_CLK_p, input XG_CLK_n, 49`endif 50 51 input SFP0_RX_p, input SFP0_RX_n, 52 output SFP0_TX_p, output SFP0_TX_n, 53 input SFP1_RX_p, input SFP1_RX_n, 54 output SFP1_TX_p, output SFP1_TX_n, 55 56 /////////////////////////////////// 57 // 58 // DRAM Interface 59 // 60 /////////////////////////////////// 61 inout [31:0] ddr3_dq, // Data pins. Input for Reads, Output for Writes. 62 inout [3:0] ddr3_dqs_n, // Data Strobes. Input for Reads, Output for Writes. 63 inout [3:0] ddr3_dqs_p, 64 // 65 output [14:0] ddr3_addr, // Address 66 output [2:0] ddr3_ba, // Bank Address 67 output ddr3_ras_n, // Row Address Strobe. 68 output ddr3_cas_n, // Column address select 69 output ddr3_we_n, // Write Enable 70 output ddr3_reset_n, // SDRAM reset pin. 71 output [0:0] ddr3_ck_p, // Differential clock 72 output [0:0] ddr3_ck_n, 73 output [0:0] ddr3_cke, // Clock Enable 74 output [0:0] ddr3_cs_n, // Chip Select 75 output [3:0] ddr3_dm, // Data Mask [3] = UDM.U26, [2] = LDM.U26, ... 76 output [0:0] ddr3_odt, // On-Die termination enable. 77 // 78 input sys_clk_i, // 100MHz clock source to generate DDR3 clocking. 79 /////////////////////////////////// 80 // 81 // IOPORT2 82 // 83 /////////////////////////////////// 84 85 //-- The IO_Port2 asynchronous handshaking pins 86 input aIoResetIn_n, 87 output aIoReadyOut, 88 input aIoReadyIn, 89 output aIoPort2Restart, 90 input aStc3Gpio7, 91 92 //-- The IO_Port2 high speed receiver pins 93 input IoRxClock, 94 input IoRxClock_n, 95 input [15:0] irIoRxData, 96 input [15:0] irIoRxData_n, 97 input irIoRxHeader, 98 input irIoRxHeader_n, 99 100 //-- The IO_Port2 high speed transmitter interface pins 101 output IoTxClock, 102 output IoTxClock_n, 103 output [15:0] itIoTxData, 104 output [15:0] itIoTxData_n, 105 output itIoTxHeader, 106 output itIoTxHeader_n, 107 108 output aIrq, 109 110 /////////////////////////////////// 111 // 112 // ADC and DAC interfaces 113 // 114 /////////////////////////////////// 115 116 input DB0_ADC_DCLK_P, input DB0_ADC_DCLK_N, 117 input DB0_ADC_DA0_P, input DB0_ADC_DA0_N, input DB0_ADC_DB0_P, input DB0_ADC_DB0_N, 118 input DB0_ADC_DA1_P, input DB0_ADC_DA1_N, input DB0_ADC_DB1_P, input DB0_ADC_DB1_N, 119 input DB0_ADC_DA2_P, input DB0_ADC_DA2_N, input DB0_ADC_DB2_P, input DB0_ADC_DB2_N, 120 input DB0_ADC_DA3_P, input DB0_ADC_DA3_N, input DB0_ADC_DB3_P, input DB0_ADC_DB3_N, 121 input DB0_ADC_DA4_P, input DB0_ADC_DA4_N, input DB0_ADC_DB4_P, input DB0_ADC_DB4_N, 122 input DB0_ADC_DA5_P, input DB0_ADC_DA5_N, input DB0_ADC_DB5_P, input DB0_ADC_DB5_N, 123 input DB0_ADC_DA6_P, input DB0_ADC_DA6_N, input DB0_ADC_DB6_P, input DB0_ADC_DB6_N, 124 125 input DB1_ADC_DCLK_P, input DB1_ADC_DCLK_N, 126 input DB1_ADC_DA0_P, input DB1_ADC_DA0_N, input DB1_ADC_DB0_P, input DB1_ADC_DB0_N, 127 input DB1_ADC_DA1_P, input DB1_ADC_DA1_N, input DB1_ADC_DB1_P, input DB1_ADC_DB1_N, 128 input DB1_ADC_DA2_P, input DB1_ADC_DA2_N, input DB1_ADC_DB2_P, input DB1_ADC_DB2_N, 129 input DB1_ADC_DA3_P, input DB1_ADC_DA3_N, input DB1_ADC_DB3_P, input DB1_ADC_DB3_N, 130 input DB1_ADC_DA4_P, input DB1_ADC_DA4_N, input DB1_ADC_DB4_P, input DB1_ADC_DB4_N, 131 input DB1_ADC_DA5_P, input DB1_ADC_DA5_N, input DB1_ADC_DB5_P, input DB1_ADC_DB5_N, 132 input DB1_ADC_DA6_P, input DB1_ADC_DA6_N, input DB1_ADC_DB6_P, input DB1_ADC_DB6_N, 133 134 output DB0_DAC_DCI_P, output DB0_DAC_DCI_N, 135 output DB0_DAC_FRAME_P, output DB0_DAC_FRAME_N, 136 output DB0_DAC_D0_P, output DB0_DAC_D0_N, output DB0_DAC_D1_P, output DB0_DAC_D1_N, 137 output DB0_DAC_D2_P, output DB0_DAC_D2_N, output DB0_DAC_D3_P, output DB0_DAC_D3_N, 138 output DB0_DAC_D4_P, output DB0_DAC_D4_N, output DB0_DAC_D5_P, output DB0_DAC_D5_N, 139 output DB0_DAC_D6_P, output DB0_DAC_D6_N, output DB0_DAC_D7_P, output DB0_DAC_D7_N, 140 output DB0_DAC_ENABLE, 141 142 output DB1_DAC_DCI_P, output DB1_DAC_DCI_N, 143 output DB1_DAC_FRAME_P, output DB1_DAC_FRAME_N, 144 output DB1_DAC_D0_P, output DB1_DAC_D0_N, output DB1_DAC_D1_P, output DB1_DAC_D1_N, 145 output DB1_DAC_D2_P, output DB1_DAC_D2_N, output DB1_DAC_D3_P, output DB1_DAC_D3_N, 146 output DB1_DAC_D4_P, output DB1_DAC_D4_N, output DB1_DAC_D5_P, output DB1_DAC_D5_N, 147 output DB1_DAC_D6_P, output DB1_DAC_D6_N, output DB1_DAC_D7_P, output DB1_DAC_D7_N, 148 output DB1_DAC_ENABLE, 149 150 output DB0_SCLK, output DB0_MOSI, 151 output DB0_ADC_SEN, output DB0_DAC_SEN, output DB0_TX_SEN, output DB0_RX_SEN, 152 output DB0_RX_LSADC_SEN, output DB0_RX_LSDAC_SEN, output DB0_TX_LSADC_SEN, output DB0_TX_LSDAC_SEN, 153 input DB0_RX_LSADC_MISO, input DB0_RX_MISO, input DB0_TX_LSADC_MISO, input DB0_TX_MISO, 154 155 output DB1_SCLK, output DB1_MOSI, 156 output DB1_ADC_SEN, output DB1_DAC_SEN, output DB1_TX_SEN, output DB1_RX_SEN, 157 output DB1_RX_LSADC_SEN, output DB1_RX_LSDAC_SEN, output DB1_TX_LSADC_SEN, output DB1_TX_LSDAC_SEN, 158 input DB1_RX_LSADC_MISO, input DB1_RX_MISO, input DB1_TX_LSADC_MISO, input DB1_TX_MISO, 159 output DB_DAC_SCLK, inout DB_DAC_MOSI, 160 161 output DB_ADC_RESET, output DB_DAC_RESET, 162 163 inout DB_SCL, inout DB_SDA, 164 165 /////////////////////////////////// 166 // 167 // GPIO/LEDS/Etc 168 // 169 /////////////////////////////////// 170 171 inout [11:0] FrontPanelGpio, 172 173 output LED_ACT1, output LED_ACT2, 174 output LED_LINK1, output LED_LINK2, 175 176 output LED_PPS, output LED_REFLOCK, output LED_GPSLOCK, 177 output LED_LINKSTAT, output LED_LINKACT, 178 output LED_RX1_RX, output LED_RX2_RX, 179 output LED_TXRX1_RX, output LED_TXRX1_TX, 180 output LED_TXRX2_RX, output LED_TXRX2_TX, 181 inout [15:0] DB0_TX_IO, 182 inout [15:0] DB0_RX_IO, 183 inout [15:0] DB1_TX_IO, 184 inout [15:0] DB1_RX_IO, 185 186 /////////////////////////////////// 187 // 188 // LMK CLock chip 189 // 190 /////////////////////////////////// 191 192 input [1:0] LMK_Status, 193 input LMK_Holdover, 194 input LMK_Lock, 195 input LMK_Sync, //not used, we do soft sync 196 output LMK_SEN, output LMK_MOSI, output LMK_SCLK, 197 198 /////////////////////////////////// 199 // 200 // GPSDO and Clock Refs 201 // 202 /////////////////////////////////// 203 204 output [1:0] ClockRefSelect, 205 output GPS_SER_IN, input GPS_SER_OUT, 206 input GPS_PPS_OUT, input EXT_PPS_IN, 207 output EXT_PPS_OUT, input GPS_LOCK_OK, 208 output GPSDO_PWR_ENA, output TCXO_ENA, 209 210 output CPRI_CLK_OUT_P, output CPRI_CLK_OUT_N, 211 212 input FPGA_REFCLK_10MHz_p, input FPGA_REFCLK_10MHz_n, 213 214 /////////////////////////////////// 215 // 216 // Supporting I/O for SPF+ interfaces 217 // (non high speed stuff) 218 // 219 /////////////////////////////////// 220 221 inout SFPP0_SCL, inout SFPP0_SDA, 222 input SFPP0_ModAbs, 223 input SFPP0_RxLOS, // High if module asserts Loss of Signal 224 input SFPP0_TxFault, // Current 10G PMA/PCS apparently ignores this signal. 225 output SFPP0_RS0, // These are actually open drain outputs 226 output SFPP0_RS1, // CAUTION! Take great care, this signal shorted to VeeR on SFP module. 227 output SFPP0_TxDisable, // These are actually open drain outputs 228 229 inout SFPP1_SCL, inout SFPP1_SDA, 230 input SFPP1_ModAbs, 231 input SFPP1_RxLOS, // High if module asserts Loss of Signal 232 input SFPP1_TxFault, // Current 10G PMA/PCS apparently ignores this signal. 233 output SFPP1_RS0, // These are actually open drain outputs 234 output SFPP1_RS1, // CAUTION! Take great care, this signal shorted to VeeR on SFP module. 235 output SFPP1_TxDisable, // These are actually open drain outputs 236 237 /////////////////////////////////// 238 // 239 // Misc. 240 // 241 /////////////////////////////////// 242 243 input FPGA_PUDC_B 244); 245 246 wire radio_clk, radio_clk_2x, dac_dci_clk; 247 wire global_rst, radio_rst, bus_rst, bus_rst_div2, ce_rst, adc_idlyctrl_rst; 248 wire [3:0] sw_rst; 249 wire [2:0] led0, led1; 250 251 //////////////////////////////////////////////////////////////////// 252 // 253 // Generate Bus Clock and PCIe Clocks. 254 // Source clock comes from U19 which is fixed freq 255 // and bufferd to be used by STC3 also (Page17 schematics). 256 // 257 //////////////////////////////////////////////////////////////////// 258 259 wire fpga_clk125, bus_clk, bus_clk_div2, ce_clk, ioport2_clk, rio40_clk, ioport2_idelay_ref_clk; 260 wire bus_clk_locked, rio40_clk_locked, rio40_clk_reset; 261 262 IBUFG fpga_125MHz_clk_buf ( 263 .I(FPGA_125MHz_CLK), 264 .O(fpga_clk125)); 265 266 //---------------------------------------------------------------------------- 267 // Output Output Phase Duty Cycle Pk-to-Pk Phase 268 // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 269 //---------------------------------------------------------------------------- 270 // CLK_OUT1___187.500______0.000______50.0_______85.263_____73.940 271 // CLK_OUT2___125.000______0.000______50.0_______91.831_____73.940 272 // CLK_OUT3____93.750______0.000______50.0_______96.813_____73.940 273 // CLK_OUT4___214.286______0.000______50.0_______83.210_____73.940 274 // 275 //---------------------------------------------------------------------------- 276 // Input Clock Freq (MHz) Input Jitter (UI) 277 //---------------------------------------------------------------------------- 278 // __primary_________125.000____________0.010 279 280 localparam BUS_CLK_RATE = 32'd187500000; 281 282 wire ioport2_clk_unbuf; 283 284 bus_clk_gen bus_clk_gen ( 285 .CLK_IN1(fpga_clk125), 286 .CLKFB_IN(ioport2_clk), 287 .CLK_OUT1(bus_clk), 288 .CLK_OUT2_UNBUF(/* unused */), //This exists to make the IP generate a 125MHz FB clock 289 .CLK_OUT3(bus_clk_div2), //bus_clk divided by 2. used by sc/zpu 290 .CLK_OUT4(ce_clk), 291 .CLKFB_OUT(ioport2_clk_unbuf), 292 .LOCKED(bus_clk_locked)); 293 294 BUFG ioport2_clk_bufg_i ( 295 .O(ioport2_clk), 296 .I(ioport2_clk_unbuf)); 297 298 //---------------------------------------------------------------------------- 299 // Output Output Phase Duty Cycle Pk-to-Pk Phase 300 // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 301 //---------------------------------------------------------------------------- 302 // CLK_OUT1____40.000______0.000______50.0______353.417_____96.948 303 // CLK_OUT2___200.000______0.000______50.0______192.299_____96.948 304 // 305 //---------------------------------------------------------------------------- 306 // Input Clock Freq (MHz) Input Jitter (UI) 307 //---------------------------------------------------------------------------- 308 // __primary_________125.000____________0.100 309 310 //rio40_clk and ioport2_idelay_ref_clk cannot share a PLL/MMCM reset with ioport2_clk 311 //so they have to come from a different clocking primitive instance 312 pcie_clk_gen pcie_clk_gen ( 313 .CLK_IN1(fpga_clk125), 314 .CLK_OUT1(rio40_clk), 315 .CLK_OUT2(ioport2_idelay_ref_clk), 316 .RESET(rio40_clk_reset), 317 .LOCKED(rio40_clk_locked)); 318 319 ///////////////////////////////////////////////////////////////////// 320 // 321 // 10MHz Reference clock 322 // 323 ////////////////////////////////////////////////////////////////////// 324 wire ref_clk; 325 IBUFDS IBUFDS_ref_clk ( 326 .O(ref_clk), 327 .I(FPGA_REFCLK_10MHz_p), 328 .IB(FPGA_REFCLK_10MHz_n) 329 ); 330 331 ////////////////////////////////////////////////////////////////////// 332 // CPRI Clock output -- this is the dirty recovered clock from the MGT 333 // This goes to the LMK04816 which locks to it and cleans it up 334 // We get the clean versions back as CPRI_CLK (for the CPRI MGT) 335 // and FPGA_CLK (for our main rfclk) 336 ////////////////////////////////////////////////////////////////////// 337 338 wire cpri_clk_out = 1'b0; // FIXME - connect to CPRI clock recovery when implemented 339 OBUFDS OBUFDS_cpri (.I(cpri_clk_out), .O(CPRI_CLK_OUT_P), .OB(CPRI_CLK_OUT_N)); 340 341 ///////////////////////////////////////////////////////////////////// 342 // 343 // power-on-reset logic. 344 // 345 ////////////////////////////////////////////////////////////////////// 346 por_gen por_gen(.clk(bus_clk), .reset_out(global_rst)); 347 348 ////////////////////////////////////////////////////////////////////// 349 wire [31:0] rx0, rx1; 350 wire [31:0] tx0, tx1; 351 wire sclk0, mosi0, miso0, sclk1, mosi1, miso1; 352 wire [7:0] sen0, sen1; 353 354 wire set_stb; 355 wire [7:0] set_addr; 356 wire [31:0] set_data; 357 358 //////////////////////////////////////////////////////////////////// 359 // 360 // Generate Radio Clocks from LMK04816 361 // Radio clock is normally 200MHz, radio_clk_2x 400MHz. 362 // In CPRI or LTE mode, radio clock is 184.32 MHz. 363 // radio_clk_2x is only to be used for clocking out TX samples to DAC 364 // 365 //---------------------------------------------------------------------------- 366 // Output Output Phase Duty Cycle Pk-to-Pk Phase 367 // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 368 //---------------------------------------------------------------------------- 369 // CLK_OUT1___200.000______0.000______50.0_______92.799_____82.655 370 // CLK_OUT2___400.000____-45.000______50.0_______81.254_____82.655 371 // CLK_OUT3___400.000_____60.000______50.0_______81.254_____82.655 372 // 373 //---------------------------------------------------------------------------- 374 // Input Clock Freq (MHz) Input Jitter (UI) 375 //---------------------------------------------------------------------------- 376 // __primary_________200.000____________0.010 377 // 378 //////////////////////////////////////////////////////////////////// 379 380 wire radio_clk_locked; 381 radio_clk_gen radio_clk_gen ( 382 .clk_in1_p(FPGA_CLK_p), .clk_in1_n(FPGA_CLK_n), 383 .CLK_OUT1(radio_clk), .CLK_OUT2(radio_clk_2x), .CLK_OUT3(dac_dci_clk), 384 .RESET(sw_rst[2]), .LOCKED(radio_clk_locked)); 385 386 //////////////////////////////////////////////////////////////////// 387 // 388 // IJB. Radio PLL doesn't seem to lock at power up. 389 // Probably needs AD9610 to be programmed to 120 or 200MHz to get 390 // an input clock thats in the ball park for PLL configuration. 391 // Currently use busclk PLL lock signal to control this reset, 392 // but we should find a better solution, perhaps a S/W controllable 393 // reset like the ETH PHY uses so that we can reset this clock domain 394 // after programming the AD9610. 395 // 396 //////////////////////////////////////////////////////////////////// 397 398 reset_sync radio_reset_sync ( 399 .clk(radio_clk), 400 .reset_in(global_rst || !bus_clk_locked || sw_rst[1]), 401 .reset_out(radio_rst) 402 ); 403 404 reset_sync int_reset_sync ( 405 .clk(bus_clk), 406 .reset_in(global_rst || !bus_clk_locked), 407 .reset_out(bus_rst) 408 ); 409 410 reset_sync int_div2_reset_sync ( 411 .clk(bus_clk_div2), 412 .reset_in(global_rst || !bus_clk_locked), 413 .reset_out(bus_rst_div2) 414 ); 415 416 reset_sync adc_idlyctrl_reset_sync ( 417 .clk(bus_clk), 418 .reset_in(global_rst || !bus_clk_locked || sw_rst[3]), 419 .reset_out(adc_idlyctrl_rst) 420 ); 421 422 reset_sync ce_reset_sync ( 423 .clk(ce_clk), 424 .reset_in(global_rst || !bus_clk_locked), 425 .reset_out(ce_rst) 426 ); 427 428 //////////////////////////////////////////////////////////////////// 429 // PPS 430 // Support for internal, external, and GPSDO PPS inputs 431 // Every attempt to minimize propagation between the external PPS 432 // input and outputs to support daisy-chaining the signal. 433 //////////////////////////////////////////////////////////////////// 434 435 wire int_pps; 436 wire [31:0] ref_freq; 437 wire ref_freq_changed; 438 wire ref_freq_sync_empty; 439 wire [71:0] ref_freq_sync_out; 440 reg new_ref_freq = 0; 441 reg [31:0] ref_freq_refclk = 10_000_000; // Default to 10 MHz reference 442 443 // Synchronize ref_freq to ref_clk 444 fifo_short_2clk ref_freq_sync 445 ( 446 .rst(bus_rst), 447 .wr_clk(bus_clk), 448 .rd_clk(ref_clk), 449 .din({40'd0,ref_freq}), 450 .wr_en(ref_freq_changed), 451 .rd_en(new_ref_freq), 452 .dout(ref_freq_sync_out), 453 .full( /* unused */ ), 454 .empty(ref_freq_sync_empty), 455 .rd_data_count( /* unused */ ), 456 .wr_data_count( /* unused */ ) 457 ); 458 459 // Capture the new reference frequency 460 always @(posedge ref_clk) begin 461 if (~ref_freq_sync_empty) begin 462 ref_freq_refclk <= ref_freq_sync_out[31:0]; 463 new_ref_freq <= 1'b1; 464 end else 465 new_ref_freq <= 1'b0; 466 end 467 468 // Generate an internal PPS signal with a 25% duty cycle 469 pulse_generator #(.WIDTH(32)) pps_gen 470 ( 471 .clk(ref_clk), 472 .reset(new_ref_freq), 473 .period(ref_freq_refclk), 474 //shift frequency by 2 bits (divide by 4) for a 25% duty cycle 475 .pulse_width({2'b00,ref_freq_refclk[31:2]}), 476 .pulse(int_pps) 477 ); 478 479 // PPS MUX - selects internal, external, or gpsdo PPS 480 reg pps; 481 wire [1:0] pps_select; 482 wire pps_out_enb; 483 always @(*) begin 484 case(pps_select) 485 2'b00 : pps = EXT_PPS_IN; 486 2'b01 : pps = 1'b0; 487 2'b10 : pps = int_pps; 488 2'b11 : pps = GPS_PPS_OUT; 489 default: pps = 1'b0; 490 endcase 491 end 492 493 // PPS out and LED 494 assign EXT_PPS_OUT = pps & pps_out_enb; 495 assign LED_PPS = ~pps; // active low LED driver 496 497 assign LED_GPSLOCK = ~GPS_LOCK_OK; 498 assign LED_REFLOCK = ~LMK_Lock; 499 assign {LED_RX1_RX,LED_TXRX1_TX,LED_TXRX1_RX} = ~led0; // active low LED driver 500 assign {LED_RX2_RX,LED_TXRX2_TX,LED_TXRX2_RX} = ~led1; // active low LED driver 501 // Allocate SPI chip selects to various slaves. 502 assign {DB1_DAC_SEN, DB1_ADC_SEN, DB1_RX_LSADC_SEN, DB1_RX_LSDAC_SEN, DB1_TX_LSADC_SEN, DB1_TX_LSDAC_SEN, DB1_RX_SEN, DB1_TX_SEN} = sen1; 503 assign {DB0_DAC_SEN, DB0_ADC_SEN, DB0_RX_LSADC_SEN, DB0_RX_LSDAC_SEN, DB0_TX_LSADC_SEN, DB0_TX_LSDAC_SEN, DB0_RX_SEN, DB0_TX_SEN} = sen0; 504 505 wire db_dac_mosi_int, db_dac_miso; 506 wire drive_dac_pin; 507 reg drop_dac_pin; 508 reg [5:0] bitcount; 509 reg sclk_d1; 510 511 // Register copy of outgoing DAC clock to do synchronous edge detect. 512 always @(posedge radio_clk) sclk_d1 <= DB_DAC_SCLK; 513 514 always @(posedge radio_clk) 515 // If neither DAC is selected keep counter reset 516 if(DB0_DAC_SEN & DB1_DAC_SEN) 517 begin 518 bitcount <= 6'd0; 519 drop_dac_pin <= 1'b0; 520 end 521 else if(~DB_DAC_SCLK & sclk_d1) 522 // Falling edge of SCLK detected. 523 begin 524 bitcount <= bitcount + 6'd1; 525 end 526 else if(bitcount == 0 & DB_DAC_SCLK & ~sclk_d1) 527 // On first rising edge store R/W bit to determine if we tristate after 8bits for a Read. 528 drop_dac_pin <= db_dac_mosi_int; 529 530 assign drive_dac_pin = (bitcount < 8) | ~drop_dac_pin; 531 532 // Both DAC's use a single SPI bus on PCB. Select appriate Radio to drive the SPi bus by looking at chip selects. 533 assign { DB_DAC_SCLK, db_dac_mosi_int } = ~DB0_DAC_SEN ? {sclk0, mosi0} : ~DB1_DAC_SEN ? {sclk1,mosi1} : 2'b0; 534 // Data to/from DAC's is bi-dir so tristate driver when reading. 535 assign DB_DAC_MOSI = drive_dac_pin ? db_dac_mosi_int : 1'bz; 536 // I/O Input buffer 537 assign db_dac_miso = DB_DAC_MOSI; 538 539 // If any SPI Slave is selected (except DAC) then drive SPI clk and MOSI out onto duaghterboard. 540 assign { DB0_SCLK, DB0_MOSI } = (~&sen0[6:0]) ? {sclk0,mosi0} : 2'b0; 541 assign { DB1_SCLK, DB1_MOSI } = (~&sen1[6:0]) ? {sclk1,mosi1} : 2'b0; 542 543 // Wired OR Mux together the possible sources of read data from SPI devices. 544 assign miso0 = (~DB0_RX_LSADC_SEN & DB0_RX_LSADC_MISO) | 545 (~DB0_RX_SEN & DB0_RX_MISO) | 546 (~DB0_TX_LSADC_SEN & DB0_TX_LSADC_MISO) | 547 (~DB0_TX_SEN & DB0_TX_MISO) | 548 (~DB0_DAC_SEN & db_dac_miso); 549 550 assign miso1 = (~DB1_RX_LSADC_SEN & DB1_RX_LSADC_MISO) | 551 (~DB1_RX_SEN & DB1_RX_MISO) | 552 (~DB1_TX_LSADC_SEN & DB1_TX_LSADC_MISO) | 553 (~DB1_TX_SEN & DB1_TX_MISO) | 554 (~DB1_DAC_SEN & db_dac_miso); 555 556 557 wire [31:0] radio0_misc_out, radio1_misc_out; 558 wire [31:0] radio0_misc_in, radio1_misc_in; 559 560 ///////////////////////////////////////////////////////////////////// 561 // 562 // ADC Interface for ADS62P48 563 // 564 ///////////////////////////////////////////////////////////////////// 565 wire [13:0] rx0_q_inv, rx1_q_inv, rx0_i, rx1_i; 566 // Analog diff pairs on I side of ADC are inverted for layout reasons, but data diff pairs are all swapped as well 567 // so I gets a double negative, and is unchanged. Q must be inverted. 568 569 capture_ddrlvds #( 570 .WIDTH(14), 571 .PATT_CHECKER("TRUE"), 572 .DATA_IDELAY_MODE("DYNAMIC"), .DATA_IDELAY_VAL(16), .DATA_IDELAY_FREF(200.0) 573 ) cap_db0 ( 574 .adc_clk_p(DB0_ADC_DCLK_P), .adc_clk_n(DB0_ADC_DCLK_N), 575 .adc_data_p( 576 {{DB0_ADC_DA6_P, DB0_ADC_DA5_P, DB0_ADC_DA4_P, DB0_ADC_DA3_P, DB0_ADC_DA2_P, DB0_ADC_DA1_P, DB0_ADC_DA0_P}, 577 {DB0_ADC_DB6_P, DB0_ADC_DB5_P, DB0_ADC_DB4_P, DB0_ADC_DB3_P, DB0_ADC_DB2_P, DB0_ADC_DB1_P, DB0_ADC_DB0_P}}), 578 .adc_data_n( 579 {{DB0_ADC_DA6_N, DB0_ADC_DA5_N, DB0_ADC_DA4_N, DB0_ADC_DA3_N, DB0_ADC_DA2_N, DB0_ADC_DA1_N, DB0_ADC_DA0_N}, 580 {DB0_ADC_DB6_N, DB0_ADC_DB5_N, DB0_ADC_DB4_N, DB0_ADC_DB3_N, DB0_ADC_DB2_N, DB0_ADC_DB1_N, DB0_ADC_DB0_N}}), 581 .radio_clk(radio_clk), 582 .data_delay_stb(radio0_misc_out[3]), .data_delay_val(radio0_misc_out[8:4]), 583 .adc_cap_clk(), 584 .data_out({rx0_i,rx0_q_inv}), 585 .checker_en(radio0_misc_out[9]), .checker_locked(radio0_misc_in[3:0]), .checker_failed(radio0_misc_in[7:4]) 586 ); 587 assign rx0[31:0] = { rx0_i, 2'b00, ~rx0_q_inv, 2'b00 }; 588 589 capture_ddrlvds #( 590 .WIDTH(14), 591 .PATT_CHECKER("TRUE"), 592 .DATA_IDELAY_MODE("DYNAMIC"), .DATA_IDELAY_VAL(16), .DATA_IDELAY_FREF(200.0) 593 ) cap_db1 ( 594 .adc_clk_p(DB1_ADC_DCLK_P), .adc_clk_n(DB1_ADC_DCLK_N), 595 .adc_data_p( 596 {{DB1_ADC_DA6_P, DB1_ADC_DA5_P, DB1_ADC_DA4_P, DB1_ADC_DA3_P, DB1_ADC_DA2_P, DB1_ADC_DA1_P, DB1_ADC_DA0_P}, 597 {DB1_ADC_DB6_P, DB1_ADC_DB5_P, DB1_ADC_DB4_P, DB1_ADC_DB3_P, DB1_ADC_DB2_P, DB1_ADC_DB1_P, DB1_ADC_DB0_P}}), 598 .adc_data_n( 599 {{DB1_ADC_DA6_N, DB1_ADC_DA5_N, DB1_ADC_DA4_N, DB1_ADC_DA3_N, DB1_ADC_DA2_N, DB1_ADC_DA1_N, DB1_ADC_DA0_N}, 600 {DB1_ADC_DB6_N, DB1_ADC_DB5_N, DB1_ADC_DB4_N, DB1_ADC_DB3_N, DB1_ADC_DB2_N, DB1_ADC_DB1_N, DB1_ADC_DB0_N}}), 601 .radio_clk(radio_clk), 602 .data_delay_stb(radio1_misc_out[3]), .data_delay_val(radio1_misc_out[8:4]), 603 .adc_cap_clk(), 604 .data_out({rx1_i,rx1_q_inv}), 605 .checker_en(radio1_misc_out[9]), .checker_locked(radio1_misc_in[3:0]), .checker_failed(radio1_misc_in[7:4]) 606 ); 607 assign rx1[31:0] = { rx1_i, 2'b00, ~rx1_q_inv, 2'b00 }; 608 609 // IDELAYCTRL to calibrate all IDELAYE2 instances in capture_ddrlvds for both sides 610 wire adc_idlyctrl_rdy; 611 IDELAYCTRL adc_cap_idelayctrl_i (.RDY(adc_idlyctrl_rdy), .REFCLK(radio_clk), .RST(adc_idlyctrl_rst)); 612 613 ///////////////////////////////////////////////////////////////////// 614 // 615 // DAC Interface for AD9146 616 // 617 ///////////////////////////////////////////////////////////////////// 618 gen_ddrlvds gen_db0 619 ( 620 .reset(radio_rst), 621 .tx_clk_2x_p(DB0_DAC_DCI_P), .tx_clk_2x_n(DB0_DAC_DCI_N), 622 .tx_frame_p(DB0_DAC_FRAME_P), .tx_frame_n(DB0_DAC_FRAME_N), 623 .tx_d_p({DB0_DAC_D7_P,DB0_DAC_D6_P,DB0_DAC_D5_P,DB0_DAC_D4_P,DB0_DAC_D3_P,DB0_DAC_D2_P,DB0_DAC_D1_P,DB0_DAC_D0_P}), 624 .tx_d_n({DB0_DAC_D7_N,DB0_DAC_D6_N,DB0_DAC_D5_N,DB0_DAC_D4_N,DB0_DAC_D3_N,DB0_DAC_D2_N,DB0_DAC_D1_N,DB0_DAC_D0_N}), 625 .tx_clk_2x(radio_clk_2x), .tx_clk_1x(radio_clk), .tx_dci_clk(dac_dci_clk), 626 .i(~tx0[31:16]), .q(~tx0[15:0]), // invert b/c Analog diff pairs are swapped for layout 627 .sync_dacs(radio0_misc_out[10]|radio1_misc_out[10]) 628 ); 629 630 631 gen_ddrlvds gen_db1 632 ( 633 .reset(radio_rst), 634 .tx_clk_2x_p(DB1_DAC_DCI_P), .tx_clk_2x_n(DB1_DAC_DCI_N), 635 .tx_frame_p(DB1_DAC_FRAME_P), .tx_frame_n(DB1_DAC_FRAME_N), 636 .tx_d_p({DB1_DAC_D7_P,DB1_DAC_D6_P,DB1_DAC_D5_P,DB1_DAC_D4_P,DB1_DAC_D3_P,DB1_DAC_D2_P,DB1_DAC_D1_P,DB1_DAC_D0_P}), 637 .tx_d_n({DB1_DAC_D7_N,DB1_DAC_D6_N,DB1_DAC_D5_N,DB1_DAC_D4_N,DB1_DAC_D3_N,DB1_DAC_D2_N,DB1_DAC_D1_N,DB1_DAC_D0_N}), 638 .tx_clk_2x(radio_clk_2x), .tx_clk_1x(radio_clk), .tx_dci_clk(dac_dci_clk), 639 .i(~tx1[31:16]), .q(~tx1[15:0]), // invert b/c Analog diff pairs are swapped for layout 640 .sync_dacs(radio0_misc_out[10]|radio1_misc_out[10]) 641 ); 642 643 644 wire [1:0] leds; 645 assign {LED_LINKSTAT, LED_LINKACT} = ~leds; 646 647 wire [31:0] debug; 648 649 ////////////////////////////////////////////////////////////////////// 650 // 651 // PCIe Stuff 652 // 653 ////////////////////////////////////////////////////////////////////// 654 655 localparam IOP2_MSG_WIDTH = 64; 656 localparam DMA_STREAM_WIDTH = `LVFPGA_IFACE_DMA_CHAN_WIDTH; 657 localparam DMA_COUNT_WIDTH = `LVFPGA_IFACE_DMA_SIZE_WIDTH; 658 localparam NUM_TX_STREAMS = `LVFPGA_IFACE_NUM_TX_DMA_CNT; 659 localparam NUM_RX_STREAMS = `LVFPGA_IFACE_NUM_RX_DMA_CNT; 660 localparam TX_STREAM_START_IDX = `LVFPGA_IFACE_TX_DMA_INDEX; 661 localparam RX_STREAM_START_IDX = `LVFPGA_IFACE_RX_DMA_INDEX; 662 localparam DMA_DEST_WIDTH = 3; 663 664 wire [DMA_STREAM_WIDTH-1:0] dmatx_tdata, dmarx_tdata, pcii_tdata, pcio_tdata; 665 wire [DMA_DEST_WIDTH-1:0] dmatx_tuser, dmarx_tuser, pcii_tuser, pcio_tuser; 666 wire dmatx_tvalid, dmarx_tvalid, pcii_tvalid, pcio_tvalid; 667 wire dmatx_tlast, dmarx_tlast, pcii_tlast, pcio_tlast; 668 wire dmatx_tready, dmarx_tready, pcii_tready, pcio_tready; 669 670 wire [IOP2_MSG_WIDTH-1:0] o_iop2_msg_tdata, i_iop2_msg_tdata; 671 wire o_iop2_msg_tvalid, o_iop2_msg_tlast, o_iop2_msg_tready; 672 wire i_iop2_msg_tvalid, i_iop2_msg_tlast, i_iop2_msg_tready; 673 674 wire pcie_usr_reg_wr, pcie_usr_reg_rd, pcie_usr_reg_rc, pcie_usr_reg_rdy; 675 wire [1:0] pcie_usr_reg_len; 676 wire [19:0] pcie_usr_reg_addr; 677 wire [31:0] pcie_usr_reg_data_in, pcie_usr_reg_data_out; 678 679 wire chinch_reg_wr, chinch_reg_rd, chinch_reg_rc, chinch_reg_rdy; 680 wire [1:0] chinch_reg_len; 681 wire [19:0] chinch_reg_addr; 682 wire [31:0] chinch_reg_data_out; 683 wire [63:0] chinch_reg_data_in; 684 685 wire [(NUM_TX_STREAMS*DMA_STREAM_WIDTH)-1:0] dmatx_tdata_iop2; 686 wire [NUM_TX_STREAMS-1:0] dmatx_tvalid_iop2, dmatx_tready_iop2; 687 688 wire [(NUM_RX_STREAMS*DMA_STREAM_WIDTH)-1:0] dmarx_tdata_iop2; 689 wire [NUM_RX_STREAMS-1:0] dmarx_tvalid_iop2, dmarx_tready_iop2; 690 691 //PCIe Express "Physical" DMA and Register logic 692 LvFpga_Chinch_Interface lvfpga_chinch_inst 693 ( 694 .aIoResetIn_n(aIoResetIn_n), 695 .bBusReset(), //Output 696 697 // Clocks 698 .BusClk(ioport2_clk), 699 .Rio40Clk(rio40_clk), 700 .IDelayRefClk(ioport2_idelay_ref_clk), 701 .aRioClkPllLocked(rio40_clk_locked), 702 .aRioClkPllReset(rio40_clk_reset), 703 704 // The IO_Port2 asynchronous handshaking pins 705 .aIoReadyOut(aIoReadyOut), 706 .aIoReadyIn(aIoReadyIn), 707 .aIoPort2Restart(aIoPort2Restart), 708 709 // The IO_Port2 high speed receiver pins 710 .IoRxClock(IoRxClock), 711 .IoRxClock_n(IoRxClock_n), 712 .irIoRxData(irIoRxData), 713 .irIoRxData_n(irIoRxData_n), 714 .irIoRxHeader(irIoRxHeader), 715 .irIoRxHeader_n(irIoRxHeader_n), 716 717 // The IO_Port2 high speed transmitter interface pins 718 .IoTxClock(IoTxClock), 719 .IoTxClock_n(IoTxClock_n), 720 .itIoTxData(itIoTxData), 721 .itIoTxData_n(itIoTxData_n), 722 .itIoTxHeader(itIoTxHeader), 723 .itIoTxHeader_n(itIoTxHeader_n), 724 725 // DMA TX Fifos 726 .bDmaTxData(dmatx_tdata_iop2), 727 .bDmaTxValid(dmatx_tvalid_iop2), 728 .bDmaTxReady(dmatx_tready_iop2), 729 .bDmaTxEnabled(), 730 .bDmaTxFifoFullCnt(), 731 732 // DMA RX Fifos 733 .bDmaRxData(dmarx_tdata_iop2), 734 .bDmaRxValid(dmarx_tvalid_iop2), 735 .bDmaRxReady(dmarx_tready_iop2), 736 .bDmaRxEnabled(), 737 .bDmaRxFifoFreeCnt(), 738 739 // User Register Port In 740 .bUserRegPortInWt(pcie_usr_reg_wr), 741 .bUserRegPortInRd(pcie_usr_reg_rd), 742 .bUserRegPortInAddr(pcie_usr_reg_addr), 743 .bUserRegPortInData(pcie_usr_reg_data_in), 744 .bUserRegPortInSize(pcie_usr_reg_len), 745 746 // User Register Port Out 747 .bUserRegPortOutData(pcie_usr_reg_data_out), 748 .bUserRegPortOutDataValid(pcie_usr_reg_rc), 749 .bUserRegPortOutReady(pcie_usr_reg_rdy), 750 751 // Chinch Register Port Out 752 .bChinchRegPortOutWt(chinch_reg_wr), 753 .bChinchRegPortOutRd(chinch_reg_rd), 754 .bChinchRegPortOutAddr({12'h0, chinch_reg_addr}), 755 .bChinchRegPortOutData({32'h0, chinch_reg_data_out}), 756 .bChinchRegPortOutSize(chinch_reg_len), 757 758 // User Register Port In 759 .bChinchRegPortInData(chinch_reg_data_in), 760 .bChinchRegPortInDataValid(chinch_reg_rc), 761 .bChinchRegPortInReady(chinch_reg_rdy), 762 763 // Level interrupt 764 .aIrq(aIrq) 765 ); 766 767 //PCIe Express adapter logic to link to the AXI crossbar and the WB bus 768 x300_pcie_int #( 769 .DMA_STREAM_WIDTH(DMA_STREAM_WIDTH), 770 .NUM_TX_STREAMS(NUM_TX_STREAMS), 771 .NUM_RX_STREAMS(NUM_RX_STREAMS), 772 .REGPORT_ADDR_WIDTH(20), 773 .REGPORT_DATA_WIDTH(32), 774 .IOP2_MSG_WIDTH(IOP2_MSG_WIDTH), 775 .BUS_CLK_RATE(BUS_CLK_RATE) 776 ) x300_pcie_int ( 777 .ioport2_clk(ioport2_clk), 778 .bus_clk(bus_clk), 779 .bus_rst(bus_rst), 780 781 //DMA TX FIFOs (IoPort2 Clock Domain) 782 .dmatx_tdata_iop2(dmatx_tdata_iop2), 783 .dmatx_tvalid_iop2(dmatx_tvalid_iop2), 784 .dmatx_tready_iop2(dmatx_tready_iop2), 785 786 //DMA TX FIFOs (IoPort2 Clock Domain) 787 .dmarx_tdata_iop2(dmarx_tdata_iop2), 788 .dmarx_tvalid_iop2(dmarx_tvalid_iop2), 789 .dmarx_tready_iop2(dmarx_tready_iop2), 790 791 //PCIe User Regport 792 .pcie_usr_reg_wr(pcie_usr_reg_wr), 793 .pcie_usr_reg_rd(pcie_usr_reg_rd), 794 .pcie_usr_reg_addr(pcie_usr_reg_addr), 795 .pcie_usr_reg_data_in(pcie_usr_reg_data_in), 796 .pcie_usr_reg_len(pcie_usr_reg_len), 797 .pcie_usr_reg_data_out(pcie_usr_reg_data_out), 798 .pcie_usr_reg_rc(pcie_usr_reg_rc), 799 .pcie_usr_reg_rdy(pcie_usr_reg_rdy), 800 801 //Chinch Regport 802 .chinch_reg_wr(chinch_reg_wr), 803 .chinch_reg_rd(chinch_reg_rd), 804 .chinch_reg_addr(chinch_reg_addr), 805 .chinch_reg_data_out(chinch_reg_data_out), 806 .chinch_reg_len(chinch_reg_len), 807 .chinch_reg_data_in(chinch_reg_data_in[31:0]), 808 .chinch_reg_rc(chinch_reg_rc), 809 .chinch_reg_rdy(chinch_reg_rdy), 810 811 //DMA TX FIFO (Bus Clock Domain). Note: tuser is used for muxing. 812 .dmatx_tdata(dmatx_tdata), 813 .dmatx_tuser(dmatx_tuser), 814 .dmatx_tlast(dmatx_tlast), 815 .dmatx_tvalid(dmatx_tvalid), 816 .dmatx_tready(dmatx_tready), 817 818 //DMA RX FIFO (Bus Clock Domain). Note: tuser is used for muxing. 819 .dmarx_tdata(dmarx_tdata), 820 .dmarx_tuser(dmarx_tuser), 821 .dmarx_tlast(dmarx_tlast), 822 .dmarx_tvalid(dmarx_tvalid), 823 .dmarx_tready(dmarx_tready), 824 825 //Message FIFO Out (Bus Clock Domain) 826 .rego_tdata(o_iop2_msg_tdata), 827 .rego_tvalid(o_iop2_msg_tvalid), 828 .rego_tlast(o_iop2_msg_tlast), 829 .rego_tready(o_iop2_msg_tready), 830 831 //Message FIFO In (Bus Clock Domain) 832 .regi_tdata(i_iop2_msg_tdata), 833 .regi_tvalid(i_iop2_msg_tvalid), 834 .regi_tlast(i_iop2_msg_tlast), 835 .regi_tready(i_iop2_msg_tready), 836 837 //Misc 838 .misc_status({15'h0, aStc3Gpio7}), 839 .debug() 840 ); 841 842 // The PCIe logic will tend to stay close to the physical IoPort2 pins 843 // so add an additional stage of pipelining to give the tool more routing 844 // slack. This is significantly help timing closure. 845 846 axi_fifo_short #(.WIDTH(DMA_STREAM_WIDTH+1+DMA_DEST_WIDTH)) pcii_pipeline_srl ( 847 .clk(bus_clk), .reset(bus_rst), .clear(1'b0), 848 .i_tdata({dmatx_tuser, dmatx_tlast, dmatx_tdata}), .i_tvalid(dmatx_tvalid), .i_tready(dmatx_tready), 849 .o_tdata({pcii_tuser, pcii_tlast, pcii_tdata}), .o_tvalid(pcii_tvalid), .o_tready(pcii_tready), 850 .space(), .occupied()); 851 852 axi_fifo_short #(.WIDTH(DMA_STREAM_WIDTH+1+DMA_DEST_WIDTH)) pcio_pipeline_srl ( 853 .clk(bus_clk), .reset(bus_rst), .clear(1'b0), 854 .i_tdata({pcio_tuser, pcio_tlast, pcio_tdata}), .i_tvalid(pcio_tvalid), .i_tready(pcio_tready), 855 .o_tdata({dmarx_tuser, dmarx_tlast, dmarx_tdata}), .o_tvalid(dmarx_tvalid), .o_tready(dmarx_tready), 856 .space(), .occupied()); 857 858 ////////////////////////////////////////////////////////////////////// 859 // 860 // Configure SFP+ clocking 861 // 862 ////////////////////////////////////////////////////////////////////// 863`ifdef BUILD_1G 864 wire gige_refclk, gige_refclk_bufg; 865 866 one_gige_phy_clk_gen gige_clk_gen_i ( 867 .refclk_p(ETH_CLK_p), 868 .refclk_n(ETH_CLK_n), 869 .refclk(gige_refclk), 870 .refclk_bufg(gige_refclk_bufg) 871 ); 872`endif 873`ifdef BUILD_10G 874 wire xgige_refclk; 875 wire xgige_clk156; 876 wire xgige_dclk; 877 878 ten_gige_phy_clk_gen xgige_clk_gen_i ( 879 .areset(global_rst | sw_rst[0]), 880 .refclk_p(XG_CLK_p), 881 .refclk_n(XG_CLK_n), 882 .refclk(xgige_refclk), 883 .clk156(xgige_clk156), 884 .dclk(xgige_dclk) 885 ); 886 `ifdef BUILD_AURORA 887 wire aurora_refclk = xgige_refclk; 888 wire aurora_refclk_bufg = xgige_clk156; 889 wire aurora_init_clk = xgige_dclk; 890 `endif 891`else 892 `ifdef BUILD_AURORA 893 wire aurora_refclk; 894 wire aurora_refclk_bufg; 895 wire aurora_init_clk; 896 897 aurora_phy_clk_gen aurora_clk_gen_i ( 898 .areset(global_rst | sw_rst[0]), 899 .refclk_p(XG_CLK_p), 900 .refclk_n(XG_CLK_n), 901 .refclk(aurora_refclk), 902 .clk156(aurora_refclk_bufg), 903 .init_clk(aurora_init_clk) 904 ); 905 `endif 906`endif 907 908 wire sfp0_gt_refclk, sfp1_gt_refclk; 909 wire sfp0_gb_refclk, sfp1_gb_refclk; 910 wire sfp0_misc_clk, sfp1_misc_clk; 911 912`ifdef SFP0_10GBE 913 assign sfp0_gt_refclk = xgige_refclk; 914 assign sfp0_gb_refclk = xgige_clk156; 915 assign sfp0_misc_clk = xgige_dclk; 916`endif 917`ifdef SFP0_1GBE 918 assign sfp0_gt_refclk = gige_refclk; 919 assign sfp0_gb_refclk = gige_refclk_bufg; 920 assign sfp0_misc_clk = gige_refclk_bufg; 921`endif 922`ifdef SFP0_AURORA 923 assign sfp0_gt_refclk = aurora_refclk; 924 assign sfp0_gb_refclk = aurora_refclk_bufg; 925 assign sfp0_misc_clk = aurora_init_clk; 926`endif 927 928`ifdef SFP1_10GBE 929 assign sfp1_gt_refclk = xgige_refclk; 930 assign sfp1_gb_refclk = xgige_clk156; 931 assign sfp1_misc_clk = xgige_dclk; 932`endif 933`ifdef SFP1_1GBE 934 assign sfp1_gt_refclk = gige_refclk; 935 assign sfp1_gb_refclk = gige_refclk_bufg; 936 assign sfp1_misc_clk = gige_refclk_bufg; 937`endif 938`ifdef SFP1_AURORA 939 assign sfp1_gt_refclk = aurora_refclk; 940 assign sfp1_gb_refclk = aurora_refclk_bufg; 941 assign sfp1_misc_clk = aurora_init_clk; 942`endif 943 944 ////////////////////////////////////////////////////////////////////// 945 // 946 // SFP+ PORT0 947 // 948 ////////////////////////////////////////////////////////////////////// 949 950 wire [63:0] sfp0_rx_tdata, sfp0_tx_tdata; 951 wire [3:0] sfp0_rx_tuser, sfp0_tx_tuser; 952 wire sfp0_rx_tlast, sfp0_tx_tlast, sfp0_rx_tvalid, sfp0_tx_tvalid, sfp0_rx_tready, sfp0_tx_tready; 953 wire [15:0] sfp0_phy_status; 954 955 wire [31:0] sfp0_wb_dat_i; 956 wire [31:0] sfp0_wb_dat_o; 957 wire [15:0] sfp0_wb_adr; 958 wire sfp0_wb_ack, sfp0_wb_stb, sfp0_wb_cyc, sfp0_wb_we, sfp0_wb_int; 959 960 wire sfp0_link_up, sfp0_activity; 961 962 x300_sfpp_io_core #( 963`ifdef SFP0_10GBE 964 .PROTOCOL("10GbE"), 965`endif 966`ifdef SFP0_1GBE 967 .PROTOCOL("1GbE"), 968`endif 969`ifdef SFP0_AURORA 970 .PROTOCOL("Aurora"), 971`endif 972 .PORTNUM(8'd0) 973 ) sfpp_io_i0 ( 974 .areset(global_rst | sw_rst[0]), 975 .gt_refclk(sfp0_gt_refclk), 976 .gb_refclk(sfp0_gb_refclk), 977 .misc_clk(sfp0_misc_clk), 978 979 .bus_rst(bus_rst), 980 .bus_clk(bus_clk), 981 .bus_rst_div2(bus_rst_div2), 982 .bus_clk_div2(bus_clk_div2), 983 984 .txp(SFP0_TX_p), 985 .txn(SFP0_TX_n), 986 .rxp(SFP0_RX_p), 987 .rxn(SFP0_RX_n), 988 989 .sfpp_rxlos(SFPP0_RxLOS), 990 .sfpp_tx_fault(SFPP0_TxFault), 991 .sfpp_tx_disable(SFPP0_TxDisable), 992 993 .s_axis_tdata(sfp0_tx_tdata), 994 .s_axis_tuser(sfp0_tx_tuser), 995 .s_axis_tlast(sfp0_tx_tlast), 996 .s_axis_tvalid(sfp0_tx_tvalid), 997 .s_axis_tready(sfp0_tx_tready), 998 999 .m_axis_tdata(sfp0_rx_tdata), 1000 .m_axis_tuser(sfp0_rx_tuser), 1001 .m_axis_tlast(sfp0_rx_tlast), 1002 .m_axis_tvalid(sfp0_rx_tvalid), 1003 .m_axis_tready(sfp0_rx_tready), 1004 1005 .wb_adr_i(sfp0_wb_adr), 1006 .wb_cyc_i(sfp0_wb_cyc), 1007 .wb_dat_i(sfp0_wb_dat_o), 1008 .wb_stb_i(sfp0_wb_stb), 1009 .wb_we_i(sfp0_wb_we), 1010 .wb_ack_o(sfp0_wb_ack), 1011 .wb_dat_o(sfp0_wb_dat_i), 1012 .wb_int_o(sfp0_wb_int), 1013 1014 .phy_status(sfp0_phy_status), 1015 .link_up(sfp0_link_up), 1016 .activity(sfp0_activity) 1017 ); 1018 1019 // LEDs are driven with negative logic. 1020 assign LED_LINK2 = ~sfp0_link_up; 1021 assign LED_ACT2 = ~sfp0_activity; 1022 1023 1024 ////////////////////////////////////////////////////////////////////// 1025 // 1026 // SFP+ PORT1 1027 // 1028 ////////////////////////////////////////////////////////////////////// 1029 1030 wire [63:0] sfp1_rx_tdata, sfp1_tx_tdata; 1031 wire [3:0] sfp1_rx_tuser, sfp1_tx_tuser; 1032 wire sfp1_rx_tlast, sfp1_tx_tlast, sfp1_rx_tvalid, sfp1_tx_tvalid, sfp1_rx_tready, sfp1_tx_tready; 1033 wire [15:0] sfp1_phy_status; 1034 1035 wire [31:0] sfp1_wb_dat_i; 1036 wire [31:0] sfp1_wb_dat_o; 1037 wire [15:0] sfp1_wb_adr; 1038 wire sfp1_wb_ack, sfp1_wb_stb, sfp1_wb_cyc, sfp1_wb_we, sfp1_wb_int; 1039 1040 wire sfp1_link_up, sfp1_activity; 1041 1042 x300_sfpp_io_core #( 1043`ifdef SFP1_10GBE 1044 .PROTOCOL("10GbE"), 1045`endif 1046`ifdef SFP1_1GBE 1047 .PROTOCOL("1GbE"), 1048`endif 1049`ifdef SFP1_AURORA 1050 .PROTOCOL("Aurora"), 1051`endif 1052 .PORTNUM(8'd1) 1053 ) sfpp_io_i1 ( 1054 .areset(global_rst | sw_rst[0]), 1055 .gt_refclk(sfp1_gt_refclk), 1056 .gb_refclk(sfp1_gb_refclk), 1057 .misc_clk(sfp1_misc_clk), 1058 1059 .bus_rst(bus_rst), 1060 .bus_clk(bus_clk), 1061 .bus_rst_div2(bus_rst_div2), 1062 .bus_clk_div2(bus_clk_div2), 1063 1064 .txp(SFP1_TX_p), 1065 .txn(SFP1_TX_n), 1066 .rxp(SFP1_RX_p), 1067 .rxn(SFP1_RX_n), 1068 1069 .sfpp_rxlos(SFPP1_RxLOS), 1070 .sfpp_tx_fault(SFPP1_TxFault), 1071 .sfpp_tx_disable(SFPP1_TxDisable), 1072 1073 .s_axis_tdata(sfp1_tx_tdata), 1074 .s_axis_tuser(sfp1_tx_tuser), 1075 .s_axis_tlast(sfp1_tx_tlast), 1076 .s_axis_tvalid(sfp1_tx_tvalid), 1077 .s_axis_tready(sfp1_tx_tready), 1078 1079 .m_axis_tdata(sfp1_rx_tdata), 1080 .m_axis_tuser(sfp1_rx_tuser), 1081 .m_axis_tlast(sfp1_rx_tlast), 1082 .m_axis_tvalid(sfp1_rx_tvalid), 1083 .m_axis_tready(sfp1_rx_tready), 1084 1085 .wb_adr_i(sfp1_wb_adr), 1086 .wb_cyc_i(sfp1_wb_cyc), 1087 .wb_dat_i(sfp1_wb_dat_o), 1088 .wb_stb_i(sfp1_wb_stb), 1089 .wb_we_i(sfp1_wb_we), 1090 .wb_ack_o(sfp1_wb_ack), 1091 .wb_dat_o(sfp1_wb_dat_i), 1092 .wb_int_o(sfp1_wb_int), 1093 1094 .phy_status(sfp1_phy_status), 1095 .link_up(sfp1_link_up), 1096 .activity(sfp1_activity) 1097 ); 1098 1099 // LEDs are driven with negative logic. 1100 assign LED_LINK1 = ~sfp1_link_up; 1101 assign LED_ACT1 = ~sfp1_activity; 1102 1103 /////////////////////////////////////////////////////////////////////////////////// 1104 // 1105 // Synchronize misc asynchronous signals 1106 // 1107 /////////////////////////////////////////////////////////////////////////////////// 1108 wire LMK_Holdover_sync, LMK_Lock_sync, LMK_Sync_sync; 1109 wire LMK_Status0_sync, LMK_Status1_sync; 1110 wire radio_clk_locked_sync; 1111 wire adc_idlyctrl_rdy_sync; 1112 1113 //Sync all LMK_* signals to bus_clk 1114 synchronizer #(.INITIAL_VAL(1'b0)) LMK_Holdover_sync_inst ( 1115 .clk(bus_clk), .rst(1'b0 /* no reset */), .in(LMK_Holdover), .out(LMK_Holdover_sync)); 1116 synchronizer #(.INITIAL_VAL(1'b0)) LMK_Lock_sync_inst ( 1117 .clk(bus_clk), .rst(1'b0 /* no reset */), .in(LMK_Lock), .out(LMK_Lock_sync)); 1118 synchronizer #(.INITIAL_VAL(1'b0)) LMK_Sync_sync_inst ( 1119 .clk(bus_clk), .rst(1'b0 /* no reset */), .in(LMK_Sync), .out(LMK_Sync_sync)); 1120 //The status bits (although in a bus) are really independent 1121 synchronizer #(.INITIAL_VAL(1'b0)) LMK_Status0_sync_inst ( 1122 .clk(bus_clk), .rst(1'b0 /* no reset */), .in(LMK_Status[0]), .out(LMK_Status0_sync)); 1123 synchronizer #(.INITIAL_VAL(1'b0)) LMK_Status1_sync_inst ( 1124 .clk(bus_clk), .rst(1'b0 /* no reset */), .in(LMK_Status[1]), .out(LMK_Status1_sync)); 1125 1126 synchronizer #(.INITIAL_VAL(1'b0)) radio_clk_locked_sync_inst ( 1127 .clk(bus_clk), .rst(1'b0 /* no reset */), .in(radio_clk_locked), .out(radio_clk_locked_sync)); 1128 synchronizer #(.INITIAL_VAL(1'b0)) adc_idlyctrl_rdy_sync_inst ( 1129 .clk(bus_clk), .rst(1'b0 /* no reset */), .in(adc_idlyctrl_rdy), .out(adc_idlyctrl_rdy_sync)); 1130 1131 /////////////////////////////////////////////////////////////////////////////////// 1132 // 1133 // Xilinx DDR3 Controller and PHY. 1134 // 1135 /////////////////////////////////////////////////////////////////////////////////// 1136 1137 1138 wire ddr3_axi_clk; // 1/4 DDR external clock rate (150MHz) 1139 wire ddr3_axi_clk_x2; // 1/2 DDR external clock rate (300MHz) 1140 wire ddr3_axi_rst; // Synchronized to ddr_sys_clk 1141 wire ddr3_running; // DRAM calibration complete. 1142 wire [11:0] device_temp; 1143 1144 // Slave Interface Write Address Ports 1145 wire s_axi_awid; 1146 wire [31:0] s_axi_awaddr; 1147 wire [7:0] s_axi_awlen; 1148 wire [2:0] s_axi_awsize; 1149 wire [1:0] s_axi_awburst; 1150 wire [0:0] s_axi_awlock; 1151 wire [3:0] s_axi_awcache; 1152 wire [2:0] s_axi_awprot; 1153 wire [3:0] s_axi_awqos; 1154 wire s_axi_awvalid; 1155 wire s_axi_awready; 1156 // Slave Interface Write Data Ports 1157 wire [255:0] s_axi_wdata; 1158 wire [31:0] s_axi_wstrb; 1159 wire s_axi_wlast; 1160 wire s_axi_wvalid; 1161 wire s_axi_wready; 1162 // Slave Interface Write Response Ports 1163 wire s_axi_bready; 1164 wire s_axi_bid; 1165 wire [1:0] s_axi_bresp; 1166 wire s_axi_bvalid; 1167 // Slave Interface Read Address Ports 1168 wire s_axi_arid; 1169 wire [31:0] s_axi_araddr; 1170 wire [7:0] s_axi_arlen; 1171 wire [2:0] s_axi_arsize; 1172 wire [1:0] s_axi_arburst; 1173 wire [0:0] s_axi_arlock; 1174 wire [3:0] s_axi_arcache; 1175 wire [2:0] s_axi_arprot; 1176 wire [3:0] s_axi_arqos; 1177 wire s_axi_arvalid; 1178 wire s_axi_arready; 1179 // Slave Interface Read Data Ports 1180 wire s_axi_rready; 1181 wire s_axi_rid; 1182 wire [255:0] s_axi_rdata; 1183 wire [1:0] s_axi_rresp; 1184 wire s_axi_rlast; 1185 wire s_axi_rvalid; 1186 1187 wire ddr3_idelay_refclk; 1188 reg ddr3_axi_rst_reg_n; 1189 1190 // Copied this reset circuit from example design. 1191 always @(posedge ddr3_axi_clk) 1192 ddr3_axi_rst_reg_n <= ~ddr3_axi_rst; 1193 1194 // Instantiate the DDR3 MIG core 1195 ddr3_32bit u_ddr3_32bit ( 1196 // Memory interface ports 1197 .ddr3_addr (ddr3_addr), 1198 .ddr3_ba (ddr3_ba), 1199 .ddr3_cas_n (ddr3_cas_n), 1200 .ddr3_ck_n (ddr3_ck_n), 1201 .ddr3_ck_p (ddr3_ck_p), 1202 .ddr3_cke (ddr3_cke), 1203 .ddr3_ras_n (ddr3_ras_n), 1204 .ddr3_reset_n (ddr3_reset_n), 1205 .ddr3_we_n (ddr3_we_n), 1206 .ddr3_dq (ddr3_dq), 1207 .ddr3_dqs_n (ddr3_dqs_n), 1208 .ddr3_dqs_p (ddr3_dqs_p), 1209 .ddr3_cs_n (ddr3_cs_n), 1210 .ddr3_dm (ddr3_dm), 1211 .ddr3_odt (ddr3_odt), 1212 .init_calib_complete (ddr3_running), 1213 .device_temp_i (device_temp), 1214 // Application interface ports 1215 .ui_clk (ddr3_axi_clk), // 150MHz clock out 1216 .ui_addn_clk_0 (ddr3_axi_clk_x2), // 300MHz clock out 1217 .ui_addn_clk_1 (ddr3_idelay_refclk), 1218 .ui_addn_clk_2 (), 1219 .ui_addn_clk_3 (), 1220 .ui_addn_clk_4 (), 1221 .clk_ref_i (ddr3_idelay_refclk), 1222 .ui_clk_sync_rst (ddr3_axi_rst), // Active high Reset signal synchronised to 150MHz 1223 .aresetn (ddr3_axi_rst_reg_n), 1224 .app_sr_req (1'b0), 1225 .app_sr_active (), 1226 .app_ref_req (1'b0), 1227 .app_ref_ack (), 1228 .app_zq_req (1'b0), 1229 .app_zq_ack (), 1230 1231 // Slave Interface Write Address Ports 1232 .s_axi_awid (s_axi_awid), 1233 .s_axi_awaddr (s_axi_awaddr), 1234 .s_axi_awlen (s_axi_awlen), 1235 .s_axi_awsize (s_axi_awsize), 1236 .s_axi_awburst (s_axi_awburst), 1237 .s_axi_awlock (s_axi_awlock), 1238 .s_axi_awcache (s_axi_awcache), 1239 .s_axi_awprot (s_axi_awprot), 1240 .s_axi_awqos (s_axi_awqos), 1241 .s_axi_awvalid (s_axi_awvalid), 1242 .s_axi_awready (s_axi_awready), 1243 // Slave Interface Write Data Ports 1244 .s_axi_wdata (s_axi_wdata), 1245 .s_axi_wstrb (s_axi_wstrb), 1246 .s_axi_wlast (s_axi_wlast), 1247 .s_axi_wvalid (s_axi_wvalid), 1248 .s_axi_wready (s_axi_wready), 1249 // Slave Interface Write Response Ports 1250 .s_axi_bid (s_axi_bid), 1251 .s_axi_bresp (s_axi_bresp), 1252 .s_axi_bvalid (s_axi_bvalid), 1253 .s_axi_bready (s_axi_bready), 1254 // Slave Interface Read Address Ports 1255 .s_axi_arid (s_axi_arid), 1256 .s_axi_araddr (s_axi_araddr), 1257 .s_axi_arlen (s_axi_arlen), 1258 .s_axi_arsize (s_axi_arsize), 1259 .s_axi_arburst (s_axi_arburst), 1260 .s_axi_arlock (s_axi_arlock), 1261 .s_axi_arcache (s_axi_arcache), 1262 .s_axi_arprot (s_axi_arprot), 1263 .s_axi_arqos (s_axi_arqos), 1264 .s_axi_arvalid (s_axi_arvalid), 1265 .s_axi_arready (s_axi_arready), 1266 // Slave Interface Read Data Ports 1267 .s_axi_rid (s_axi_rid), 1268 .s_axi_rdata (s_axi_rdata), 1269 .s_axi_rresp (s_axi_rresp), 1270 .s_axi_rlast (s_axi_rlast), 1271 .s_axi_rvalid (s_axi_rvalid), 1272 .s_axi_rready (s_axi_rready), 1273 // System Clock Ports 1274 .sys_clk_i (sys_clk_i), // From external 100MHz source. 1275 .sys_rst (global_rst) 1276 ); 1277 1278 // Temperature monitor module 1279 mig_7series_v4_2_tempmon #( 1280 .TEMP_MON_CONTROL("INTERNAL"), .XADC_CLK_PERIOD(8000 /* 125MHz clock period in ps */) 1281 ) tempmon_i ( 1282 .clk(bus_clk), .xadc_clk(ioport2_clk), .rst(bus_rst), 1283 .device_temp_i(12'd0 /* ignored */), .device_temp(device_temp) 1284 ); 1285 1286 ///////////////////////////////////////////////////////////////////// 1287 // 1288 // Daughterboard GPIO and Debug UART 1289 // 1290 ////////////////////////////////////////////////////////////////////// 1291 1292 wire [31:0] db0_gpio_in, db0_gpio_out, db0_gpio_ddr; 1293 wire [31:0] db1_gpio_in, db1_gpio_out, db1_gpio_ddr; 1294 wire [31:0] fp_gpio_in, fp_gpio_out, fp_gpio_ddr; 1295 wire debug_txd, debug_rxd; 1296 1297 gpio_atr_io #(.WIDTH(32)) gpio_atr_db0_inst ( 1298 .clk(radio_clk), .gpio_pins({DB0_TX_IO,DB0_RX_IO}), 1299 .gpio_ddr(db0_gpio_ddr), .gpio_out(db0_gpio_out), .gpio_in(db0_gpio_in) 1300 ); 1301 1302 gpio_atr_io #(.WIDTH(32)) gpio_atr_db1_inst ( 1303 .clk(radio_clk), .gpio_pins({DB1_TX_IO,DB1_RX_IO}), 1304 .gpio_ddr(db1_gpio_ddr), .gpio_out(db1_gpio_out), .gpio_in(db1_gpio_in) 1305 ); 1306 1307`ifdef DEBUG_UART 1308 gpio_atr_io #(.WIDTH(10)) fp_gpio_atr_inst ( 1309 .clk(radio_clk), .gpio_pins(FrontPanelGpio[9:0]), 1310 .gpio_ddr(fp_gpio_ddr[9:0]), .gpio_out(fp_gpio_out[9:0]), .gpio_in(fp_gpio_in[9:0]) 1311 ); 1312 assign FrontPanelGpio[11] = debug_txd; 1313 assign debug_rxd = FrontPanelGpio[10]; 1314`else 1315 gpio_atr_io #(.WIDTH(12)) fp_gpio_atr_inst ( 1316 .clk(radio_clk), .gpio_pins(FrontPanelGpio[11:0]), 1317 .gpio_ddr(fp_gpio_ddr[11:0]), .gpio_out(fp_gpio_out[11:0]), .gpio_in(fp_gpio_in[11:0]) 1318 ); 1319 assign debug_rxd = 1'b0; 1320`endif 1321 assign fp_gpio_in[31:12] = 20'h0; 1322 1323 /////////////////////////////////////////////////////////////////////////////////// 1324 // 1325 // X300 Core 1326 // 1327 /////////////////////////////////////////////////////////////////////////////////// 1328 1329 x300_core #( .BUS_CLK_RATE(BUS_CLK_RATE) ) x300_core ( 1330 .radio_clk(radio_clk), .radio_rst(radio_rst), 1331 .bus_clk(bus_clk), .bus_rst(bus_rst), .sw_rst(sw_rst), 1332 .bus_clk_div2(bus_clk_div2), 1333 .ce_clk(ce_clk), 1334 .ce_rst(ce_rst), 1335 // Radio0 signals 1336 .rx0(rx0), .tx0(tx0), 1337 .db0_gpio_in(db0_gpio_in), .db0_gpio_out(db0_gpio_out), .db0_gpio_ddr(db0_gpio_ddr), 1338 .fp_gpio_in(fp_gpio_in), .fp_gpio_out(fp_gpio_out), .fp_gpio_ddr(fp_gpio_ddr), 1339 .sen0(sen0), .sclk0(sclk0), .mosi0(mosi0), .miso0(miso0), 1340 .radio_led0(led0), .radio0_misc_out(radio0_misc_out), .radio0_misc_in(radio0_misc_in), 1341 // Radio1 signals 1342 .rx1(rx1), .tx1(tx1), 1343 .db1_gpio_in(db1_gpio_in), .db1_gpio_out(db1_gpio_out), .db1_gpio_ddr(db1_gpio_ddr), 1344 .sen1(sen1), .sclk1(sclk1), .mosi1(mosi1), .miso1(miso1), 1345 .radio_led1(led1), .radio1_misc_out(radio1_misc_out), .radio1_misc_in(radio1_misc_in), 1346 // I2C bus 1347 .db_scl(DB_SCL), .db_sda(DB_SDA), 1348 // External clock gen 1349 .ext_ref_clk(ref_clk), 1350 .clock_ref_sel(ClockRefSelect), 1351 .clock_misc_opt({GPSDO_PWR_ENA, TCXO_ENA}), 1352 .LMK_Status({LMK_Status1_sync, LMK_Status0_sync}), .LMK_Holdover(LMK_Holdover_sync), .LMK_Lock(LMK_Lock_sync), .LMK_Sync(LMK_Sync_sync), 1353 .LMK_SEN(LMK_SEN), .LMK_SCLK(LMK_SCLK), .LMK_MOSI(LMK_MOSI), 1354 .misc_clock_status({1'b0, adc_idlyctrl_rdy_sync, radio_clk_locked_sync}), 1355 // SFP+ 0 flags 1356 .SFPP0_SCL(SFPP0_SCL), .SFPP0_SDA(SFPP0_SDA), .SFPP0_ModAbs(SFPP0_ModAbs), .SFPP0_TxFault(SFPP0_TxFault), 1357 .SFPP0_RxLOS(SFPP0_RxLOS), .SFPP0_RS1(SFPP0_RS1), .SFPP0_RS0(SFPP0_RS0), 1358 // SFP+ 1 flags 1359 .SFPP1_SCL(SFPP1_SCL), .SFPP1_SDA(SFPP1_SDA), .SFPP1_ModAbs(SFPP1_ModAbs), .SFPP1_TxFault(SFPP1_TxFault), 1360 .SFPP1_RxLOS(SFPP1_RxLOS), .SFPP1_RS1(SFPP1_RS1), .SFPP1_RS0(SFPP1_RS0), 1361 // SFP+ 0 data stream 1362 .sfp0_tx_tdata(sfp0_tx_tdata), .sfp0_tx_tuser(sfp0_tx_tuser), .sfp0_tx_tlast(sfp0_tx_tlast), 1363 .sfp0_tx_tvalid(sfp0_tx_tvalid), .sfp0_tx_tready(sfp0_tx_tready), 1364 .sfp0_rx_tdata(sfp0_rx_tdata), .sfp0_rx_tuser(sfp0_rx_tuser), .sfp0_rx_tlast(sfp0_rx_tlast), 1365 .sfp0_rx_tvalid(sfp0_rx_tvalid), .sfp0_rx_tready(sfp0_rx_tready), 1366 .sfp0_phy_status(sfp0_phy_status), 1367 // SFP+ 1 data stream 1368 .sfp1_tx_tdata(sfp1_tx_tdata), .sfp1_tx_tuser(sfp1_tx_tuser), .sfp1_tx_tlast(sfp1_tx_tlast), 1369 .sfp1_tx_tvalid(sfp1_tx_tvalid), .sfp1_tx_tready(sfp1_tx_tready), 1370 .sfp1_rx_tdata(sfp1_rx_tdata), .sfp1_rx_tuser(sfp1_rx_tuser), .sfp1_rx_tlast(sfp1_rx_tlast), 1371 .sfp1_rx_tvalid(sfp1_rx_tvalid), .sfp1_rx_tready(sfp1_rx_tready), 1372 .sfp1_phy_status(sfp1_phy_status), 1373 // Wishbone Slave Interface(s) 1374 .sfp0_wb_dat_i(sfp0_wb_dat_i), .sfp0_wb_dat_o(sfp0_wb_dat_o), .sfp0_wb_adr(sfp0_wb_adr), 1375 .sfp0_wb_sel(), .sfp0_wb_ack(sfp0_wb_ack), .sfp0_wb_stb(sfp0_wb_stb), 1376 .sfp0_wb_cyc(sfp0_wb_cyc), .sfp0_wb_we(sfp0_wb_we), .sfp0_wb_int(sfp0_wb_int), 1377 .sfp1_wb_dat_i(sfp1_wb_dat_i), .sfp1_wb_dat_o(sfp1_wb_dat_o), .sfp1_wb_adr(sfp1_wb_adr), 1378 .sfp1_wb_sel(), .sfp1_wb_ack(sfp1_wb_ack), .sfp1_wb_stb(sfp1_wb_stb), 1379 .sfp1_wb_cyc(sfp1_wb_cyc), .sfp1_wb_we(sfp1_wb_we), .sfp1_wb_int(sfp1_wb_int), 1380 // Time 1381 .pps(pps),.pps_select(pps_select), .pps_out_enb(pps_out_enb), 1382 .ref_freq(ref_freq), .ref_freq_changed(ref_freq_changed), 1383 // GPS Signals 1384 .gps_txd(GPS_SER_IN), .gps_rxd(GPS_SER_OUT), 1385 // Debug UART 1386 .debug_rxd(debug_rxd), .debug_txd(debug_txd), 1387 // Misc. 1388 .led_misc(leds), 1389 .xadc_readback({20'h0, device_temp}), 1390 .debug0(), .debug1(), .debug2(), 1391 // DRAM signals. 1392 .ddr3_axi_clk (ddr3_axi_clk), 1393 .ddr3_axi_clk_x2 (ddr3_axi_clk_x2), 1394 .ddr3_axi_rst (ddr3_axi_rst), 1395 // Slave Interface Write Address Ports 1396 .ddr3_axi_awid (s_axi_awid), 1397 .ddr3_axi_awaddr (s_axi_awaddr), 1398 .ddr3_axi_awlen (s_axi_awlen), 1399 .ddr3_axi_awsize (s_axi_awsize), 1400 .ddr3_axi_awburst (s_axi_awburst), 1401 .ddr3_axi_awlock (s_axi_awlock), 1402 .ddr3_axi_awcache (s_axi_awcache), 1403 .ddr3_axi_awprot (s_axi_awprot), 1404 .ddr3_axi_awqos (s_axi_awqos), 1405 .ddr3_axi_awvalid (s_axi_awvalid), 1406 .ddr3_axi_awready (s_axi_awready), 1407 // Slave Interface Write Data Ports 1408 .ddr3_axi_wdata (s_axi_wdata), 1409 .ddr3_axi_wstrb (s_axi_wstrb), 1410 .ddr3_axi_wlast (s_axi_wlast), 1411 .ddr3_axi_wvalid (s_axi_wvalid), 1412 .ddr3_axi_wready (s_axi_wready), 1413 // Slave Interface Write Response Ports 1414 .ddr3_axi_bid (s_axi_bid), 1415 .ddr3_axi_bresp (s_axi_bresp), 1416 .ddr3_axi_bvalid (s_axi_bvalid), 1417 .ddr3_axi_bready (s_axi_bready), 1418 // Slave Interface Read Address Ports 1419 .ddr3_axi_arid (s_axi_arid), 1420 .ddr3_axi_araddr (s_axi_araddr), 1421 .ddr3_axi_arlen (s_axi_arlen), 1422 .ddr3_axi_arsize (s_axi_arsize), 1423 .ddr3_axi_arburst (s_axi_arburst), 1424 .ddr3_axi_arlock (s_axi_arlock), 1425 .ddr3_axi_arcache (s_axi_arcache), 1426 .ddr3_axi_arprot (s_axi_arprot), 1427 .ddr3_axi_arqos (s_axi_arqos), 1428 .ddr3_axi_arvalid (s_axi_arvalid), 1429 .ddr3_axi_arready (s_axi_arready), 1430 // Slave Interface Read Data Ports 1431 .ddr3_axi_rid (s_axi_rid), 1432 .ddr3_axi_rdata (s_axi_rdata), 1433 .ddr3_axi_rresp (s_axi_rresp), 1434 .ddr3_axi_rlast (s_axi_rlast), 1435 .ddr3_axi_rvalid (s_axi_rvalid), 1436 .ddr3_axi_rready (s_axi_rready), 1437 // IoPort2 Message FIFOs 1438 .o_iop2_msg_tdata (o_iop2_msg_tdata), 1439 .o_iop2_msg_tvalid (o_iop2_msg_tvalid), 1440 .o_iop2_msg_tlast (o_iop2_msg_tlast), 1441 .o_iop2_msg_tready (o_iop2_msg_tready), 1442 .i_iop2_msg_tdata (i_iop2_msg_tdata), 1443 .i_iop2_msg_tvalid (i_iop2_msg_tvalid), 1444 .i_iop2_msg_tlast (i_iop2_msg_tlast), 1445 .i_iop2_msg_tready (i_iop2_msg_tready), 1446 // PCIe DMA Data 1447 .pcio_tdata (pcio_tdata), 1448 .pcio_tuser (pcio_tuser), 1449 .pcio_tlast (pcio_tlast), 1450 .pcio_tvalid (pcio_tvalid), 1451 .pcio_tready (pcio_tready), 1452 .pcii_tdata (pcii_tdata), 1453 .pcii_tuser (pcii_tuser), 1454 .pcii_tlast (pcii_tlast), 1455 .pcii_tvalid (pcii_tvalid), 1456 .pcii_tready (pcii_tready) 1457 ); 1458 1459 assign {DB_ADC_RESET, DB_DAC_RESET,DB0_DAC_ENABLE} = radio0_misc_out[2:0]; 1460 assign {DB1_DAC_ENABLE} = radio1_misc_out[0]; //[2:1] unused 1461 1462 ///////////////////////////////////////////////////////////////////// 1463 // 1464 // PUDC Workaround 1465 // 1466 ////////////////////////////////////////////////////////////////////// 1467 // This is a workaround for a silicon bug in Series 7 FPGA where a 1468 // race condition with the reading of PUDC during the erase of the FPGA 1469 // image cause glitches on output IO pins. This glitch happens even if 1470 // you have PUDC correctly pulled high!! When PUDC is high the pull up 1471 // resistor should never be enabled on the IO lines, however there is a 1472 // race condition that causes this to not be the case. 1473 // 1474 // Workaround: 1475 // - Define the PUDC pin in the XDC file with a pullup. 1476 // - Implements an IBUF on the PUDC input and make sure that it does 1477 // not get optimized out. 1478 (* dont_touch = "true" *) wire fpga_pudc_b_buf; 1479 IBUF pudc_ibuf_i ( 1480 .I(FPGA_PUDC_B), 1481 .O(fpga_pudc_b_buf)); 1482 1483endmodule // x300 1484