1; Machine description for AArch64 architecture.
2; Copyright (C) 2009-2018 Free Software Foundation, Inc.
3; Contributed by ARM Ltd.
4;
5; This file is part of GCC.
6;
7; GCC is free software; you can redistribute it and/or modify it
8; under the terms of the GNU General Public License as published by
9; the Free Software Foundation; either version 3, or (at your option)
10; any later version.
11;
12; GCC is distributed in the hope that it will be useful, but
13; WITHOUT ANY WARRANTY; without even the implied warranty of
14; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15; General Public License for more details.
16;
17; You should have received a copy of the GNU General Public License
18; along with GCC; see the file COPYING3.  If not see
19; <http://www.gnu.org/licenses/>.
20
21HeaderInclude
22config/aarch64/aarch64-opts.h
23
24TargetVariable
25enum aarch64_processor explicit_tune_core = aarch64_none
26
27TargetVariable
28enum aarch64_arch explicit_arch = aarch64_no_arch
29
30TargetSave
31const char *x_aarch64_override_tune_string
32
33TargetVariable
34unsigned long aarch64_isa_flags = 0
35
36; The TLS dialect names to use with -mtls-dialect.
37
38Enum
39Name(tls_type) Type(enum aarch64_tls_type)
40The possible TLS dialects:
41
42EnumValue
43Enum(tls_type) String(trad) Value(TLS_TRADITIONAL)
44
45EnumValue
46Enum(tls_type) String(desc) Value(TLS_DESCRIPTORS)
47
48; The code model option names for -mcmodel.
49
50Enum
51Name(cmodel) Type(enum aarch64_code_model)
52The code model option names for -mcmodel:
53
54EnumValue
55Enum(cmodel) String(tiny) Value(AARCH64_CMODEL_TINY)
56
57EnumValue
58Enum(cmodel) String(small) Value(AARCH64_CMODEL_SMALL)
59
60EnumValue
61Enum(cmodel) String(large) Value(AARCH64_CMODEL_LARGE)
62
63mbig-endian
64Target Report RejectNegative Mask(BIG_END)
65Assume target CPU is configured as big endian.
66
67mgeneral-regs-only
68Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Save
69Generate code which uses only the general registers.
70
71mfix-cortex-a53-835769
72Target Report Var(aarch64_fix_a53_err835769) Init(2) Save
73Workaround for ARM Cortex-A53 Erratum number 835769.
74
75mfix-cortex-a53-843419
76Target Report Var(aarch64_fix_a53_err843419) Init(2) Save
77Workaround for ARM Cortex-A53 Erratum number 843419.
78
79mlittle-endian
80Target Report RejectNegative InverseMask(BIG_END)
81Assume target CPU is configured as little endian.
82
83mcmodel=
84Target RejectNegative Joined Enum(cmodel) Var(aarch64_cmodel_var) Init(AARCH64_CMODEL_SMALL) Save
85Specify the code model.
86
87mstrict-align
88Target Report RejectNegative Mask(STRICT_ALIGN) Save
89Don't assume that unaligned accesses are handled by the system.
90
91momit-leaf-frame-pointer
92Target Report Var(flag_omit_leaf_frame_pointer) Init(2) Save
93Omit the frame pointer in leaf functions.
94
95mtls-dialect=
96Target RejectNegative Joined Enum(tls_type) Var(aarch64_tls_dialect) Init(TLS_DESCRIPTORS) Save
97Specify TLS dialect.
98
99mtls-size=
100Target RejectNegative Joined Var(aarch64_tls_size) Enum(aarch64_tls_size)
101Specifies bit size of immediate TLS offsets.  Valid values are 12, 24, 32, 48.
102
103Enum
104Name(aarch64_tls_size) Type(int)
105
106EnumValue
107Enum(aarch64_tls_size) String(12) Value(12)
108
109EnumValue
110Enum(aarch64_tls_size) String(24) Value(24)
111
112EnumValue
113Enum(aarch64_tls_size) String(32) Value(32)
114
115EnumValue
116Enum(aarch64_tls_size) String(48) Value(48)
117
118march=
119Target RejectNegative ToLower Joined Var(aarch64_arch_string)
120-march=ARCH	Use features of architecture ARCH.
121
122mcpu=
123Target RejectNegative ToLower Joined Var(aarch64_cpu_string)
124-mcpu=CPU	Use features of and optimize for CPU.
125
126mtune=
127Target RejectNegative ToLower Joined Var(aarch64_tune_string)
128-mtune=CPU	Optimize for CPU.
129
130mabi=
131Target RejectNegative Joined Enum(aarch64_abi) Var(aarch64_abi) Init(AARCH64_ABI_DEFAULT)
132-mabi=ABI	Generate code that conforms to the specified ABI.
133
134moverride=
135Target RejectNegative ToLower Joined Var(aarch64_override_tune_string)
136-moverride=STRING	Power users only! Override CPU optimization parameters.
137
138Enum
139Name(aarch64_abi) Type(int)
140Known AArch64 ABIs (for use with the -mabi= option):
141
142EnumValue
143Enum(aarch64_abi) String(ilp32) Value(AARCH64_ABI_ILP32)
144
145EnumValue
146Enum(aarch64_abi) String(lp64) Value(AARCH64_ABI_LP64)
147
148mpc-relative-literal-loads
149Target Report Save Var(pcrelative_literal_loads) Init(2) Save
150PC relative literal loads.
151
152msign-return-address=
153Target RejectNegative Report Joined Enum(aarch64_ra_sign_scope_t) Var(aarch64_ra_sign_scope) Init(AARCH64_FUNCTION_NONE) Save
154Select return address signing scope.
155
156Enum
157Name(aarch64_ra_sign_scope_t) Type(enum aarch64_function_type)
158Supported AArch64 return address signing scope (for use with -msign-return-address= option):
159
160EnumValue
161Enum(aarch64_ra_sign_scope_t) String(none) Value(AARCH64_FUNCTION_NONE)
162
163EnumValue
164Enum(aarch64_ra_sign_scope_t) String(non-leaf) Value(AARCH64_FUNCTION_NON_LEAF)
165
166EnumValue
167Enum(aarch64_ra_sign_scope_t) String(all) Value(AARCH64_FUNCTION_ALL)
168
169mlow-precision-recip-sqrt
170Common Var(flag_mrecip_low_precision_sqrt) Optimization
171Enable the reciprocal square root approximation.  Enabling this reduces
172precision of reciprocal square root results to about 16 bits for
173single precision and to 32 bits for double precision.
174
175mlow-precision-sqrt
176Common Var(flag_mlow_precision_sqrt) Optimization
177Enable the square root approximation.  Enabling this reduces
178precision of square root results to about 16 bits for
179single precision and to 32 bits for double precision.
180If enabled, it implies -mlow-precision-recip-sqrt.
181
182mlow-precision-div
183Common Var(flag_mlow_precision_div) Optimization
184Enable the division approximation.  Enabling this reduces
185precision of division results to about 16 bits for
186single precision and to 32 bits for double precision.
187
188Enum
189Name(sve_vector_bits) Type(enum aarch64_sve_vector_bits_enum)
190The possible SVE vector lengths:
191
192EnumValue
193Enum(sve_vector_bits) String(scalable) Value(SVE_SCALABLE)
194
195EnumValue
196Enum(sve_vector_bits) String(128) Value(SVE_128)
197
198EnumValue
199Enum(sve_vector_bits) String(256) Value(SVE_256)
200
201EnumValue
202Enum(sve_vector_bits) String(512) Value(SVE_512)
203
204EnumValue
205Enum(sve_vector_bits) String(1024) Value(SVE_1024)
206
207EnumValue
208Enum(sve_vector_bits) String(2048) Value(SVE_2048)
209
210msve-vector-bits=
211Target RejectNegative Joined Enum(sve_vector_bits) Var(aarch64_sve_vector_bits) Init(SVE_SCALABLE)
212-msve-vector-bits=N	Set the number of bits in an SVE vector register to N.
213
214mverbose-cost-dump
215Common Undocumented Var(flag_aarch64_verbose_cost)
216Enables verbose cost model dumping in the debug dump files.
217