1 /* { dg-do compile { target { powerpc*-*-* } } } */ 2 /* { dg-skip-if "" { powerpc*-*-darwin* } } */ 3 /* { dg-require-effective-target powerpc_p8vector_ok } */ 4 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ 5 /* { dg-options "-mcpu=power8 -O3 -ftree-vectorize -fvect-cost-model=dynamic" } */ 6 7 #include <altivec.h> 8 9 typedef vector long long vll_sign; 10 typedef vector unsigned long long vll_uns; 11 typedef vector bool long long vll_bool; 12 13 typedef vector int vi_sign; 14 typedef vector unsigned int vi_uns; 15 typedef vector bool int vi_bool; 16 17 typedef vector short vs_sign; 18 typedef vector unsigned short vs_uns; 19 typedef vector bool short vs_bool; 20 21 typedef vector signed char vc_sign; 22 typedef vector unsigned char vc_uns; 23 typedef vector bool char vc_bool; 24 vll_clz_1(vll_sign a)25vll_sign vll_clz_1 (vll_sign a) 26 { 27 return __builtin_altivec_vclzd (a); 28 } 29 vll_clz_2(vll_sign a)30vll_sign vll_clz_2 (vll_sign a) 31 { 32 return vec_vclz (a); 33 } 34 vll_clz_3(vll_sign a)35vll_sign vll_clz_3 (vll_sign a) 36 { 37 return vec_vclzd (a); 38 } 39 vll_clz_4(vll_uns a)40vll_uns vll_clz_4 (vll_uns a) 41 { 42 return vec_vclz (a); 43 } 44 vll_clz_5(vll_uns a)45vll_uns vll_clz_5 (vll_uns a) 46 { 47 return vec_vclzd (a); 48 } 49 vi_clz_1(vi_sign a)50vi_sign vi_clz_1 (vi_sign a) 51 { 52 return __builtin_altivec_vclzw (a); 53 } 54 vi_clz_2(vi_sign a)55vi_sign vi_clz_2 (vi_sign a) 56 { 57 return vec_vclz (a); 58 } 59 vi_clz_3(vi_sign a)60vi_sign vi_clz_3 (vi_sign a) 61 { 62 return vec_vclzw (a); 63 } 64 vi_clz_4(vi_uns a)65vi_uns vi_clz_4 (vi_uns a) 66 { 67 return vec_vclz (a); 68 } 69 vi_clz_5(vi_uns a)70vi_uns vi_clz_5 (vi_uns a) 71 { 72 return vec_vclzw (a); 73 } 74 vs_clz_1(vs_sign a)75vs_sign vs_clz_1 (vs_sign a) 76 { 77 return __builtin_altivec_vclzh (a); 78 } 79 vs_clz_2(vs_sign a)80vs_sign vs_clz_2 (vs_sign a) 81 { 82 return vec_vclz (a); 83 } 84 vs_clz_3(vs_sign a)85vs_sign vs_clz_3 (vs_sign a) 86 { 87 return vec_vclzh (a); 88 } 89 vs_clz_4(vs_uns a)90vs_uns vs_clz_4 (vs_uns a) 91 { 92 return vec_vclz (a); 93 } 94 vs_clz_5(vs_uns a)95vs_uns vs_clz_5 (vs_uns a) 96 { 97 return vec_vclzh (a); 98 } 99 vc_clz_1(vc_sign a)100vc_sign vc_clz_1 (vc_sign a) 101 { 102 return __builtin_altivec_vclzb (a); 103 } 104 vc_clz_2(vc_sign a)105vc_sign vc_clz_2 (vc_sign a) 106 { 107 return vec_vclz (a); 108 } 109 vc_clz_3(vc_sign a)110vc_sign vc_clz_3 (vc_sign a) 111 { 112 return vec_vclzb (a); 113 } 114 vc_clz_4(vc_uns a)115vc_uns vc_clz_4 (vc_uns a) 116 { 117 return vec_vclz (a); 118 } 119 vc_clz_5(vc_uns a)120vc_uns vc_clz_5 (vc_uns a) 121 { 122 return vec_vclzb (a); 123 } 124 vll_popcnt_1(vll_sign a)125vll_sign vll_popcnt_1 (vll_sign a) 126 { 127 return __builtin_altivec_vpopcntd (a); 128 } 129 vll_popcnt_2(vll_sign a)130vll_sign vll_popcnt_2 (vll_sign a) 131 { 132 return vec_vpopcnt (a); 133 } 134 vll_popcnt_3(vll_sign a)135vll_sign vll_popcnt_3 (vll_sign a) 136 { 137 return vec_vpopcntd (a); 138 } 139 vll_popcnt_4(vll_uns a)140vll_uns vll_popcnt_4 (vll_uns a) 141 { 142 return vec_vpopcnt (a); 143 } 144 vll_popcnt_5(vll_uns a)145vll_uns vll_popcnt_5 (vll_uns a) 146 { 147 return vec_vpopcntd (a); 148 } 149 vi_popcnt_1(vi_sign a)150vi_sign vi_popcnt_1 (vi_sign a) 151 { 152 return __builtin_altivec_vpopcntw (a); 153 } 154 vi_popcnt_2(vi_sign a)155vi_sign vi_popcnt_2 (vi_sign a) 156 { 157 return vec_vpopcnt (a); 158 } 159 vi_popcnt_3(vi_sign a)160vi_sign vi_popcnt_3 (vi_sign a) 161 { 162 return vec_vpopcntw (a); 163 } 164 vi_popcnt_4(vi_uns a)165vi_uns vi_popcnt_4 (vi_uns a) 166 { 167 return vec_vpopcnt (a); 168 } 169 vi_popcnt_5(vi_uns a)170vi_uns vi_popcnt_5 (vi_uns a) 171 { 172 return vec_vpopcntw (a); 173 } 174 vs_popcnt_1(vs_sign a)175vs_sign vs_popcnt_1 (vs_sign a) 176 { 177 return __builtin_altivec_vpopcnth (a); 178 } 179 vs_popcnt_2(vs_sign a)180vs_sign vs_popcnt_2 (vs_sign a) 181 { 182 return vec_vpopcnt (a); 183 } 184 vs_popcnt_3(vs_sign a)185vs_sign vs_popcnt_3 (vs_sign a) 186 { 187 return vec_vpopcnth (a); 188 } 189 vs_popcnt_4(vs_uns a)190vs_uns vs_popcnt_4 (vs_uns a) 191 { 192 return vec_vpopcnt (a); 193 } 194 vs_popcnt_5(vs_uns a)195vs_uns vs_popcnt_5 (vs_uns a) 196 { 197 return vec_vpopcnth (a); 198 } 199 vc_popcnt_1(vc_sign a)200vc_sign vc_popcnt_1 (vc_sign a) 201 { 202 return __builtin_altivec_vpopcntb (a); 203 } 204 vc_popcnt_2(vc_sign a)205vc_sign vc_popcnt_2 (vc_sign a) 206 { 207 return vec_vpopcnt (a); 208 } 209 vc_popcnt_3(vc_sign a)210vc_sign vc_popcnt_3 (vc_sign a) 211 { 212 return vec_vpopcntb (a); 213 } 214 vc_popcnt_4(vc_uns a)215vc_uns vc_popcnt_4 (vc_uns a) 216 { 217 return vec_vpopcnt (a); 218 } 219 vc_popcnt_5(vc_uns a)220vc_uns vc_popcnt_5 (vc_uns a) 221 { 222 return vec_vpopcntb (a); 223 } 224 vc_gbb_1(vc_uns a)225vc_uns vc_gbb_1 (vc_uns a) 226 { 227 return __builtin_altivec_vgbbd (a); 228 } 229 vc_gbb_2(vc_sign a)230vc_sign vc_gbb_2 (vc_sign a) 231 { 232 return vec_vgbbd (a); 233 } 234 vc_gbb_3(vc_uns a)235vc_uns vc_gbb_3 (vc_uns a) 236 { 237 return vec_vgbbd (a); 238 } 239 240 /* { dg-final { scan-assembler-times "vclzd" 5 } } */ 241 /* { dg-final { scan-assembler-times "vclzw" 5 } } */ 242 /* { dg-final { scan-assembler-times "vclzh" 5 } } */ 243 /* { dg-final { scan-assembler-times "vclzb" 5 } } */ 244 245 /* { dg-final { scan-assembler-times "vpopcntd" 5 } } */ 246 /* { dg-final { scan-assembler-times "vpopcntw" 5 } } */ 247 /* { dg-final { scan-assembler-times "vpopcnth" 5 } } */ 248 /* { dg-final { scan-assembler-times "vpopcntb" 5 } } */ 249 250 /* { dg-final { scan-assembler-times "vgbbd" 3 } } */ 251