1;; Machine description for AArch64 architecture. 2;; Copyright (C) 2009-2018 Free Software Foundation, Inc. 3;; Contributed by ARM Ltd. 4;; 5;; This file is part of GCC. 6;; 7;; GCC is free software; you can redistribute it and/or modify it 8;; under the terms of the GNU General Public License as published by 9;; the Free Software Foundation; either version 3, or (at your option) 10;; any later version. 11;; 12;; GCC is distributed in the hope that it will be useful, but 13;; WITHOUT ANY WARRANTY; without even the implied warranty of 14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15;; General Public License for more details. 16;; 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21;; ------------------------------------------------------------------- 22;; Mode Iterators 23;; ------------------------------------------------------------------- 24 25 26;; Iterator for General Purpose Integer registers (32- and 64-bit modes) 27(define_mode_iterator GPI [SI DI]) 28 29;; Iterator for HI, SI, DI, some instructions can only work on these modes. 30(define_mode_iterator GPI_I16 [(HI "AARCH64_ISA_F16") SI DI]) 31 32;; Iterator for QI and HI modes 33(define_mode_iterator SHORT [QI HI]) 34 35;; Iterator for all integer modes (up to 64-bit) 36(define_mode_iterator ALLI [QI HI SI DI]) 37 38;; Iterator for all integer modes that can be extended (up to 64-bit) 39(define_mode_iterator ALLX [QI HI SI]) 40 41;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes) 42(define_mode_iterator GPF [SF DF]) 43 44;; Iterator for all scalar floating point modes (HF, SF, DF) 45(define_mode_iterator GPF_F16 [(HF "AARCH64_ISA_F16") SF DF]) 46 47;; Iterator for all scalar floating point modes (HF, SF, DF) 48(define_mode_iterator GPF_HF [HF SF DF]) 49 50;; Iterator for all scalar floating point modes (HF, SF, DF and TF) 51(define_mode_iterator GPF_TF_F16 [HF SF DF TF]) 52 53;; Double vector modes. 54(define_mode_iterator VDF [V2SF V4HF]) 55 56;; Iterator for all scalar floating point modes (SF, DF and TF) 57(define_mode_iterator GPF_TF [SF DF TF]) 58 59;; Integer Advanced SIMD modes. 60(define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI]) 61 62;; Advanced SIMD and scalar, 64 & 128-bit container, all integer modes. 63(define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI]) 64 65;; Advanced SIMD and scalar, 64 & 128-bit container: all Advanced SIMD 66;; integer modes; 64-bit scalar integer mode. 67(define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI]) 68 69;; Double vector modes. 70(define_mode_iterator VD [V8QI V4HI V4HF V2SI V2SF]) 71 72;; Advanced SIMD, 64-bit container, all integer modes. 73(define_mode_iterator VD_BHSI [V8QI V4HI V2SI]) 74 75;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes 76(define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI]) 77 78;; Quad vector modes. 79(define_mode_iterator VQ [V16QI V8HI V4SI V2DI V8HF V4SF V2DF]) 80 81;; VQ without 2 element modes. 82(define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V8HF V4SF]) 83 84;; Quad vector with only 2 element modes. 85(define_mode_iterator VQ_2E [V2DI V2DF]) 86 87;; This mode iterator allows :P to be used for patterns that operate on 88;; addresses in different modes. In LP64, only DI will match, while in 89;; ILP32, either can match. 90(define_mode_iterator P [(SI "ptr_mode == SImode || Pmode == SImode") 91 (DI "ptr_mode == DImode || Pmode == DImode")]) 92 93;; This mode iterator allows :PTR to be used for patterns that operate on 94;; pointer-sized quantities. Exactly one of the two alternatives will match. 95(define_mode_iterator PTR [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")]) 96 97;; Advanced SIMD Float modes suitable for moving, loading and storing. 98(define_mode_iterator VDQF_F16 [V4HF V8HF V2SF V4SF V2DF]) 99 100;; Advanced SIMD Float modes. 101(define_mode_iterator VDQF [V2SF V4SF V2DF]) 102(define_mode_iterator VHSDF [(V4HF "TARGET_SIMD_F16INST") 103 (V8HF "TARGET_SIMD_F16INST") 104 V2SF V4SF V2DF]) 105 106;; Advanced SIMD Float modes, and DF. 107(define_mode_iterator VHSDF_DF [(V4HF "TARGET_SIMD_F16INST") 108 (V8HF "TARGET_SIMD_F16INST") 109 V2SF V4SF V2DF DF]) 110(define_mode_iterator VHSDF_HSDF [(V4HF "TARGET_SIMD_F16INST") 111 (V8HF "TARGET_SIMD_F16INST") 112 V2SF V4SF V2DF 113 (HF "TARGET_SIMD_F16INST") 114 SF DF]) 115 116;; Advanced SIMD single Float modes. 117(define_mode_iterator VDQSF [V2SF V4SF]) 118 119;; Quad vector Float modes with half/single elements. 120(define_mode_iterator VQ_HSF [V8HF V4SF]) 121 122;; Modes suitable to use as the return type of a vcond expression. 123(define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI]) 124 125;; All scalar and Advanced SIMD Float modes. 126(define_mode_iterator VALLF [V2SF V4SF V2DF SF DF]) 127 128;; Advanced SIMD Float modes with 2 elements. 129(define_mode_iterator V2F [V2SF V2DF]) 130 131;; All Advanced SIMD modes on which we support any arithmetic operations. 132(define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF]) 133 134;; All Advanced SIMD modes suitable for moving, loading, and storing. 135(define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI 136 V4HF V8HF V2SF V4SF V2DF]) 137 138;; The VALL_F16 modes except the 128-bit 2-element ones. 139(define_mode_iterator VALL_F16_NO_V2Q [V8QI V16QI V4HI V8HI V2SI V4SI 140 V4HF V8HF V2SF V4SF]) 141 142;; All Advanced SIMD modes barring HF modes, plus DI. 143(define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI]) 144 145;; All Advanced SIMD modes and DI. 146(define_mode_iterator VALLDI_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI 147 V4HF V8HF V2SF V4SF V2DF DI]) 148 149;; All Advanced SIMD modes, plus DI and DF. 150(define_mode_iterator VALLDIF [V8QI V16QI V4HI V8HI V2SI V4SI 151 V2DI V4HF V8HF V2SF V4SF V2DF DI DF]) 152 153;; Advanced SIMD modes for Integer reduction across lanes. 154(define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI]) 155 156;; Advanced SIMD modes (except V2DI) for Integer reduction across lanes. 157(define_mode_iterator VDQV_S [V8QI V16QI V4HI V8HI V4SI]) 158 159;; All double integer narrow-able modes. 160(define_mode_iterator VDN [V4HI V2SI DI]) 161 162;; All quad integer narrow-able modes. 163(define_mode_iterator VQN [V8HI V4SI V2DI]) 164 165;; Advanced SIMD and scalar 128-bit container: narrowable 16, 32, 64-bit 166;; integer modes 167(define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI]) 168 169;; All quad integer widen-able modes. 170(define_mode_iterator VQW [V16QI V8HI V4SI]) 171 172;; Double vector modes for combines. 173(define_mode_iterator VDC [V8QI V4HI V4HF V2SI V2SF DI DF]) 174 175;; Advanced SIMD modes except double int. 176(define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF]) 177(define_mode_iterator VDQIF_F16 [V8QI V16QI V4HI V8HI V2SI V4SI 178 V4HF V8HF V2SF V4SF V2DF]) 179 180;; Advanced SIMD modes for S type. 181(define_mode_iterator VDQ_SI [V2SI V4SI]) 182 183;; Advanced SIMD modes for S and D. 184(define_mode_iterator VDQ_SDI [V2SI V4SI V2DI]) 185 186;; Advanced SIMD modes for H, S and D. 187(define_mode_iterator VDQ_HSDI [(V4HI "TARGET_SIMD_F16INST") 188 (V8HI "TARGET_SIMD_F16INST") 189 V2SI V4SI V2DI]) 190 191;; Scalar and Advanced SIMD modes for S and D. 192(define_mode_iterator VSDQ_SDI [V2SI V4SI V2DI SI DI]) 193 194;; Scalar and Advanced SIMD modes for S and D, Advanced SIMD modes for H. 195(define_mode_iterator VSDQ_HSDI [(V4HI "TARGET_SIMD_F16INST") 196 (V8HI "TARGET_SIMD_F16INST") 197 V2SI V4SI V2DI 198 (HI "TARGET_SIMD_F16INST") 199 SI DI]) 200 201;; Advanced SIMD modes for Q and H types. 202(define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI]) 203 204;; Advanced SIMD modes for H and S types. 205(define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI]) 206 207;; Advanced SIMD modes for H, S and D types. 208(define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI]) 209 210;; Advanced SIMD and scalar integer modes for H and S. 211(define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI]) 212 213;; Advanced SIMD and scalar 64-bit container: 16, 32-bit integer modes. 214(define_mode_iterator VSD_HSI [V4HI V2SI HI SI]) 215 216;; Advanced SIMD 64-bit container: 16, 32-bit integer modes. 217(define_mode_iterator VD_HSI [V4HI V2SI]) 218 219;; Scalar 64-bit container: 16, 32-bit integer modes 220(define_mode_iterator SD_HSI [HI SI]) 221 222;; Advanced SIMD 64-bit container: 16, 32-bit integer modes. 223(define_mode_iterator VQ_HSI [V8HI V4SI]) 224 225;; All byte modes. 226(define_mode_iterator VB [V8QI V16QI]) 227 228;; 2 and 4 lane SI modes. 229(define_mode_iterator VS [V2SI V4SI]) 230 231(define_mode_iterator TX [TI TF]) 232 233;; Advanced SIMD opaque structure modes. 234(define_mode_iterator VSTRUCT [OI CI XI]) 235 236;; Double scalar modes 237(define_mode_iterator DX [DI DF]) 238 239;; Modes available for Advanced SIMD <f>mul lane operations. 240(define_mode_iterator VMUL [V4HI V8HI V2SI V4SI 241 (V4HF "TARGET_SIMD_F16INST") 242 (V8HF "TARGET_SIMD_F16INST") 243 V2SF V4SF V2DF]) 244 245;; Modes available for Advanced SIMD <f>mul lane operations changing lane 246;; count. 247(define_mode_iterator VMUL_CHANGE_NLANES [V4HI V8HI V2SI V4SI V2SF V4SF]) 248 249;; All SVE vector modes. 250(define_mode_iterator SVE_ALL [VNx16QI VNx8HI VNx4SI VNx2DI 251 VNx8HF VNx4SF VNx2DF]) 252 253;; All SVE vector structure modes. 254(define_mode_iterator SVE_STRUCT [VNx32QI VNx16HI VNx8SI VNx4DI 255 VNx16HF VNx8SF VNx4DF 256 VNx48QI VNx24HI VNx12SI VNx6DI 257 VNx24HF VNx12SF VNx6DF 258 VNx64QI VNx32HI VNx16SI VNx8DI 259 VNx32HF VNx16SF VNx8DF]) 260 261;; All SVE vector modes that have 8-bit or 16-bit elements. 262(define_mode_iterator SVE_BH [VNx16QI VNx8HI VNx8HF]) 263 264;; All SVE vector modes that have 8-bit, 16-bit or 32-bit elements. 265(define_mode_iterator SVE_BHS [VNx16QI VNx8HI VNx4SI VNx8HF VNx4SF]) 266 267;; All SVE integer vector modes that have 8-bit, 16-bit or 32-bit elements. 268(define_mode_iterator SVE_BHSI [VNx16QI VNx8HI VNx4SI]) 269 270;; All SVE integer vector modes that have 16-bit, 32-bit or 64-bit elements. 271(define_mode_iterator SVE_HSDI [VNx16QI VNx8HI VNx4SI]) 272 273;; All SVE floating-point vector modes that have 16-bit or 32-bit elements. 274(define_mode_iterator SVE_HSF [VNx8HF VNx4SF]) 275 276;; All SVE vector modes that have 32-bit or 64-bit elements. 277(define_mode_iterator SVE_SD [VNx4SI VNx2DI VNx4SF VNx2DF]) 278 279;; All SVE vector modes that have 32-bit elements. 280(define_mode_iterator SVE_S [VNx4SI VNx4SF]) 281 282;; All SVE vector modes that have 64-bit elements. 283(define_mode_iterator SVE_D [VNx2DI VNx2DF]) 284 285;; All SVE integer vector modes that have 32-bit or 64-bit elements. 286(define_mode_iterator SVE_SDI [VNx4SI VNx2DI]) 287 288;; All SVE integer vector modes. 289(define_mode_iterator SVE_I [VNx16QI VNx8HI VNx4SI VNx2DI]) 290 291;; All SVE floating-point vector modes. 292(define_mode_iterator SVE_F [VNx8HF VNx4SF VNx2DF]) 293 294;; All SVE predicate modes. 295(define_mode_iterator PRED_ALL [VNx16BI VNx8BI VNx4BI VNx2BI]) 296 297;; SVE predicate modes that control 8-bit, 16-bit or 32-bit elements. 298(define_mode_iterator PRED_BHS [VNx16BI VNx8BI VNx4BI]) 299 300;; ------------------------------------------------------------------ 301;; Unspec enumerations for Advance SIMD. These could well go into 302;; aarch64.md but for their use in int_iterators here. 303;; ------------------------------------------------------------------ 304 305(define_c_enum "unspec" 306 [ 307 UNSPEC_ASHIFT_SIGNED ; Used in aarch-simd.md. 308 UNSPEC_ASHIFT_UNSIGNED ; Used in aarch64-simd.md. 309 UNSPEC_ABS ; Used in aarch64-simd.md. 310 UNSPEC_FMAX ; Used in aarch64-simd.md. 311 UNSPEC_FMAXNMV ; Used in aarch64-simd.md. 312 UNSPEC_FMAXV ; Used in aarch64-simd.md. 313 UNSPEC_FMIN ; Used in aarch64-simd.md. 314 UNSPEC_FMINNMV ; Used in aarch64-simd.md. 315 UNSPEC_FMINV ; Used in aarch64-simd.md. 316 UNSPEC_FADDV ; Used in aarch64-simd.md. 317 UNSPEC_ADDV ; Used in aarch64-simd.md. 318 UNSPEC_SMAXV ; Used in aarch64-simd.md. 319 UNSPEC_SMINV ; Used in aarch64-simd.md. 320 UNSPEC_UMAXV ; Used in aarch64-simd.md. 321 UNSPEC_UMINV ; Used in aarch64-simd.md. 322 UNSPEC_SHADD ; Used in aarch64-simd.md. 323 UNSPEC_UHADD ; Used in aarch64-simd.md. 324 UNSPEC_SRHADD ; Used in aarch64-simd.md. 325 UNSPEC_URHADD ; Used in aarch64-simd.md. 326 UNSPEC_SHSUB ; Used in aarch64-simd.md. 327 UNSPEC_UHSUB ; Used in aarch64-simd.md. 328 UNSPEC_SRHSUB ; Used in aarch64-simd.md. 329 UNSPEC_URHSUB ; Used in aarch64-simd.md. 330 UNSPEC_ADDHN ; Used in aarch64-simd.md. 331 UNSPEC_RADDHN ; Used in aarch64-simd.md. 332 UNSPEC_SUBHN ; Used in aarch64-simd.md. 333 UNSPEC_RSUBHN ; Used in aarch64-simd.md. 334 UNSPEC_ADDHN2 ; Used in aarch64-simd.md. 335 UNSPEC_RADDHN2 ; Used in aarch64-simd.md. 336 UNSPEC_SUBHN2 ; Used in aarch64-simd.md. 337 UNSPEC_RSUBHN2 ; Used in aarch64-simd.md. 338 UNSPEC_SQDMULH ; Used in aarch64-simd.md. 339 UNSPEC_SQRDMULH ; Used in aarch64-simd.md. 340 UNSPEC_PMUL ; Used in aarch64-simd.md. 341 UNSPEC_FMULX ; Used in aarch64-simd.md. 342 UNSPEC_USQADD ; Used in aarch64-simd.md. 343 UNSPEC_SUQADD ; Used in aarch64-simd.md. 344 UNSPEC_SQXTUN ; Used in aarch64-simd.md. 345 UNSPEC_SQXTN ; Used in aarch64-simd.md. 346 UNSPEC_UQXTN ; Used in aarch64-simd.md. 347 UNSPEC_SSRA ; Used in aarch64-simd.md. 348 UNSPEC_USRA ; Used in aarch64-simd.md. 349 UNSPEC_SRSRA ; Used in aarch64-simd.md. 350 UNSPEC_URSRA ; Used in aarch64-simd.md. 351 UNSPEC_SRSHR ; Used in aarch64-simd.md. 352 UNSPEC_URSHR ; Used in aarch64-simd.md. 353 UNSPEC_SQSHLU ; Used in aarch64-simd.md. 354 UNSPEC_SQSHL ; Used in aarch64-simd.md. 355 UNSPEC_UQSHL ; Used in aarch64-simd.md. 356 UNSPEC_SQSHRUN ; Used in aarch64-simd.md. 357 UNSPEC_SQRSHRUN ; Used in aarch64-simd.md. 358 UNSPEC_SQSHRN ; Used in aarch64-simd.md. 359 UNSPEC_UQSHRN ; Used in aarch64-simd.md. 360 UNSPEC_SQRSHRN ; Used in aarch64-simd.md. 361 UNSPEC_UQRSHRN ; Used in aarch64-simd.md. 362 UNSPEC_SSHL ; Used in aarch64-simd.md. 363 UNSPEC_USHL ; Used in aarch64-simd.md. 364 UNSPEC_SRSHL ; Used in aarch64-simd.md. 365 UNSPEC_URSHL ; Used in aarch64-simd.md. 366 UNSPEC_SQRSHL ; Used in aarch64-simd.md. 367 UNSPEC_UQRSHL ; Used in aarch64-simd.md. 368 UNSPEC_SSLI ; Used in aarch64-simd.md. 369 UNSPEC_USLI ; Used in aarch64-simd.md. 370 UNSPEC_SSRI ; Used in aarch64-simd.md. 371 UNSPEC_USRI ; Used in aarch64-simd.md. 372 UNSPEC_SSHLL ; Used in aarch64-simd.md. 373 UNSPEC_USHLL ; Used in aarch64-simd.md. 374 UNSPEC_ADDP ; Used in aarch64-simd.md. 375 UNSPEC_TBL ; Used in vector permute patterns. 376 UNSPEC_TBX ; Used in vector permute patterns. 377 UNSPEC_CONCAT ; Used in vector permute patterns. 378 379 ;; The following permute unspecs are generated directly by 380 ;; aarch64_expand_vec_perm_const, so any changes to the underlying 381 ;; instructions would need a corresponding change there. 382 UNSPEC_ZIP1 ; Used in vector permute patterns. 383 UNSPEC_ZIP2 ; Used in vector permute patterns. 384 UNSPEC_UZP1 ; Used in vector permute patterns. 385 UNSPEC_UZP2 ; Used in vector permute patterns. 386 UNSPEC_TRN1 ; Used in vector permute patterns. 387 UNSPEC_TRN2 ; Used in vector permute patterns. 388 UNSPEC_EXT ; Used in vector permute patterns. 389 UNSPEC_REV64 ; Used in vector reverse patterns (permute). 390 UNSPEC_REV32 ; Used in vector reverse patterns (permute). 391 UNSPEC_REV16 ; Used in vector reverse patterns (permute). 392 393 UNSPEC_AESE ; Used in aarch64-simd.md. 394 UNSPEC_AESD ; Used in aarch64-simd.md. 395 UNSPEC_AESMC ; Used in aarch64-simd.md. 396 UNSPEC_AESIMC ; Used in aarch64-simd.md. 397 UNSPEC_SHA1C ; Used in aarch64-simd.md. 398 UNSPEC_SHA1M ; Used in aarch64-simd.md. 399 UNSPEC_SHA1P ; Used in aarch64-simd.md. 400 UNSPEC_SHA1H ; Used in aarch64-simd.md. 401 UNSPEC_SHA1SU0 ; Used in aarch64-simd.md. 402 UNSPEC_SHA1SU1 ; Used in aarch64-simd.md. 403 UNSPEC_SHA256H ; Used in aarch64-simd.md. 404 UNSPEC_SHA256H2 ; Used in aarch64-simd.md. 405 UNSPEC_SHA256SU0 ; Used in aarch64-simd.md. 406 UNSPEC_SHA256SU1 ; Used in aarch64-simd.md. 407 UNSPEC_PMULL ; Used in aarch64-simd.md. 408 UNSPEC_PMULL2 ; Used in aarch64-simd.md. 409 UNSPEC_REV_REGLIST ; Used in aarch64-simd.md. 410 UNSPEC_VEC_SHR ; Used in aarch64-simd.md. 411 UNSPEC_SQRDMLAH ; Used in aarch64-simd.md. 412 UNSPEC_SQRDMLSH ; Used in aarch64-simd.md. 413 UNSPEC_FMAXNM ; Used in aarch64-simd.md. 414 UNSPEC_FMINNM ; Used in aarch64-simd.md. 415 UNSPEC_SDOT ; Used in aarch64-simd.md. 416 UNSPEC_UDOT ; Used in aarch64-simd.md. 417 UNSPEC_SM3SS1 ; Used in aarch64-simd.md. 418 UNSPEC_SM3TT1A ; Used in aarch64-simd.md. 419 UNSPEC_SM3TT1B ; Used in aarch64-simd.md. 420 UNSPEC_SM3TT2A ; Used in aarch64-simd.md. 421 UNSPEC_SM3TT2B ; Used in aarch64-simd.md. 422 UNSPEC_SM3PARTW1 ; Used in aarch64-simd.md. 423 UNSPEC_SM3PARTW2 ; Used in aarch64-simd.md. 424 UNSPEC_SM4E ; Used in aarch64-simd.md. 425 UNSPEC_SM4EKEY ; Used in aarch64-simd.md. 426 UNSPEC_SHA512H ; Used in aarch64-simd.md. 427 UNSPEC_SHA512H2 ; Used in aarch64-simd.md. 428 UNSPEC_SHA512SU0 ; Used in aarch64-simd.md. 429 UNSPEC_SHA512SU1 ; Used in aarch64-simd.md. 430 UNSPEC_FMLAL ; Used in aarch64-simd.md. 431 UNSPEC_FMLSL ; Used in aarch64-simd.md. 432 UNSPEC_FMLAL2 ; Used in aarch64-simd.md. 433 UNSPEC_FMLSL2 ; Used in aarch64-simd.md. 434 UNSPEC_SEL ; Used in aarch64-sve.md. 435 UNSPEC_ANDV ; Used in aarch64-sve.md. 436 UNSPEC_IORV ; Used in aarch64-sve.md. 437 UNSPEC_XORV ; Used in aarch64-sve.md. 438 UNSPEC_ANDF ; Used in aarch64-sve.md. 439 UNSPEC_IORF ; Used in aarch64-sve.md. 440 UNSPEC_XORF ; Used in aarch64-sve.md. 441 UNSPEC_SMUL_HIGHPART ; Used in aarch64-sve.md. 442 UNSPEC_UMUL_HIGHPART ; Used in aarch64-sve.md. 443 UNSPEC_COND_ADD ; Used in aarch64-sve.md. 444 UNSPEC_COND_SUB ; Used in aarch64-sve.md. 445 UNSPEC_COND_SMAX ; Used in aarch64-sve.md. 446 UNSPEC_COND_UMAX ; Used in aarch64-sve.md. 447 UNSPEC_COND_SMIN ; Used in aarch64-sve.md. 448 UNSPEC_COND_UMIN ; Used in aarch64-sve.md. 449 UNSPEC_COND_AND ; Used in aarch64-sve.md. 450 UNSPEC_COND_ORR ; Used in aarch64-sve.md. 451 UNSPEC_COND_EOR ; Used in aarch64-sve.md. 452 UNSPEC_COND_LT ; Used in aarch64-sve.md. 453 UNSPEC_COND_LE ; Used in aarch64-sve.md. 454 UNSPEC_COND_EQ ; Used in aarch64-sve.md. 455 UNSPEC_COND_NE ; Used in aarch64-sve.md. 456 UNSPEC_COND_GE ; Used in aarch64-sve.md. 457 UNSPEC_COND_GT ; Used in aarch64-sve.md. 458 UNSPEC_COND_LO ; Used in aarch64-sve.md. 459 UNSPEC_COND_LS ; Used in aarch64-sve.md. 460 UNSPEC_COND_HS ; Used in aarch64-sve.md. 461 UNSPEC_COND_HI ; Used in aarch64-sve.md. 462 UNSPEC_COND_UO ; Used in aarch64-sve.md. 463 UNSPEC_LASTB ; Used in aarch64-sve.md. 464]) 465 466;; ------------------------------------------------------------------ 467;; Unspec enumerations for Atomics. They are here so that they can be 468;; used in the int_iterators for atomic operations. 469;; ------------------------------------------------------------------ 470 471(define_c_enum "unspecv" 472 [ 473 UNSPECV_LX ; Represent a load-exclusive. 474 UNSPECV_SX ; Represent a store-exclusive. 475 UNSPECV_LDA ; Represent an atomic load or load-acquire. 476 UNSPECV_STL ; Represent an atomic store or store-release. 477 UNSPECV_ATOMIC_CMPSW ; Represent an atomic compare swap. 478 UNSPECV_ATOMIC_EXCHG ; Represent an atomic exchange. 479 UNSPECV_ATOMIC_CAS ; Represent an atomic CAS. 480 UNSPECV_ATOMIC_SWP ; Represent an atomic SWP. 481 UNSPECV_ATOMIC_OP ; Represent an atomic operation. 482 UNSPECV_ATOMIC_LDOP ; Represent an atomic load-operation 483 UNSPECV_ATOMIC_LDOP_OR ; Represent an atomic load-or 484 UNSPECV_ATOMIC_LDOP_BIC ; Represent an atomic load-bic 485 UNSPECV_ATOMIC_LDOP_XOR ; Represent an atomic load-xor 486 UNSPECV_ATOMIC_LDOP_PLUS ; Represent an atomic load-add 487]) 488 489;; ------------------------------------------------------------------- 490;; Mode attributes 491;; ------------------------------------------------------------------- 492 493;; In GPI templates, a string like "%<w>0" will expand to "%w0" in the 494;; 32-bit version and "%x0" in the 64-bit version. 495(define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")]) 496 497;; The size of access, in bytes. 498(define_mode_attr ldst_sz [(SI "4") (DI "8")]) 499;; Likewise for load/store pair. 500(define_mode_attr ldpstp_sz [(SI "8") (DI "16")]) 501 502;; For inequal width int to float conversion 503(define_mode_attr w1 [(HF "w") (SF "w") (DF "x")]) 504(define_mode_attr w2 [(HF "x") (SF "x") (DF "w")]) 505 506;; For width of fp registers in fcvt instruction 507(define_mode_attr fpw [(DI "s") (SI "d")]) 508 509(define_mode_attr short_mask [(HI "65535") (QI "255")]) 510 511;; For constraints used in scalar immediate vector moves 512(define_mode_attr hq [(HI "h") (QI "q")]) 513 514;; For doubling width of an integer mode 515(define_mode_attr DWI [(QI "HI") (HI "SI") (SI "DI") (DI "TI")]) 516 517(define_mode_attr fcvt_change_mode [(SI "df") (DI "sf")]) 518 519(define_mode_attr FCVT_CHANGE_MODE [(SI "DF") (DI "SF")]) 520 521;; For scalar usage of vector/FP registers 522(define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d") 523 (HF "h") (SF "s") (DF "d") 524 (V8QI "") (V16QI "") 525 (V4HI "") (V8HI "") 526 (V2SI "") (V4SI "") 527 (V2DI "") (V2SF "") 528 (V4SF "") (V4HF "") 529 (V8HF "") (V2DF "")]) 530 531;; For scalar usage of vector/FP registers, narrowing 532(define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s") 533 (V8QI "") (V16QI "") 534 (V4HI "") (V8HI "") 535 (V2SI "") (V4SI "") 536 (V2DI "") (V2SF "") 537 (V4SF "") (V2DF "")]) 538 539;; For scalar usage of vector/FP registers, widening 540(define_mode_attr vw2 [(DI "") (QI "h") (HI "s") (SI "d") 541 (V8QI "") (V16QI "") 542 (V4HI "") (V8HI "") 543 (V2SI "") (V4SI "") 544 (V2DI "") (V2SF "") 545 (V4SF "") (V2DF "")]) 546 547;; Register Type Name and Vector Arrangement Specifier for when 548;; we are doing scalar for DI and SIMD for SI (ignoring all but 549;; lane 0). 550(define_mode_attr rtn [(DI "d") (SI "")]) 551(define_mode_attr vas [(DI "") (SI ".2s")]) 552 553;; Map a vector to the number of units in it, if the size of the mode 554;; is constant. 555(define_mode_attr nunits [(V8QI "8") (V16QI "16") 556 (V4HI "4") (V8HI "8") 557 (V2SI "2") (V4SI "4") 558 (V2DI "2") 559 (V4HF "4") (V8HF "8") 560 (V2SF "2") (V4SF "4") 561 (V1DF "1") (V2DF "2") 562 (DI "1") (DF "1")]) 563 564;; Map a mode to the number of bits in it, if the size of the mode 565;; is constant. 566(define_mode_attr bitsize [(V8QI "64") (V16QI "128") 567 (V4HI "64") (V8HI "128") 568 (V2SI "64") (V4SI "128") 569 (V2DI "128")]) 570 571;; Map a floating point or integer mode to the appropriate register name prefix 572(define_mode_attr s [(HF "h") (SF "s") (DF "d") (SI "s") (DI "d")]) 573 574;; Give the length suffix letter for a sign- or zero-extension. 575(define_mode_attr size [(QI "b") (HI "h") (SI "w")]) 576 577;; Give the number of bits in the mode 578(define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")]) 579 580;; Give the ordinal of the MSB in the mode 581(define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63") 582 (HF "#15") (SF "#31") (DF "#63")]) 583 584;; Attribute to describe constants acceptable in logical operations 585(define_mode_attr lconst [(SI "K") (DI "L")]) 586 587;; Attribute to describe constants acceptable in logical and operations 588(define_mode_attr lconst2 [(SI "UsO") (DI "UsP")]) 589 590;; Map a mode to a specific constraint character. 591(define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")]) 592 593;; Map modes to Usg and Usj constraints for SISD right shifts 594(define_mode_attr cmode_simd [(SI "g") (DI "j")]) 595 596(define_mode_attr Vtype [(V8QI "8b") (V16QI "16b") 597 (V4HI "4h") (V8HI "8h") 598 (V2SI "2s") (V4SI "4s") 599 (DI "1d") (DF "1d") 600 (V2DI "2d") (V2SF "2s") 601 (V4SF "4s") (V2DF "2d") 602 (V4HF "4h") (V8HF "8h")]) 603 604(define_mode_attr Vrevsuff [(V4HI "16") (V8HI "16") (V2SI "32") 605 (V4SI "32") (V2DI "64")]) 606 607(define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b") 608 (V4HI ".4h") (V8HI ".8h") 609 (V2SI ".2s") (V4SI ".4s") 610 (V2DI ".2d") (V4HF ".4h") 611 (V8HF ".8h") (V2SF ".2s") 612 (V4SF ".4s") (V2DF ".2d") 613 (DI "") (SI "") 614 (HI "") (QI "") 615 (TI "") (HF "") 616 (SF "") (DF "")]) 617 618;; Register suffix narrowed modes for VQN. 619(define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h") 620 (V2DI ".2s") 621 (DI "") (SI "") 622 (HI "")]) 623 624;; Mode-to-individual element type mapping. 625(define_mode_attr Vetype [(V8QI "b") (V16QI "b") (VNx16QI "b") (VNx16BI "b") 626 (V4HI "h") (V8HI "h") (VNx8HI "h") (VNx8BI "h") 627 (V2SI "s") (V4SI "s") (VNx4SI "s") (VNx4BI "s") 628 (V2DI "d") (VNx2DI "d") (VNx2BI "d") 629 (V4HF "h") (V8HF "h") (VNx8HF "h") 630 (V2SF "s") (V4SF "s") (VNx4SF "s") 631 (V2DF "d") (VNx2DF "d") 632 (HF "h") 633 (SF "s") (DF "d") 634 (QI "b") (HI "h") 635 (SI "s") (DI "d")]) 636 637;; Equivalent of "size" for a vector element. 638(define_mode_attr Vesize [(VNx16QI "b") 639 (VNx8HI "h") (VNx8HF "h") 640 (VNx4SI "w") (VNx4SF "w") 641 (VNx2DI "d") (VNx2DF "d") 642 (VNx32QI "b") (VNx48QI "b") (VNx64QI "b") 643 (VNx16HI "h") (VNx24HI "h") (VNx32HI "h") 644 (VNx16HF "h") (VNx24HF "h") (VNx32HF "h") 645 (VNx8SI "w") (VNx12SI "w") (VNx16SI "w") 646 (VNx8SF "w") (VNx12SF "w") (VNx16SF "w") 647 (VNx4DI "d") (VNx6DI "d") (VNx8DI "d") 648 (VNx4DF "d") (VNx6DF "d") (VNx8DF "d")]) 649 650;; Vetype is used everywhere in scheduling type and assembly output, 651;; sometimes they are not the same, for example HF modes on some 652;; instructions. stype is defined to represent scheduling type 653;; more accurately. 654(define_mode_attr stype [(V8QI "b") (V16QI "b") (V4HI "s") (V8HI "s") 655 (V2SI "s") (V4SI "s") (V2DI "d") (V4HF "s") 656 (V8HF "s") (V2SF "s") (V4SF "s") (V2DF "d") 657 (HF "s") (SF "s") (DF "d") (QI "b") (HI "s") 658 (SI "s") (DI "d")]) 659 660;; Mode-to-bitwise operation type mapping. 661(define_mode_attr Vbtype [(V8QI "8b") (V16QI "16b") 662 (V4HI "8b") (V8HI "16b") 663 (V2SI "8b") (V4SI "16b") 664 (V2DI "16b") (V4HF "8b") 665 (V8HF "16b") (V2SF "8b") 666 (V4SF "16b") (V2DF "16b") 667 (DI "8b") (DF "8b") 668 (SI "8b") (SF "8b")]) 669 670;; Define element mode for each vector mode. 671(define_mode_attr VEL [(V8QI "QI") (V16QI "QI") (VNx16QI "QI") 672 (V4HI "HI") (V8HI "HI") (VNx8HI "HI") 673 (V2SI "SI") (V4SI "SI") (VNx4SI "SI") 674 (DI "DI") (V2DI "DI") (VNx2DI "DI") 675 (V4HF "HF") (V8HF "HF") (VNx8HF "HF") 676 (V2SF "SF") (V4SF "SF") (VNx4SF "SF") 677 (DF "DF") (V2DF "DF") (VNx2DF "DF") 678 (SI "SI") (HI "HI") 679 (QI "QI")]) 680 681;; Define element mode for each vector mode (lower case). 682(define_mode_attr Vel [(V8QI "qi") (V16QI "qi") (VNx16QI "qi") 683 (V4HI "hi") (V8HI "hi") (VNx8HI "hi") 684 (V2SI "si") (V4SI "si") (VNx4SI "si") 685 (DI "di") (V2DI "di") (VNx2DI "di") 686 (V4HF "hf") (V8HF "hf") (VNx8HF "hf") 687 (V2SF "sf") (V4SF "sf") (VNx4SF "sf") 688 (V2DF "df") (DF "df") (VNx2DF "df") 689 (SI "si") (HI "hi") 690 (QI "qi")]) 691 692;; Element mode with floating-point values replaced by like-sized integers. 693(define_mode_attr VEL_INT [(VNx16QI "QI") 694 (VNx8HI "HI") (VNx8HF "HI") 695 (VNx4SI "SI") (VNx4SF "SI") 696 (VNx2DI "DI") (VNx2DF "DI")]) 697 698;; Gives the mode of the 128-bit lowpart of an SVE vector. 699(define_mode_attr V128 [(VNx16QI "V16QI") 700 (VNx8HI "V8HI") (VNx8HF "V8HF") 701 (VNx4SI "V4SI") (VNx4SF "V4SF") 702 (VNx2DI "V2DI") (VNx2DF "V2DF")]) 703 704;; ...and again in lower case. 705(define_mode_attr v128 [(VNx16QI "v16qi") 706 (VNx8HI "v8hi") (VNx8HF "v8hf") 707 (VNx4SI "v4si") (VNx4SF "v4sf") 708 (VNx2DI "v2di") (VNx2DF "v2df")]) 709 710;; 64-bit container modes the inner or scalar source mode. 711(define_mode_attr VCOND [(HI "V4HI") (SI "V2SI") 712 (V4HI "V4HI") (V8HI "V4HI") 713 (V2SI "V2SI") (V4SI "V2SI") 714 (DI "DI") (V2DI "DI") 715 (V2SF "V2SF") (V4SF "V2SF") 716 (V2DF "DF")]) 717 718;; 128-bit container modes the inner or scalar source mode. 719(define_mode_attr VCONQ [(V8QI "V16QI") (V16QI "V16QI") 720 (V4HI "V8HI") (V8HI "V8HI") 721 (V2SI "V4SI") (V4SI "V4SI") 722 (DI "V2DI") (V2DI "V2DI") 723 (V4HF "V8HF") (V8HF "V8HF") 724 (V2SF "V2SF") (V4SF "V4SF") 725 (V2DF "V2DF") (SI "V4SI") 726 (HI "V8HI") (QI "V16QI")]) 727 728;; Half modes of all vector modes. 729(define_mode_attr VHALF [(V8QI "V4QI") (V16QI "V8QI") 730 (V4HI "V2HI") (V8HI "V4HI") 731 (V2SI "SI") (V4SI "V2SI") 732 (V2DI "DI") (V2SF "SF") 733 (V4SF "V2SF") (V4HF "V2HF") 734 (V8HF "V4HF") (V2DF "DF")]) 735 736;; Half modes of all vector modes, in lower-case. 737(define_mode_attr Vhalf [(V8QI "v4qi") (V16QI "v8qi") 738 (V4HI "v2hi") (V8HI "v4hi") 739 (V2SI "si") (V4SI "v2si") 740 (V2DI "di") (V2SF "sf") 741 (V4SF "v2sf") (V2DF "df")]) 742 743;; Double modes of vector modes. 744(define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI") 745 (V4HF "V8HF") 746 (V2SI "V4SI") (V2SF "V4SF") 747 (SI "V2SI") (DI "V2DI") 748 (DF "V2DF")]) 749 750;; Register suffix for double-length mode. 751(define_mode_attr Vdtype [(V4HF "8h") (V2SF "4s")]) 752 753;; Double modes of vector modes (lower case). 754(define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi") 755 (V4HF "v8hf") 756 (V2SI "v4si") (V2SF "v4sf") 757 (SI "v2si") (DI "v2di") 758 (DF "v2df")]) 759 760;; Modes with double-width elements. 761(define_mode_attr VDBLW [(V8QI "V4HI") (V16QI "V8HI") 762 (V4HI "V2SI") (V8HI "V4SI") 763 (V2SI "DI") (V4SI "V2DI")]) 764 765;; Narrowed modes for VDN. 766(define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI") 767 (DI "V2SI")]) 768 769;; Narrowed double-modes for VQN (Used for XTN). 770(define_mode_attr VNARROWQ [(V8HI "V8QI") (V4SI "V4HI") 771 (V2DI "V2SI") 772 (DI "SI") (SI "HI") 773 (HI "QI")]) 774 775;; Narrowed quad-modes for VQN (Used for XTN2). 776(define_mode_attr VNARROWQ2 [(V8HI "V16QI") (V4SI "V8HI") 777 (V2DI "V4SI")]) 778 779;; Register suffix narrowed modes for VQN. 780(define_mode_attr Vntype [(V8HI "8b") (V4SI "4h") 781 (V2DI "2s")]) 782 783;; Register suffix narrowed modes for VQN. 784(define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h") 785 (V2DI "4s")]) 786 787;; Widened modes of vector modes. 788(define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI") 789 (V2SI "V2DI") (V16QI "V8HI") 790 (V8HI "V4SI") (V4SI "V2DI") 791 (HI "SI") (SI "DI") 792 (V8HF "V4SF") (V4SF "V2DF") 793 (V4HF "V4SF") (V2SF "V2DF") 794 (VNx8HF "VNx4SF") (VNx4SF "VNx2DF") 795 (VNx16QI "VNx8HI") (VNx8HI "VNx4SI") 796 (VNx4SI "VNx2DI") 797 (VNx16BI "VNx8BI") (VNx8BI "VNx4BI") 798 (VNx4BI "VNx2BI")]) 799 800;; Predicate mode associated with VWIDE. 801(define_mode_attr VWIDE_PRED [(VNx8HF "VNx4BI") (VNx4SF "VNx2BI")]) 802 803;; Widened modes of vector modes, lowercase 804(define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf") 805 (VNx16QI "vnx8hi") (VNx8HI "vnx4si") 806 (VNx4SI "vnx2di") 807 (VNx8HF "vnx4sf") (VNx4SF "vnx2df") 808 (VNx16BI "vnx8bi") (VNx8BI "vnx4bi") 809 (VNx4BI "vnx2bi")]) 810 811;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF. 812(define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s") 813 (V2SI "2d") (V16QI "8h") 814 (V8HI "4s") (V4SI "2d") 815 (V8HF "4s") (V4SF "2d")]) 816 817;; SVE vector after widening 818(define_mode_attr Vewtype [(VNx16QI "h") 819 (VNx8HI "s") (VNx8HF "s") 820 (VNx4SI "d") (VNx4SF "d")]) 821 822;; Widened mode register suffixes for VDW/VQW. 823(define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s") 824 (V2SI ".2d") (V16QI ".8h") 825 (V8HI ".4s") (V4SI ".2d") 826 (V4HF ".4s") (V2SF ".2d") 827 (SI "") (HI "")]) 828 829;; Lower part register suffixes for VQW/VQ_HSF. 830(define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h") 831 (V4SI "2s") (V8HF "4h") 832 (V4SF "2s")]) 833 834;; Define corresponding core/FP element mode for each vector mode. 835(define_mode_attr vw [(V8QI "w") (V16QI "w") (VNx16QI "w") 836 (V4HI "w") (V8HI "w") (VNx8HI "w") 837 (V2SI "w") (V4SI "w") (VNx4SI "w") 838 (DI "x") (V2DI "x") (VNx2DI "x") 839 (VNx8HF "h") 840 (V2SF "s") (V4SF "s") (VNx4SF "s") 841 (V2DF "d") (VNx2DF "d")]) 842 843;; Corresponding core element mode for each vector mode. This is a 844;; variation on <vw> mapping FP modes to GP regs. 845(define_mode_attr vwcore [(V8QI "w") (V16QI "w") (VNx16QI "w") 846 (V4HI "w") (V8HI "w") (VNx8HI "w") 847 (V2SI "w") (V4SI "w") (VNx4SI "w") 848 (DI "x") (V2DI "x") (VNx2DI "x") 849 (V4HF "w") (V8HF "w") (VNx8HF "w") 850 (V2SF "w") (V4SF "w") (VNx4SF "w") 851 (V2DF "x") (VNx2DF "x")]) 852 853;; Double vector types for ALLX. 854(define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")]) 855 856;; Mode with floating-point values replaced by like-sized integers. 857(define_mode_attr V_INT_EQUIV [(V8QI "V8QI") (V16QI "V16QI") 858 (V4HI "V4HI") (V8HI "V8HI") 859 (V2SI "V2SI") (V4SI "V4SI") 860 (DI "DI") (V2DI "V2DI") 861 (V4HF "V4HI") (V8HF "V8HI") 862 (V2SF "V2SI") (V4SF "V4SI") 863 (DF "DI") (V2DF "V2DI") 864 (SF "SI") (HF "HI") 865 (VNx16QI "VNx16QI") 866 (VNx8HI "VNx8HI") (VNx8HF "VNx8HI") 867 (VNx4SI "VNx4SI") (VNx4SF "VNx4SI") 868 (VNx2DI "VNx2DI") (VNx2DF "VNx2DI") 869]) 870 871;; Lower case mode with floating-point values replaced by like-sized integers. 872(define_mode_attr v_int_equiv [(V8QI "v8qi") (V16QI "v16qi") 873 (V4HI "v4hi") (V8HI "v8hi") 874 (V2SI "v2si") (V4SI "v4si") 875 (DI "di") (V2DI "v2di") 876 (V4HF "v4hi") (V8HF "v8hi") 877 (V2SF "v2si") (V4SF "v4si") 878 (DF "di") (V2DF "v2di") 879 (SF "si") 880 (VNx16QI "vnx16qi") 881 (VNx8HI "vnx8hi") (VNx8HF "vnx8hi") 882 (VNx4SI "vnx4si") (VNx4SF "vnx4si") 883 (VNx2DI "vnx2di") (VNx2DF "vnx2di") 884]) 885 886;; Floating-point equivalent of selected modes. 887(define_mode_attr V_FP_EQUIV [(VNx4SI "VNx4SF") (VNx4SF "VNx4SF") 888 (VNx2DI "VNx2DF") (VNx2DF "VNx2DF")]) 889(define_mode_attr v_fp_equiv [(VNx4SI "vnx4sf") (VNx4SF "vnx4sf") 890 (VNx2DI "vnx2df") (VNx2DF "vnx2df")]) 891 892;; Mode for vector conditional operations where the comparison has 893;; different type from the lhs. 894(define_mode_attr V_cmp_mixed [(V2SI "V2SF") (V4SI "V4SF") 895 (V2DI "V2DF") (V2SF "V2SI") 896 (V4SF "V4SI") (V2DF "V2DI")]) 897 898(define_mode_attr v_cmp_mixed [(V2SI "v2sf") (V4SI "v4sf") 899 (V2DI "v2df") (V2SF "v2si") 900 (V4SF "v4si") (V2DF "v2di")]) 901 902;; Lower case element modes (as used in shift immediate patterns). 903(define_mode_attr ve_mode [(V8QI "qi") (V16QI "qi") 904 (V4HI "hi") (V8HI "hi") 905 (V2SI "si") (V4SI "si") 906 (DI "di") (V2DI "di") 907 (QI "qi") (HI "hi") 908 (SI "si")]) 909 910;; Vm for lane instructions is restricted to FP_LO_REGS. 911(define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x") 912 (V2SI "w") (V4SI "w") (SI "w")]) 913 914(define_mode_attr Vendreg [(OI "T") (CI "U") (XI "V")]) 915 916;; This is both the number of Q-Registers needed to hold the corresponding 917;; opaque large integer mode, and the number of elements touched by the 918;; ld..._lane and st..._lane operations. 919(define_mode_attr nregs [(OI "2") (CI "3") (XI "4")]) 920 921;; Mode for atomic operation suffixes 922(define_mode_attr atomic_sfx 923 [(QI "b") (HI "h") (SI "") (DI "")]) 924 925(define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si") 926 (V2DI "v2df") (V4SI "v4sf") (V2SI "v2sf") 927 (SF "si") (DF "di") (SI "sf") (DI "df") 928 (V4HF "v4hi") (V8HF "v8hi") (V4HI "v4hf") 929 (V8HI "v8hf") (HF "hi") (HI "hf")]) 930(define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI") 931 (V2DI "V2DF") (V4SI "V4SF") (V2SI "V2SF") 932 (SF "SI") (DF "DI") (SI "SF") (DI "DF") 933 (V4HF "V4HI") (V8HF "V8HI") (V4HI "V4HF") 934 (V8HI "V8HF") (HF "HI") (HI "HF")]) 935 936 937;; for the inequal width integer to fp conversions 938(define_mode_attr fcvt_iesize [(HF "di") (SF "di") (DF "si")]) 939(define_mode_attr FCVT_IESIZE [(HF "DI") (SF "DI") (DF "SI")]) 940 941(define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI") 942 (V4HI "V8HI") (V8HI "V4HI") 943 (V2SI "V4SI") (V4SI "V2SI") 944 (DI "V2DI") (V2DI "DI") 945 (V2SF "V4SF") (V4SF "V2SF") 946 (V4HF "V8HF") (V8HF "V4HF") 947 (DF "V2DF") (V2DF "DF")]) 948 949(define_mode_attr vswap_width_name [(V8QI "to_128") (V16QI "to_64") 950 (V4HI "to_128") (V8HI "to_64") 951 (V2SI "to_128") (V4SI "to_64") 952 (DI "to_128") (V2DI "to_64") 953 (V4HF "to_128") (V8HF "to_64") 954 (V2SF "to_128") (V4SF "to_64") 955 (DF "to_128") (V2DF "to_64")]) 956 957;; For certain vector-by-element multiplication instructions we must 958;; constrain the 16-bit cases to use only V0-V15. This is covered by 959;; the 'x' constraint. All other modes may use the 'w' constraint. 960(define_mode_attr h_con [(V2SI "w") (V4SI "w") 961 (V4HI "x") (V8HI "x") 962 (V4HF "x") (V8HF "x") 963 (V2SF "w") (V4SF "w") 964 (V2DF "w") (DF "w")]) 965 966;; Defined to 'f' for types whose element type is a float type. 967(define_mode_attr f [(V8QI "") (V16QI "") 968 (V4HI "") (V8HI "") 969 (V2SI "") (V4SI "") 970 (DI "") (V2DI "") 971 (V4HF "f") (V8HF "f") 972 (V2SF "f") (V4SF "f") 973 (V2DF "f") (DF "f")]) 974 975;; Defined to '_fp' for types whose element type is a float type. 976(define_mode_attr fp [(V8QI "") (V16QI "") 977 (V4HI "") (V8HI "") 978 (V2SI "") (V4SI "") 979 (DI "") (V2DI "") 980 (V4HF "_fp") (V8HF "_fp") 981 (V2SF "_fp") (V4SF "_fp") 982 (V2DF "_fp") (DF "_fp") 983 (SF "_fp")]) 984 985;; Defined to '_q' for 128-bit types. 986(define_mode_attr q [(V8QI "") (V16QI "_q") 987 (V4HI "") (V8HI "_q") 988 (V2SI "") (V4SI "_q") 989 (DI "") (V2DI "_q") 990 (V4HF "") (V8HF "_q") 991 (V2SF "") (V4SF "_q") 992 (V2DF "_q") 993 (QI "") (HI "") (SI "") (DI "") (HF "") (SF "") (DF "")]) 994 995(define_mode_attr vp [(V8QI "v") (V16QI "v") 996 (V4HI "v") (V8HI "v") 997 (V2SI "p") (V4SI "v") 998 (V2DI "p") (V2DF "p") 999 (V2SF "p") (V4SF "v") 1000 (V4HF "v") (V8HF "v")]) 1001 1002(define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")]) 1003(define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")]) 1004 1005 1006;; Register suffix for DOTPROD input types from the return type. 1007(define_mode_attr Vdottype [(V2SI "8b") (V4SI "16b")]) 1008 1009;; Sum of lengths of instructions needed to move vector registers of a mode. 1010(define_mode_attr insn_count [(OI "8") (CI "12") (XI "16")]) 1011 1012;; -fpic small model GOT reloc modifers: gotpage_lo15/lo14 for ILP64/32. 1013;; No need of iterator for -fPIC as it use got_lo12 for both modes. 1014(define_mode_attr got_modifier [(SI "gotpage_lo14") (DI "gotpage_lo15")]) 1015 1016;; Width of 2nd and 3rd arguments to fp16 vector multiply add/sub 1017(define_mode_attr VFMLA_W [(V2SF "V4HF") (V4SF "V8HF")]) 1018 1019(define_mode_attr VFMLA_SEL_W [(V2SF "V2HF") (V4SF "V4HF")]) 1020 1021(define_mode_attr f16quad [(V2SF "") (V4SF "q")]) 1022 1023(define_code_attr f16mac [(plus "a") (minus "s")]) 1024 1025;; The number of subvectors in an SVE_STRUCT. 1026(define_mode_attr vector_count [(VNx32QI "2") (VNx16HI "2") 1027 (VNx8SI "2") (VNx4DI "2") 1028 (VNx16HF "2") (VNx8SF "2") (VNx4DF "2") 1029 (VNx48QI "3") (VNx24HI "3") 1030 (VNx12SI "3") (VNx6DI "3") 1031 (VNx24HF "3") (VNx12SF "3") (VNx6DF "3") 1032 (VNx64QI "4") (VNx32HI "4") 1033 (VNx16SI "4") (VNx8DI "4") 1034 (VNx32HF "4") (VNx16SF "4") (VNx8DF "4")]) 1035 1036;; The number of instruction bytes needed for an SVE_STRUCT move. This is 1037;; equal to vector_count * 4. 1038(define_mode_attr insn_length [(VNx32QI "8") (VNx16HI "8") 1039 (VNx8SI "8") (VNx4DI "8") 1040 (VNx16HF "8") (VNx8SF "8") (VNx4DF "8") 1041 (VNx48QI "12") (VNx24HI "12") 1042 (VNx12SI "12") (VNx6DI "12") 1043 (VNx24HF "12") (VNx12SF "12") (VNx6DF "12") 1044 (VNx64QI "16") (VNx32HI "16") 1045 (VNx16SI "16") (VNx8DI "16") 1046 (VNx32HF "16") (VNx16SF "16") (VNx8DF "16")]) 1047 1048;; The type of a subvector in an SVE_STRUCT. 1049(define_mode_attr VSINGLE [(VNx32QI "VNx16QI") 1050 (VNx16HI "VNx8HI") (VNx16HF "VNx8HF") 1051 (VNx8SI "VNx4SI") (VNx8SF "VNx4SF") 1052 (VNx4DI "VNx2DI") (VNx4DF "VNx2DF") 1053 (VNx48QI "VNx16QI") 1054 (VNx24HI "VNx8HI") (VNx24HF "VNx8HF") 1055 (VNx12SI "VNx4SI") (VNx12SF "VNx4SF") 1056 (VNx6DI "VNx2DI") (VNx6DF "VNx2DF") 1057 (VNx64QI "VNx16QI") 1058 (VNx32HI "VNx8HI") (VNx32HF "VNx8HF") 1059 (VNx16SI "VNx4SI") (VNx16SF "VNx4SF") 1060 (VNx8DI "VNx2DI") (VNx8DF "VNx2DF")]) 1061 1062;; ...and again in lower case. 1063(define_mode_attr vsingle [(VNx32QI "vnx16qi") 1064 (VNx16HI "vnx8hi") (VNx16HF "vnx8hf") 1065 (VNx8SI "vnx4si") (VNx8SF "vnx4sf") 1066 (VNx4DI "vnx2di") (VNx4DF "vnx2df") 1067 (VNx48QI "vnx16qi") 1068 (VNx24HI "vnx8hi") (VNx24HF "vnx8hf") 1069 (VNx12SI "vnx4si") (VNx12SF "vnx4sf") 1070 (VNx6DI "vnx2di") (VNx6DF "vnx2df") 1071 (VNx64QI "vnx16qi") 1072 (VNx32HI "vnx8hi") (VNx32HF "vnx8hf") 1073 (VNx16SI "vnx4si") (VNx16SF "vnx4sf") 1074 (VNx8DI "vnx2di") (VNx8DF "vnx2df")]) 1075 1076;; The predicate mode associated with an SVE data mode. For structure modes 1077;; this is equivalent to the <VPRED> of the subvector mode. 1078(define_mode_attr VPRED [(VNx16QI "VNx16BI") 1079 (VNx8HI "VNx8BI") (VNx8HF "VNx8BI") 1080 (VNx4SI "VNx4BI") (VNx4SF "VNx4BI") 1081 (VNx2DI "VNx2BI") (VNx2DF "VNx2BI") 1082 (VNx32QI "VNx16BI") 1083 (VNx16HI "VNx8BI") (VNx16HF "VNx8BI") 1084 (VNx8SI "VNx4BI") (VNx8SF "VNx4BI") 1085 (VNx4DI "VNx2BI") (VNx4DF "VNx2BI") 1086 (VNx48QI "VNx16BI") 1087 (VNx24HI "VNx8BI") (VNx24HF "VNx8BI") 1088 (VNx12SI "VNx4BI") (VNx12SF "VNx4BI") 1089 (VNx6DI "VNx2BI") (VNx6DF "VNx2BI") 1090 (VNx64QI "VNx16BI") 1091 (VNx32HI "VNx8BI") (VNx32HF "VNx8BI") 1092 (VNx16SI "VNx4BI") (VNx16SF "VNx4BI") 1093 (VNx8DI "VNx2BI") (VNx8DF "VNx2BI")]) 1094 1095;; ...and again in lower case. 1096(define_mode_attr vpred [(VNx16QI "vnx16bi") 1097 (VNx8HI "vnx8bi") (VNx8HF "vnx8bi") 1098 (VNx4SI "vnx4bi") (VNx4SF "vnx4bi") 1099 (VNx2DI "vnx2bi") (VNx2DF "vnx2bi") 1100 (VNx32QI "vnx16bi") 1101 (VNx16HI "vnx8bi") (VNx16HF "vnx8bi") 1102 (VNx8SI "vnx4bi") (VNx8SF "vnx4bi") 1103 (VNx4DI "vnx2bi") (VNx4DF "vnx2bi") 1104 (VNx48QI "vnx16bi") 1105 (VNx24HI "vnx8bi") (VNx24HF "vnx8bi") 1106 (VNx12SI "vnx4bi") (VNx12SF "vnx4bi") 1107 (VNx6DI "vnx2bi") (VNx6DF "vnx2bi") 1108 (VNx64QI "vnx16bi") 1109 (VNx32HI "vnx8bi") (VNx32HF "vnx4bi") 1110 (VNx16SI "vnx4bi") (VNx16SF "vnx4bi") 1111 (VNx8DI "vnx2bi") (VNx8DF "vnx2bi")]) 1112 1113;; ------------------------------------------------------------------- 1114;; Code Iterators 1115;; ------------------------------------------------------------------- 1116 1117;; This code iterator allows the various shifts supported on the core 1118(define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert]) 1119 1120;; This code iterator allows the shifts supported in arithmetic instructions 1121(define_code_iterator ASHIFT [ashift ashiftrt lshiftrt]) 1122 1123;; Code iterator for logical operations 1124(define_code_iterator LOGICAL [and ior xor]) 1125 1126;; LOGICAL without AND. 1127(define_code_iterator LOGICAL_OR [ior xor]) 1128 1129;; Code iterator for logical operations whose :nlogical works on SIMD registers. 1130(define_code_iterator NLOGICAL [and ior]) 1131 1132;; Code iterator for unary negate and bitwise complement. 1133(define_code_iterator NEG_NOT [neg not]) 1134 1135;; Code iterator for sign/zero extension 1136(define_code_iterator ANY_EXTEND [sign_extend zero_extend]) 1137 1138;; All division operations (signed/unsigned) 1139(define_code_iterator ANY_DIV [div udiv]) 1140 1141;; Code iterator for sign/zero extraction 1142(define_code_iterator ANY_EXTRACT [sign_extract zero_extract]) 1143 1144;; Code iterator for equality comparisons 1145(define_code_iterator EQL [eq ne]) 1146 1147;; Code iterator for less-than and greater/equal-to 1148(define_code_iterator LTGE [lt ge]) 1149 1150;; Iterator for __sync_<op> operations that where the operation can be 1151;; represented directly RTL. This is all of the sync operations bar 1152;; nand. 1153(define_code_iterator atomic_op [plus minus ior xor and]) 1154 1155;; Iterator for integer conversions 1156(define_code_iterator FIXUORS [fix unsigned_fix]) 1157 1158;; Iterator for float conversions 1159(define_code_iterator FLOATUORS [float unsigned_float]) 1160 1161;; Code iterator for variants of vector max and min. 1162(define_code_iterator MAXMIN [smax smin umax umin]) 1163 1164(define_code_iterator FMAXMIN [smax smin]) 1165 1166;; Code iterator for variants of vector max and min. 1167(define_code_iterator ADDSUB [plus minus]) 1168 1169;; Code iterator for variants of vector saturating binary ops. 1170(define_code_iterator BINQOPS [ss_plus us_plus ss_minus us_minus]) 1171 1172;; Code iterator for variants of vector saturating unary ops. 1173(define_code_iterator UNQOPS [ss_neg ss_abs]) 1174 1175;; Code iterator for signed variants of vector saturating binary ops. 1176(define_code_iterator SBINQOPS [ss_plus ss_minus]) 1177 1178;; Comparison operators for <F>CM. 1179(define_code_iterator COMPARISONS [lt le eq ge gt]) 1180 1181;; Unsigned comparison operators. 1182(define_code_iterator UCOMPARISONS [ltu leu geu gtu]) 1183 1184;; Unsigned comparison operators. 1185(define_code_iterator FAC_COMPARISONS [lt le ge gt]) 1186 1187;; SVE integer unary operations. 1188(define_code_iterator SVE_INT_UNARY [neg not popcount]) 1189 1190;; SVE floating-point unary operations. 1191(define_code_iterator SVE_FP_UNARY [neg abs sqrt]) 1192 1193;; ------------------------------------------------------------------- 1194;; Code Attributes 1195;; ------------------------------------------------------------------- 1196;; Map rtl objects to optab names 1197(define_code_attr optab [(ashift "ashl") 1198 (ashiftrt "ashr") 1199 (lshiftrt "lshr") 1200 (rotatert "rotr") 1201 (sign_extend "extend") 1202 (zero_extend "zero_extend") 1203 (sign_extract "extv") 1204 (zero_extract "extzv") 1205 (fix "fix") 1206 (unsigned_fix "fixuns") 1207 (float "float") 1208 (unsigned_float "floatuns") 1209 (popcount "popcount") 1210 (and "and") 1211 (ior "ior") 1212 (xor "xor") 1213 (not "one_cmpl") 1214 (neg "neg") 1215 (plus "add") 1216 (minus "sub") 1217 (ss_plus "qadd") 1218 (us_plus "qadd") 1219 (ss_minus "qsub") 1220 (us_minus "qsub") 1221 (ss_neg "qneg") 1222 (ss_abs "qabs") 1223 (smin "smin") 1224 (smax "smax") 1225 (umin "umin") 1226 (umax "umax") 1227 (eq "eq") 1228 (ne "ne") 1229 (lt "lt") 1230 (ge "ge") 1231 (le "le") 1232 (gt "gt") 1233 (ltu "ltu") 1234 (leu "leu") 1235 (geu "geu") 1236 (gtu "gtu") 1237 (abs "abs") 1238 (sqrt "sqrt")]) 1239 1240;; For comparison operators we use the FCM* and CM* instructions. 1241;; As there are no CMLE or CMLT instructions which act on 3 vector 1242;; operands, we must use CMGE or CMGT and swap the order of the 1243;; source operands. 1244 1245(define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt") 1246 (ltu "hi") (leu "hs") (geu "hs") (gtu "hi")]) 1247(define_code_attr cmp_1 [(lt "2") (le "2") (eq "1") (ge "1") (gt "1") 1248 (ltu "2") (leu "2") (geu "1") (gtu "1")]) 1249(define_code_attr cmp_2 [(lt "1") (le "1") (eq "2") (ge "2") (gt "2") 1250 (ltu "1") (leu "1") (geu "2") (gtu "2")]) 1251 1252(define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT") 1253 (ltu "LTU") (leu "LEU") (ne "NE") (geu "GEU") 1254 (gtu "GTU")]) 1255 1256(define_code_attr fix_trunc_optab [(fix "fix_trunc") 1257 (unsigned_fix "fixuns_trunc")]) 1258 1259;; Optab prefix for sign/zero-extending operations 1260(define_code_attr su_optab [(sign_extend "") (zero_extend "u") 1261 (div "") (udiv "u") 1262 (fix "") (unsigned_fix "u") 1263 (float "s") (unsigned_float "u") 1264 (ss_plus "s") (us_plus "u") 1265 (ss_minus "s") (us_minus "u")]) 1266 1267;; Similar for the instruction mnemonics 1268(define_code_attr shift [(ashift "lsl") (ashiftrt "asr") 1269 (lshiftrt "lsr") (rotatert "ror")]) 1270 1271;; Map shift operators onto underlying bit-field instructions 1272(define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx") 1273 (lshiftrt "ubfx") (rotatert "extr")]) 1274 1275;; Logical operator instruction mnemonics 1276(define_code_attr logical [(and "and") (ior "orr") (xor "eor")]) 1277 1278;; Operation names for negate and bitwise complement. 1279(define_code_attr neg_not_op [(neg "neg") (not "not")]) 1280 1281;; Similar, but when the second operand is inverted. 1282(define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")]) 1283 1284;; Similar, but when both operands are inverted. 1285(define_code_attr logical_nn [(and "nor") (ior "nand")]) 1286 1287;; Sign- or zero-extending data-op 1288(define_code_attr su [(sign_extend "s") (zero_extend "u") 1289 (sign_extract "s") (zero_extract "u") 1290 (fix "s") (unsigned_fix "u") 1291 (div "s") (udiv "u") 1292 (smax "s") (umax "u") 1293 (smin "s") (umin "u")]) 1294 1295;; Whether a shift is left or right. 1296(define_code_attr lr [(ashift "l") (ashiftrt "r") (lshiftrt "r")]) 1297 1298;; Emit conditional branch instructions. 1299(define_code_attr bcond [(eq "beq") (ne "bne") (lt "bne") (ge "beq")]) 1300 1301;; Emit cbz/cbnz depending on comparison type. 1302(define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")]) 1303 1304;; Emit inverted cbz/cbnz depending on comparison type. 1305(define_code_attr inv_cb [(eq "cbnz") (ne "cbz") (lt "cbz") (ge "cbnz")]) 1306 1307;; Emit tbz/tbnz depending on comparison type. 1308(define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")]) 1309 1310;; Emit inverted tbz/tbnz depending on comparison type. 1311(define_code_attr inv_tb [(eq "tbnz") (ne "tbz") (lt "tbz") (ge "tbnz")]) 1312 1313;; Max/min attributes. 1314(define_code_attr maxmin [(smax "max") 1315 (smin "min") 1316 (umax "max") 1317 (umin "min")]) 1318 1319;; MLA/MLS attributes. 1320(define_code_attr as [(ss_plus "a") (ss_minus "s")]) 1321 1322;; Atomic operations 1323(define_code_attr atomic_optab 1324 [(ior "or") (xor "xor") (and "and") (plus "add") (minus "sub")]) 1325 1326(define_code_attr atomic_op_operand 1327 [(ior "aarch64_logical_operand") 1328 (xor "aarch64_logical_operand") 1329 (and "aarch64_logical_operand") 1330 (plus "aarch64_plus_operand") 1331 (minus "aarch64_plus_operand")]) 1332 1333;; Constants acceptable for atomic operations. 1334;; This definition must appear in this file before the iterators it refers to. 1335(define_code_attr const_atomic 1336 [(plus "IJ") (minus "IJ") 1337 (xor "<lconst_atomic>") (ior "<lconst_atomic>") 1338 (and "<lconst_atomic>")]) 1339 1340;; Attribute to describe constants acceptable in atomic logical operations 1341(define_mode_attr lconst_atomic [(QI "K") (HI "K") (SI "K") (DI "L")]) 1342 1343;; The integer SVE instruction that implements an rtx code. 1344(define_code_attr sve_int_op [(plus "add") 1345 (neg "neg") 1346 (smin "smin") 1347 (smax "smax") 1348 (umin "umin") 1349 (umax "umax") 1350 (and "and") 1351 (ior "orr") 1352 (xor "eor") 1353 (not "not") 1354 (popcount "cnt")]) 1355 1356;; The floating-point SVE instruction that implements an rtx code. 1357(define_code_attr sve_fp_op [(plus "fadd") 1358 (neg "fneg") 1359 (abs "fabs") 1360 (sqrt "fsqrt")]) 1361 1362;; ------------------------------------------------------------------- 1363;; Int Iterators. 1364;; ------------------------------------------------------------------- 1365(define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV 1366 UNSPEC_SMAXV UNSPEC_SMINV]) 1367 1368(define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV 1369 UNSPEC_FMAXNMV UNSPEC_FMINNMV]) 1370 1371(define_int_iterator BITWISEV [UNSPEC_ANDV UNSPEC_IORV UNSPEC_XORV]) 1372 1373(define_int_iterator LOGICALF [UNSPEC_ANDF UNSPEC_IORF UNSPEC_XORF]) 1374 1375(define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD 1376 UNSPEC_SRHADD UNSPEC_URHADD 1377 UNSPEC_SHSUB UNSPEC_UHSUB 1378 UNSPEC_SRHSUB UNSPEC_URHSUB]) 1379 1380(define_int_iterator DOTPROD [UNSPEC_SDOT UNSPEC_UDOT]) 1381 1382(define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN 1383 UNSPEC_SUBHN UNSPEC_RSUBHN]) 1384 1385(define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2 1386 UNSPEC_SUBHN2 UNSPEC_RSUBHN2]) 1387 1388(define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN 1389 UNSPEC_FMAXNM UNSPEC_FMINNM]) 1390 1391(define_int_iterator PAUTH_LR_SP [UNSPEC_PACISP UNSPEC_AUTISP]) 1392 1393(define_int_iterator PAUTH_17_16 [UNSPEC_PACI1716 UNSPEC_AUTI1716]) 1394 1395(define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH]) 1396 1397(define_int_iterator USSUQADD [UNSPEC_SUQADD UNSPEC_USQADD]) 1398 1399(define_int_iterator SUQMOVN [UNSPEC_SQXTN UNSPEC_UQXTN]) 1400 1401(define_int_iterator VSHL [UNSPEC_SSHL UNSPEC_USHL 1402 UNSPEC_SRSHL UNSPEC_URSHL]) 1403 1404(define_int_iterator VSHLL [UNSPEC_SSHLL UNSPEC_USHLL]) 1405 1406(define_int_iterator VQSHL [UNSPEC_SQSHL UNSPEC_UQSHL 1407 UNSPEC_SQRSHL UNSPEC_UQRSHL]) 1408 1409(define_int_iterator VSRA [UNSPEC_SSRA UNSPEC_USRA 1410 UNSPEC_SRSRA UNSPEC_URSRA]) 1411 1412(define_int_iterator VSLRI [UNSPEC_SSLI UNSPEC_USLI 1413 UNSPEC_SSRI UNSPEC_USRI]) 1414 1415 1416(define_int_iterator VRSHR_N [UNSPEC_SRSHR UNSPEC_URSHR]) 1417 1418(define_int_iterator VQSHL_N [UNSPEC_SQSHLU UNSPEC_SQSHL UNSPEC_UQSHL]) 1419 1420(define_int_iterator VQSHRN_N [UNSPEC_SQSHRUN UNSPEC_SQRSHRUN 1421 UNSPEC_SQSHRN UNSPEC_UQSHRN 1422 UNSPEC_SQRSHRN UNSPEC_UQRSHRN]) 1423 1424(define_int_iterator SQRDMLH_AS [UNSPEC_SQRDMLAH UNSPEC_SQRDMLSH]) 1425 1426(define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2 1427 UNSPEC_TRN1 UNSPEC_TRN2 1428 UNSPEC_UZP1 UNSPEC_UZP2]) 1429 1430(define_int_iterator OPTAB_PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2 1431 UNSPEC_UZP1 UNSPEC_UZP2]) 1432 1433(define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16]) 1434 1435(define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM 1436 UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX 1437 UNSPEC_FRINTA]) 1438 1439(define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM 1440 UNSPEC_FRINTA UNSPEC_FRINTN]) 1441 1442(define_int_iterator FCVT_F2FIXED [UNSPEC_FCVTZS UNSPEC_FCVTZU]) 1443(define_int_iterator FCVT_FIXED2F [UNSPEC_SCVTF UNSPEC_UCVTF]) 1444 1445(define_int_iterator FRECP [UNSPEC_FRECPE UNSPEC_FRECPX]) 1446 1447(define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W 1448 UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH 1449 UNSPEC_CRC32CW UNSPEC_CRC32CX]) 1450 1451(define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD]) 1452(define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC]) 1453 1454(define_int_iterator CRYPTO_SHA1 [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P]) 1455 1456(define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2]) 1457 1458(define_int_iterator CRYPTO_SHA512 [UNSPEC_SHA512H UNSPEC_SHA512H2]) 1459 1460(define_int_iterator CRYPTO_SM3TT [UNSPEC_SM3TT1A UNSPEC_SM3TT1B 1461 UNSPEC_SM3TT2A UNSPEC_SM3TT2B]) 1462 1463(define_int_iterator CRYPTO_SM3PART [UNSPEC_SM3PARTW1 UNSPEC_SM3PARTW2]) 1464 1465;; Iterators for fp16 operations 1466 1467(define_int_iterator VFMLA16_LOW [UNSPEC_FMLAL UNSPEC_FMLSL]) 1468 1469(define_int_iterator VFMLA16_HIGH [UNSPEC_FMLAL2 UNSPEC_FMLSL2]) 1470 1471(define_int_iterator UNPACK [UNSPEC_UNPACKSHI UNSPEC_UNPACKUHI 1472 UNSPEC_UNPACKSLO UNSPEC_UNPACKULO]) 1473 1474(define_int_iterator UNPACK_UNSIGNED [UNSPEC_UNPACKULO UNSPEC_UNPACKUHI]) 1475 1476(define_int_iterator MUL_HIGHPART [UNSPEC_SMUL_HIGHPART UNSPEC_UMUL_HIGHPART]) 1477 1478(define_int_iterator SVE_COND_INT_OP [UNSPEC_COND_ADD UNSPEC_COND_SUB 1479 UNSPEC_COND_SMAX UNSPEC_COND_UMAX 1480 UNSPEC_COND_SMIN UNSPEC_COND_UMIN 1481 UNSPEC_COND_AND 1482 UNSPEC_COND_ORR 1483 UNSPEC_COND_EOR]) 1484 1485(define_int_iterator SVE_COND_FP_OP [UNSPEC_COND_ADD UNSPEC_COND_SUB]) 1486 1487(define_int_iterator SVE_COND_INT_CMP [UNSPEC_COND_LT UNSPEC_COND_LE 1488 UNSPEC_COND_EQ UNSPEC_COND_NE 1489 UNSPEC_COND_GE UNSPEC_COND_GT 1490 UNSPEC_COND_LO UNSPEC_COND_LS 1491 UNSPEC_COND_HS UNSPEC_COND_HI]) 1492 1493(define_int_iterator SVE_COND_FP_CMP [UNSPEC_COND_LT UNSPEC_COND_LE 1494 UNSPEC_COND_EQ UNSPEC_COND_NE 1495 UNSPEC_COND_GE UNSPEC_COND_GT]) 1496 1497;; Iterators for atomic operations. 1498 1499(define_int_iterator ATOMIC_LDOP 1500 [UNSPECV_ATOMIC_LDOP_OR UNSPECV_ATOMIC_LDOP_BIC 1501 UNSPECV_ATOMIC_LDOP_XOR UNSPECV_ATOMIC_LDOP_PLUS]) 1502 1503(define_int_attr atomic_ldop 1504 [(UNSPECV_ATOMIC_LDOP_OR "set") (UNSPECV_ATOMIC_LDOP_BIC "clr") 1505 (UNSPECV_ATOMIC_LDOP_XOR "eor") (UNSPECV_ATOMIC_LDOP_PLUS "add")]) 1506 1507;; ------------------------------------------------------------------- 1508;; Int Iterators Attributes. 1509;; ------------------------------------------------------------------- 1510 1511;; The optab associated with an operation. Note that for ANDF, IORF 1512;; and XORF, the optab pattern is not actually defined; we just use this 1513;; name for consistency with the integer patterns. 1514(define_int_attr optab [(UNSPEC_ANDF "and") 1515 (UNSPEC_IORF "ior") 1516 (UNSPEC_XORF "xor") 1517 (UNSPEC_ANDV "and") 1518 (UNSPEC_IORV "ior") 1519 (UNSPEC_XORV "xor") 1520 (UNSPEC_COND_ADD "add") 1521 (UNSPEC_COND_SUB "sub") 1522 (UNSPEC_COND_SMAX "smax") 1523 (UNSPEC_COND_UMAX "umax") 1524 (UNSPEC_COND_SMIN "smin") 1525 (UNSPEC_COND_UMIN "umin") 1526 (UNSPEC_COND_AND "and") 1527 (UNSPEC_COND_ORR "ior") 1528 (UNSPEC_COND_EOR "xor")]) 1529 1530(define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax") 1531 (UNSPEC_UMINV "umin") 1532 (UNSPEC_SMAXV "smax") 1533 (UNSPEC_SMINV "smin") 1534 (UNSPEC_FMAX "smax_nan") 1535 (UNSPEC_FMAXNMV "smax") 1536 (UNSPEC_FMAXV "smax_nan") 1537 (UNSPEC_FMIN "smin_nan") 1538 (UNSPEC_FMINNMV "smin") 1539 (UNSPEC_FMINV "smin_nan") 1540 (UNSPEC_FMAXNM "fmax") 1541 (UNSPEC_FMINNM "fmin")]) 1542 1543(define_int_attr maxmin_uns_op [(UNSPEC_UMAXV "umax") 1544 (UNSPEC_UMINV "umin") 1545 (UNSPEC_SMAXV "smax") 1546 (UNSPEC_SMINV "smin") 1547 (UNSPEC_FMAX "fmax") 1548 (UNSPEC_FMAXNMV "fmaxnm") 1549 (UNSPEC_FMAXV "fmax") 1550 (UNSPEC_FMIN "fmin") 1551 (UNSPEC_FMINNMV "fminnm") 1552 (UNSPEC_FMINV "fmin") 1553 (UNSPEC_FMAXNM "fmaxnm") 1554 (UNSPEC_FMINNM "fminnm")]) 1555 1556(define_int_attr bit_reduc_op [(UNSPEC_ANDV "andv") 1557 (UNSPEC_IORV "orv") 1558 (UNSPEC_XORV "eorv")]) 1559 1560;; The SVE logical instruction that implements an unspec. 1561(define_int_attr logicalf_op [(UNSPEC_ANDF "and") 1562 (UNSPEC_IORF "orr") 1563 (UNSPEC_XORF "eor")]) 1564 1565;; "s" for signed operations and "u" for unsigned ones. 1566(define_int_attr su [(UNSPEC_UNPACKSHI "s") 1567 (UNSPEC_UNPACKUHI "u") 1568 (UNSPEC_UNPACKSLO "s") 1569 (UNSPEC_UNPACKULO "u") 1570 (UNSPEC_SMUL_HIGHPART "s") 1571 (UNSPEC_UMUL_HIGHPART "u")]) 1572 1573(define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u") 1574 (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur") 1575 (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u") 1576 (UNSPEC_SRHSUB "sr") (UNSPEC_URHSUB "ur") 1577 (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r") 1578 (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r") 1579 (UNSPEC_ADDHN2 "") (UNSPEC_RADDHN2 "r") 1580 (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r") 1581 (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u") 1582 (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su") 1583 (UNSPEC_SSLI "s") (UNSPEC_USLI "u") 1584 (UNSPEC_SSRI "s") (UNSPEC_USRI "u") 1585 (UNSPEC_USRA "u") (UNSPEC_SSRA "s") 1586 (UNSPEC_URSRA "ur") (UNSPEC_SRSRA "sr") 1587 (UNSPEC_URSHR "ur") (UNSPEC_SRSHR "sr") 1588 (UNSPEC_SQSHLU "s") (UNSPEC_SQSHL "s") 1589 (UNSPEC_UQSHL "u") 1590 (UNSPEC_SQSHRUN "s") (UNSPEC_SQRSHRUN "s") 1591 (UNSPEC_SQSHRN "s") (UNSPEC_UQSHRN "u") 1592 (UNSPEC_SQRSHRN "s") (UNSPEC_UQRSHRN "u") 1593 (UNSPEC_USHL "u") (UNSPEC_SSHL "s") 1594 (UNSPEC_USHLL "u") (UNSPEC_SSHLL "s") 1595 (UNSPEC_URSHL "ur") (UNSPEC_SRSHL "sr") 1596 (UNSPEC_UQRSHL "u") (UNSPEC_SQRSHL "s") 1597 (UNSPEC_SDOT "s") (UNSPEC_UDOT "u") 1598]) 1599 1600(define_int_attr r [(UNSPEC_SQDMULH "") (UNSPEC_SQRDMULH "r") 1601 (UNSPEC_SQSHRUN "") (UNSPEC_SQRSHRUN "r") 1602 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "") 1603 (UNSPEC_SQRSHRN "r") (UNSPEC_UQRSHRN "r") 1604 (UNSPEC_SQSHL "") (UNSPEC_UQSHL "") 1605 (UNSPEC_SQRSHL "r")(UNSPEC_UQRSHL "r") 1606]) 1607 1608(define_int_attr lr [(UNSPEC_SSLI "l") (UNSPEC_USLI "l") 1609 (UNSPEC_SSRI "r") (UNSPEC_USRI "r")]) 1610 1611(define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "") 1612 (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u") 1613 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "") 1614 (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "")]) 1615 1616(define_int_attr addsub [(UNSPEC_SHADD "add") 1617 (UNSPEC_UHADD "add") 1618 (UNSPEC_SRHADD "add") 1619 (UNSPEC_URHADD "add") 1620 (UNSPEC_SHSUB "sub") 1621 (UNSPEC_UHSUB "sub") 1622 (UNSPEC_SRHSUB "sub") 1623 (UNSPEC_URHSUB "sub") 1624 (UNSPEC_ADDHN "add") 1625 (UNSPEC_SUBHN "sub") 1626 (UNSPEC_RADDHN "add") 1627 (UNSPEC_RSUBHN "sub") 1628 (UNSPEC_ADDHN2 "add") 1629 (UNSPEC_SUBHN2 "sub") 1630 (UNSPEC_RADDHN2 "add") 1631 (UNSPEC_RSUBHN2 "sub")]) 1632 1633(define_int_attr offsetlr [(UNSPEC_SSLI "") (UNSPEC_USLI "") 1634 (UNSPEC_SSRI "offset_") 1635 (UNSPEC_USRI "offset_")]) 1636 1637;; Standard pattern names for floating-point rounding instructions. 1638(define_int_attr frint_pattern [(UNSPEC_FRINTZ "btrunc") 1639 (UNSPEC_FRINTP "ceil") 1640 (UNSPEC_FRINTM "floor") 1641 (UNSPEC_FRINTI "nearbyint") 1642 (UNSPEC_FRINTX "rint") 1643 (UNSPEC_FRINTA "round") 1644 (UNSPEC_FRINTN "frintn")]) 1645 1646;; frint suffix for floating-point rounding instructions. 1647(define_int_attr frint_suffix [(UNSPEC_FRINTZ "z") (UNSPEC_FRINTP "p") 1648 (UNSPEC_FRINTM "m") (UNSPEC_FRINTI "i") 1649 (UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a") 1650 (UNSPEC_FRINTN "n")]) 1651 1652(define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round") 1653 (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor") 1654 (UNSPEC_FRINTN "frintn")]) 1655 1656(define_int_attr fcvt_fixed_insn [(UNSPEC_SCVTF "scvtf") 1657 (UNSPEC_UCVTF "ucvtf") 1658 (UNSPEC_FCVTZS "fcvtzs") 1659 (UNSPEC_FCVTZU "fcvtzu")]) 1660 1661;; Pointer authentication mnemonic prefix. 1662(define_int_attr pauth_mnem_prefix [(UNSPEC_PACISP "paci") 1663 (UNSPEC_AUTISP "auti") 1664 (UNSPEC_PACI1716 "paci") 1665 (UNSPEC_AUTI1716 "auti")]) 1666 1667;; Pointer authentication HINT number for NOP space instructions using A Key. 1668(define_int_attr pauth_hint_num_a [(UNSPEC_PACISP "25") 1669 (UNSPEC_AUTISP "29") 1670 (UNSPEC_PACI1716 "8") 1671 (UNSPEC_AUTI1716 "12")]) 1672 1673(define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip") 1674 (UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn") 1675 (UNSPEC_UZP1 "uzp") (UNSPEC_UZP2 "uzp")]) 1676 1677; op code for REV instructions (size within which elements are reversed). 1678(define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32") 1679 (UNSPEC_REV16 "16")]) 1680 1681(define_int_attr perm_hilo [(UNSPEC_ZIP1 "1") (UNSPEC_ZIP2 "2") 1682 (UNSPEC_TRN1 "1") (UNSPEC_TRN2 "2") 1683 (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2") 1684 (UNSPEC_UNPACKSHI "hi") (UNSPEC_UNPACKUHI "hi") 1685 (UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo")]) 1686 1687;; Return true if the associated optab refers to the high-numbered lanes, 1688;; false if it refers to the low-numbered lanes. The convention is for 1689;; "hi" to refer to the low-numbered lanes (the first ones in memory) 1690;; for big-endian. 1691(define_int_attr hi_lanes_optab [(UNSPEC_UNPACKSHI "!BYTES_BIG_ENDIAN") 1692 (UNSPEC_UNPACKUHI "!BYTES_BIG_ENDIAN") 1693 (UNSPEC_UNPACKSLO "BYTES_BIG_ENDIAN") 1694 (UNSPEC_UNPACKULO "BYTES_BIG_ENDIAN")]) 1695 1696(define_int_attr frecp_suffix [(UNSPEC_FRECPE "e") (UNSPEC_FRECPX "x")]) 1697 1698(define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h") 1699 (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x") 1700 (UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch") 1701 (UNSPEC_CRC32CW "crc32cw") (UNSPEC_CRC32CX "crc32cx")]) 1702 1703(define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI") 1704 (UNSPEC_CRC32W "SI") (UNSPEC_CRC32X "DI") 1705 (UNSPEC_CRC32CB "QI") (UNSPEC_CRC32CH "HI") 1706 (UNSPEC_CRC32CW "SI") (UNSPEC_CRC32CX "DI")]) 1707 1708(define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")]) 1709(define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")]) 1710 1711(define_int_attr sha1_op [(UNSPEC_SHA1C "c") (UNSPEC_SHA1P "p") 1712 (UNSPEC_SHA1M "m")]) 1713 1714(define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")]) 1715 1716(define_int_attr rdma_as [(UNSPEC_SQRDMLAH "a") (UNSPEC_SQRDMLSH "s")]) 1717 1718(define_int_attr sha512_op [(UNSPEC_SHA512H "") (UNSPEC_SHA512H2 "2")]) 1719 1720(define_int_attr sm3tt_op [(UNSPEC_SM3TT1A "1a") (UNSPEC_SM3TT1B "1b") 1721 (UNSPEC_SM3TT2A "2a") (UNSPEC_SM3TT2B "2b")]) 1722 1723(define_int_attr sm3part_op [(UNSPEC_SM3PARTW1 "1") (UNSPEC_SM3PARTW2 "2")]) 1724 1725(define_int_attr f16mac1 [(UNSPEC_FMLAL "a") (UNSPEC_FMLSL "s") 1726 (UNSPEC_FMLAL2 "a") (UNSPEC_FMLSL2 "s")]) 1727 1728;; The condition associated with an UNSPEC_COND_<xx>. 1729(define_int_attr cmp_op [(UNSPEC_COND_LT "lt") 1730 (UNSPEC_COND_LE "le") 1731 (UNSPEC_COND_EQ "eq") 1732 (UNSPEC_COND_NE "ne") 1733 (UNSPEC_COND_GE "ge") 1734 (UNSPEC_COND_GT "gt") 1735 (UNSPEC_COND_LO "lo") 1736 (UNSPEC_COND_LS "ls") 1737 (UNSPEC_COND_HS "hs") 1738 (UNSPEC_COND_HI "hi")]) 1739 1740;; The constraint to use for an UNSPEC_COND_<xx>. 1741(define_int_attr imm_con [(UNSPEC_COND_EQ "vsc") 1742 (UNSPEC_COND_NE "vsc") 1743 (UNSPEC_COND_LT "vsc") 1744 (UNSPEC_COND_GE "vsc") 1745 (UNSPEC_COND_LE "vsc") 1746 (UNSPEC_COND_GT "vsc") 1747 (UNSPEC_COND_LO "vsd") 1748 (UNSPEC_COND_LS "vsd") 1749 (UNSPEC_COND_HS "vsd") 1750 (UNSPEC_COND_HI "vsd")]) 1751 1752(define_int_attr sve_int_op [(UNSPEC_COND_ADD "add") 1753 (UNSPEC_COND_SUB "sub") 1754 (UNSPEC_COND_SMAX "smax") 1755 (UNSPEC_COND_UMAX "umax") 1756 (UNSPEC_COND_SMIN "smin") 1757 (UNSPEC_COND_UMIN "umin") 1758 (UNSPEC_COND_AND "and") 1759 (UNSPEC_COND_ORR "orr") 1760 (UNSPEC_COND_EOR "eor")]) 1761 1762(define_int_attr sve_fp_op [(UNSPEC_COND_ADD "fadd") 1763 (UNSPEC_COND_SUB "fsub")]) 1764