1;; Machine Descriptions for R8C/M16C/M32C
2;; Copyright (C) 2006-2018 Free Software Foundation, Inc.
3;; Contributed by Red Hat.
4;;
5;; This file is part of GCC.
6;;
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published
9;; by the Free Software Foundation; either version 3, or (at your
10;; option) any later version.
11;;
12;; GCC is distributed in the hope that it will be useful, but WITHOUT
13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15;; License for more details.
16;;
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3.  If not see
19;; <http://www.gnu.org/licenses/>.
20
21;; various block move instructions
22
23;; R8C:
24;;  SMOVB - while (r3--) { *a1-- = *r1ha0--; } - memcpy
25;;  SMOVF - while (r3--) { *a1++ = *r1ha0++; } - memcpy
26;;  SSTR  - while (r3--) { *a1++ = [r0l,r0]; } - memset
27
28;; M32CM:
29;;  SCMPU - while (*a0 && *a0 != *a1) { a0++; a1++; } - strcmp
30;;  SIN   - while (r3--) { *a1++ = *a0; }
31;;  SMOVB - while (r3--) { *a1-- = *a0--; } - memcpy
32;;  SMOVF - while (r3--) { *a1++ = *a0++; } - memcpy
33;;  SMOVU - while (*a1++ = *a0++) ; - strcpy
34;;  SOUT  - while (r3--) { *a1 = *a0++; }
35;;  SSTR  - while (r3--) { *a1++ = [r0l,r0]; } - memset
36
37
38
39;; 0 = destination (mem:BLK ...)
40;; 1 = source (mem:BLK ...)
41;; 2 = count
42;; 3 = alignment
43(define_expand "movmemhi"
44  [(match_operand 0 "ap_operand" "")
45   (match_operand 1 "ap_operand" "")
46   (match_operand 2 "m32c_r3_operand" "")
47   (match_operand 3 "" "")
48   ]
49  ""
50  "if (m32c_expand_movmemhi(operands)) DONE; FAIL;"
51  )
52
53;; We can't use mode iterators for these because M16C uses r1h to extend
54;; the source address, for copying data from ROM to RAM.  We don't yet
55;; support that, but we need to zero our r1h, so the patterns differ.
56
57;; 0 = dest (out)
58;; 1 = src (out)
59;; 2 = count (out)
60;; 3 = dest (in)
61;; 4 = src (in)
62;; 5 = count (in)
63(define_insn "movmemhi_bhi_op"
64  [(set (mem:QI (match_operand:HI 3 "ap_operand" "0"))
65	(mem:QI (match_operand:HI 4 "ap_operand" "1")))
66   (set (match_operand:HI 2 "m32c_r3_operand" "=R3w")
67	(const_int 0))
68   (set (match_operand:HI 0 "ap_operand" "=Ra1")
69	(plus:HI (match_dup 3)
70		  (zero_extend:HI (match_operand:HI 5 "m32c_r3_operand" "2"))))
71   (set (match_operand:HI 1 "ap_operand" "=Ra0")
72	(plus:HI (match_dup 4)
73		  (zero_extend:HI (match_dup 5))))
74   (use (reg:HI R1_REGNO))]
75  "TARGET_A16"
76  "mov.b:q\t#0,r1h\n\tsmovf.b\t; %0[0..%2-1]=r1h%1[]"
77  )
78(define_insn "movmemhi_bpsi_op"
79  [(set (mem:QI (match_operand:PSI 3 "ap_operand" "0"))
80	(mem:QI (match_operand:PSI 4 "ap_operand" "1")))
81   (set (match_operand:HI 2 "m32c_r3_operand" "=R3w")
82	(const_int 0))
83   (set (match_operand:PSI 0 "ap_operand" "=Ra1")
84	(plus:PSI (match_dup 3)
85		  (zero_extend:PSI (match_operand:HI 5 "m32c_r3_operand" "2"))))
86   (set (match_operand:PSI 1 "ap_operand" "=Ra0")
87	(plus:PSI (match_dup 4)
88		  (zero_extend:PSI (match_dup 5))))]
89  "TARGET_A24"
90  "smovf.b\t; %0[0..%2-1]=%1[]"
91  )
92(define_insn "movmemhi_whi_op"
93  [(set (mem:HI (match_operand:HI 3 "ap_operand" "0"))
94	(mem:HI (match_operand:HI 4 "ap_operand" "1")))
95   (set (match_operand:HI 2 "m32c_r3_operand" "=R3w")
96	(const_int 0))
97   (set (match_operand:HI 0 "ap_operand" "=Ra1")
98	(plus:HI (match_dup 3)
99		  (zero_extend:HI (match_operand:HI 5 "m32c_r3_operand" "2"))))
100   (set (match_operand:HI 1 "ap_operand" "=Ra0")
101	(plus:HI (match_dup 4)
102		  (zero_extend:HI (match_dup 5))))
103   (use (reg:HI R1_REGNO))]
104  "TARGET_A16"
105  "mov.b:q\t#0,r1h\n\tsmovf.w\t; %0[0..%2-1]=r1h%1[]"
106  )
107(define_insn "movmemhi_wpsi_op"
108  [(set (mem:HI (match_operand:PSI 3 "ap_operand" "0"))
109	(mem:HI (match_operand:PSI 4 "ap_operand" "1")))
110   (set (match_operand:HI 2 "m32c_r3_operand" "=R3w")
111	(const_int 0))
112   (set (match_operand:PSI 0 "ap_operand" "=Ra1")
113	(plus:PSI (match_dup 3)
114		  (zero_extend:PSI (match_operand:HI 5 "m32c_r3_operand" "2"))))
115   (set (match_operand:PSI 1 "ap_operand" "=Ra0")
116	(plus:PSI (match_dup 4)
117		  (zero_extend:PSI (match_dup 5))))]
118  "TARGET_A24"
119  "smovf.w\t; %0[0..%2-1]=%1[]"
120  )
121
122
123
124;; 0 = destination (mem:BLK ...)
125;; 1 = number of bytes
126;; 2 = value to store
127;; 3 = alignment
128(define_expand "setmemhi"
129  [(match_operand 0 "ap_operand" "")
130   (match_operand 1 "m32c_r3_operand" "")
131   (match_operand 2 "m32c_r0_operand" "")
132   (match_operand 3 "" "")
133   ]
134  "TARGET_A24"
135  "if (m32c_expand_setmemhi(operands)) DONE; FAIL;"
136  )
137
138;; 0 = address (out)
139;; 1 = count (out)
140;; 2 = value (in)
141;; 3 = address (in)
142;; 4 = count (in)
143(define_insn "setmemhi_b<mode>_op"
144  [(set (mem:QI (match_operand:HPSI 3 "ap_operand" "0"))
145	(match_operand:QI 2 "m32c_r0_operand" "R0w"))
146   (set (match_operand:HI 1 "m32c_r3_operand" "=R3w")
147	(const_int 0))
148   (set (match_operand:HPSI 0 "ap_operand" "=Ra1")
149	(plus:HPSI (match_dup 3)
150		  (zero_extend:HPSI (match_operand:HI 4 "m32c_r3_operand" "1"))))]
151  "TARGET_A24"
152  "sstr.b\t; %0[0..%1-1]=%2"
153  )
154
155(define_insn "setmemhi_w<mode>_op"
156  [(set (mem:HI (match_operand:HPSI 3 "ap_operand" "0"))
157	(match_operand:HI 2 "m32c_r0_operand" "R0w"))
158   (set (match_operand:HI 1 "m32c_r3_operand" "=R3w")
159	(const_int 0))
160   (set (match_operand:HPSI 0 "ap_operand" "=Ra1")
161	(plus:HPSI (match_dup 3)
162		  (zero_extend:HPSI (match_operand:HI 4 "m32c_r3_operand" "1"))))]
163  "TARGET_A24"
164  "sstr.w\t; %0[0..%1-1]=%2"
165  )
166
167
168;; SCMPU sets the flags according to the result of the string
169;; comparison.  GCC wants the result to be a signed value reflecting
170;; the result, which it then compares to zero.  Hopefully we can
171;; optimize that later (see peephole in cond.md).  Meanwhile, the
172;; strcmp builtin is expanded to a SCMPU followed by a flags-to-int
173;; pattern in cond.md.
174
175;; 0 = result:HI
176;; 1 = destination (mem:BLK ...)
177;; 2 = source (mem:BLK ...)
178;; 3 = alignment
179
180(define_expand "cmpstrsi"
181  [(match_operand:HI 0 "register_operand" "")
182   (match_operand 1 "memory_operand" "")
183   (match_operand 2 "memory_operand" "")
184   (match_operand 3 "const_int_operand" "")
185   ]
186  "TARGET_A24"
187  "if (m32c_expand_cmpstr(operands)) DONE; FAIL;"
188  )
189
190;; 0 = string1
191;; 1 = string2
192
193(define_insn "cmpstrhi_op"
194  [(set (reg:CC FLG_REGNO)
195	(compare:CC (mem:BLK (match_operand:PSI 0 "ap_operand" "Ra0"))
196		    (mem:BLK (match_operand:PSI 1 "ap_operand" "Ra1"))))
197   (clobber (match_operand:PSI 2 "ap_operand" "=0"))
198   (clobber (match_operand:PSI 3 "ap_operand" "=1"))]
199  "TARGET_A24"
200  "scmpu.b\t; flags := strcmp(*%0,*%1)"
201  [(set_attr "flags" "oszc")]
202  )
203
204
205
206;; Note that SMOVU leaves the address registers pointing *after*
207;; the NUL at the end of the string.  This is not what gcc expects; it
208;; expects the address registers to point *at* the NUL.  The expander
209;; must emit a suitable add insn.
210
211;; 0 = target: set to &NUL in dest
212;; 1 = destination (mem:BLK ...)
213;; 2 = source (mem:BLK ...)
214
215(define_expand "movstr"
216  [(match_operand 0 "m32c_nonimmediate_operand" "")
217   (match_operand 1 "" "")
218   (match_operand 2 "" "")
219   ]
220  "TARGET_A24"
221  "if (m32c_expand_movstr(operands)) DONE; FAIL;"
222  )
223
224;; 0 = dest (out)
225;; 1 = src (out) (clobbered)
226;; 2 = dest (in)
227;; 3 = src (in)
228(define_insn "movstr_op"
229  [(set (mem:BLK (match_operand:PSI 2 "ap_operand" "0"))
230	(mem:BLK (match_operand:PSI 3 "ap_operand" "1")))
231   (set (match_operand:PSI 0 "ap_operand" "=Ra1")
232	(plus:PSI (match_dup 2)
233		  (unspec:PSI [(const_int 0)] UNS_SMOVU)))
234   (set (match_operand:PSI 1 "ap_operand" "=Ra0")
235	(plus:PSI (match_dup 3)
236		  (unspec:PSI [(const_int 0)] UNS_SMOVU)))]
237  "TARGET_A24"
238  "smovu.b\t; while (*%2++ := *%3++) != 0"
239  [(set_attr "flags" "*")]
240  )
241
242