1;; Scheduling description for IBM POWER8 processor. 2;; Copyright (C) 2013-2014 Free Software Foundation, Inc. 3;; 4;; Contributed by Pat Haugen (pthaugen@us.ibm.com). 5 6;; This file is part of GCC. 7;; 8;; GCC is free software; you can redistribute it and/or modify it 9;; under the terms of the GNU General Public License as published 10;; by the Free Software Foundation; either version 3, or (at your 11;; option) any later version. 12;; 13;; GCC is distributed in the hope that it will be useful, but WITHOUT 14;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16;; License for more details. 17;; 18;; You should have received a copy of the GNU General Public License 19;; along with GCC; see the file COPYING3. If not see 20;; <http://www.gnu.org/licenses/>. 21 22(define_automaton "power8fxu,power8lsu,power8vsu,power8misc") 23 24(define_cpu_unit "fxu0_power8,fxu1_power8" "power8fxu") 25(define_cpu_unit "lu0_power8,lu1_power8" "power8lsu") 26(define_cpu_unit "lsu0_power8,lsu1_power8" "power8lsu") 27(define_cpu_unit "vsu0_power8,vsu1_power8" "power8vsu") 28(define_cpu_unit "bpu_power8,cru_power8" "power8misc") 29(define_cpu_unit "du0_power8,du1_power8,du2_power8,du3_power8,du4_power8,\ 30 du5_power8,du6_power8" "power8misc") 31 32 33; Dispatch group reservations 34(define_reservation "DU_any_power8" 35 "du0_power8|du1_power8|du2_power8|du3_power8|du4_power8|\ 36 du5_power8") 37 38; 2-way Cracked instructions go in slots 0-1 39; (can also have a second in slots 3-4 if insns are adjacent) 40(define_reservation "DU_cracked_power8" 41 "du0_power8+du1_power8") 42 43; Insns that are first in group 44(define_reservation "DU_first_power8" 45 "du0_power8") 46 47; Insns that are first and last in group 48(define_reservation "DU_both_power8" 49 "du0_power8+du1_power8+du2_power8+du3_power8+du4_power8+\ 50 du5_power8+du6_power8") 51 52; Dispatch slots are allocated in order conforming to program order. 53(absence_set "du0_power8" "du1_power8,du2_power8,du3_power8,du4_power8,\ 54 du5_power8,du6_power8") 55(absence_set "du1_power8" "du2_power8,du3_power8,du4_power8,du5_power8,\ 56 du6_power8") 57(absence_set "du2_power8" "du3_power8,du4_power8,du5_power8,du6_power8") 58(absence_set "du3_power8" "du4_power8,du5_power8,du6_power8") 59(absence_set "du4_power8" "du5_power8,du6_power8") 60(absence_set "du5_power8" "du6_power8") 61 62 63; Execution unit reservations 64(define_reservation "FXU_power8" 65 "fxu0_power8|fxu1_power8") 66 67(define_reservation "LU_power8" 68 "lu0_power8|lu1_power8") 69 70(define_reservation "LSU_power8" 71 "lsu0_power8|lsu1_power8") 72 73(define_reservation "LU_or_LSU_power8" 74 "lu0_power8|lu1_power8|lsu0_power8|lsu1_power8") 75 76(define_reservation "VSU_power8" 77 "vsu0_power8|vsu1_power8") 78 79 80; LS Unit 81(define_insn_reservation "power8-load" 3 82 (and (eq_attr "type" "load") 83 (eq_attr "cpu" "power8")) 84 "DU_any_power8,LU_or_LSU_power8") 85 86(define_insn_reservation "power8-load-update" 3 87 (and (eq_attr "type" "load_u,load_ux") 88 (eq_attr "cpu" "power8")) 89 "DU_cracked_power8,LU_or_LSU_power8+FXU_power8") 90 91(define_insn_reservation "power8-load-ext" 3 92 (and (eq_attr "type" "load_ext") 93 (eq_attr "cpu" "power8")) 94 "DU_cracked_power8,LU_or_LSU_power8,FXU_power8") 95 96(define_insn_reservation "power8-load-ext-update" 3 97 (and (eq_attr "type" "load_ext_u,load_ext_ux") 98 (eq_attr "cpu" "power8")) 99 "DU_both_power8,LU_or_LSU_power8+FXU_power8,FXU_power8") 100 101(define_insn_reservation "power8-fpload" 5 102 (and (eq_attr "type" "fpload,vecload") 103 (eq_attr "cpu" "power8")) 104 "DU_any_power8,LU_power8") 105 106(define_insn_reservation "power8-fpload-update" 5 107 (and (eq_attr "type" "fpload_u,fpload_ux") 108 (eq_attr "cpu" "power8")) 109 "DU_cracked_power8,LU_power8+FXU_power8") 110 111(define_insn_reservation "power8-store" 5 ; store-forwarding latency 112 (and (eq_attr "type" "store,store_u") 113 (eq_attr "cpu" "power8")) 114 "DU_any_power8,LSU_power8+LU_power8") 115 116(define_insn_reservation "power8-store-update-indexed" 5 117 (and (eq_attr "type" "store_ux") 118 (eq_attr "cpu" "power8")) 119 "DU_cracked_power8,LSU_power8+LU_power8") 120 121(define_insn_reservation "power8-fpstore" 5 122 (and (eq_attr "type" "fpstore") 123 (eq_attr "cpu" "power8")) 124 "DU_any_power8,LSU_power8+VSU_power8") 125 126(define_insn_reservation "power8-fpstore-update" 5 127 (and (eq_attr "type" "fpstore_u,fpstore_ux") 128 (eq_attr "cpu" "power8")) 129 "DU_any_power8,LSU_power8+VSU_power8") 130 131(define_insn_reservation "power8-vecstore" 5 132 (and (eq_attr "type" "vecstore") 133 (eq_attr "cpu" "power8")) 134 "DU_cracked_power8,LSU_power8+VSU_power8") 135 136(define_insn_reservation "power8-larx" 3 137 (and (eq_attr "type" "load_l") 138 (eq_attr "cpu" "power8")) 139 "DU_both_power8,LU_or_LSU_power8") 140 141(define_insn_reservation "power8-stcx" 10 142 (and (eq_attr "type" "store_c") 143 (eq_attr "cpu" "power8")) 144 "DU_both_power8,LSU_power8+LU_power8") 145 146(define_insn_reservation "power8-sync" 1 147 (and (eq_attr "type" "sync,isync") 148 (eq_attr "cpu" "power8")) 149 "DU_both_power8,LSU_power8") 150 151 152; FX Unit 153(define_insn_reservation "power8-1cyc" 1 154 (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\ 155 var_shift_rotate,exts,isel") 156 (eq_attr "cpu" "power8")) 157 "DU_any_power8,FXU_power8") 158 159; Extra cycle to LU/LSU 160(define_bypass 2 "power8-1cyc" 161 "power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\ 162 power8-vecstore,power8-larx,power8-stcx") 163; "power8-load,power8-load-update,power8-load-ext,\ 164; power8-load-ext-update,power8-fpload,power8-fpload-update,\ 165; power8-store,power8-store-update,power8-store-update-indexed,\ 166; power8-fpstore,power8-fpstore-update,power8-vecstore,\ 167; power8-larx,power8-stcx") 168 169(define_insn_reservation "power8-2cyc" 2 170 (and (eq_attr "type" "cntlz,popcnt") 171 (eq_attr "cpu" "power8")) 172 "DU_any_power8,FXU_power8") 173 174(define_insn_reservation "power8-two" 2 175 (and (eq_attr "type" "two") 176 (eq_attr "cpu" "power8")) 177 "DU_any_power8+DU_any_power8,FXU_power8,FXU_power8") 178 179(define_insn_reservation "power8-three" 3 180 (and (eq_attr "type" "three") 181 (eq_attr "cpu" "power8")) 182 "DU_any_power8+DU_any_power8+DU_any_power8,FXU_power8,FXU_power8,FXU_power8") 183 184; cmp - Normal compare insns 185(define_insn_reservation "power8-cmp" 2 186 (and (eq_attr "type" "cmp") 187 (eq_attr "cpu" "power8")) 188 "DU_any_power8,FXU_power8") 189 190; fast_compare : add./and./nor./etc 191(define_insn_reservation "power8-fast-compare" 2 192 (and (eq_attr "type" "fast_compare") 193 (eq_attr "cpu" "power8")) 194 "DU_any_power8,FXU_power8") 195 196; compare : rldicl./exts./etc 197; delayed_compare : rlwinm./slwi./etc 198; var_delayed_compare : rlwnm./slw./etc 199(define_insn_reservation "power8-compare" 2 200 (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare") 201 (eq_attr "cpu" "power8")) 202 "DU_cracked_power8,FXU_power8,FXU_power8") 203 204; Extra cycle to LU/LSU 205(define_bypass 3 "power8-fast-compare,power8-compare" 206 "power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\ 207 power8-vecstore,power8-larx,power8-stcx") 208 209; 5 cycle CR latency 210(define_bypass 5 "power8-fast-compare,power8-compare" 211 "power8-crlogical,power8-mfcr,power8-mfcrf,power8-branch") 212 213(define_insn_reservation "power8-mul" 4 214 (and (eq_attr "type" "imul,imul2,imul3,lmul") 215 (eq_attr "cpu" "power8")) 216 "DU_any_power8,FXU_power8") 217 218(define_insn_reservation "power8-mul-compare" 4 219 (and (eq_attr "type" "imul_compare,lmul_compare") 220 (eq_attr "cpu" "power8")) 221 "DU_cracked_power8,FXU_power8") 222 223; Extra cycle to LU/LSU 224(define_bypass 5 "power8-mul,power8-mul-compare" 225 "power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\ 226 power8-vecstore,power8-larx,power8-stcx") 227 228; 7 cycle CR latency 229(define_bypass 7 "power8-mul,power8-mul-compare" 230 "power8-crlogical,power8-mfcr,power8-mfcrf,power8-branch") 231 232; FXU divides are not pipelined 233(define_insn_reservation "power8-idiv" 37 234 (and (eq_attr "type" "idiv") 235 (eq_attr "cpu" "power8")) 236 "DU_any_power8,fxu0_power8*37|fxu1_power8*37") 237 238(define_insn_reservation "power8-ldiv" 68 239 (and (eq_attr "type" "ldiv") 240 (eq_attr "cpu" "power8")) 241 "DU_any_power8,fxu0_power8*68|fxu1_power8*68") 242 243(define_insn_reservation "power8-mtjmpr" 5 244 (and (eq_attr "type" "mtjmpr") 245 (eq_attr "cpu" "power8")) 246 "DU_first_power8,FXU_power8") 247 248; Should differentiate between 1 cr field and > 1 since mtocrf is not microcode 249(define_insn_reservation "power8-mtcr" 3 250 (and (eq_attr "type" "mtcr") 251 (eq_attr "cpu" "power8")) 252 "DU_both_power8,FXU_power8") 253 254 255; CR Unit 256(define_insn_reservation "power8-mfjmpr" 5 257 (and (eq_attr "type" "mfjmpr") 258 (eq_attr "cpu" "power8")) 259 "DU_first_power8,cru_power8+FXU_power8") 260 261(define_insn_reservation "power8-crlogical" 3 262 (and (eq_attr "type" "cr_logical,delayed_cr") 263 (eq_attr "cpu" "power8")) 264 "DU_first_power8,cru_power8") 265 266(define_insn_reservation "power8-mfcr" 5 267 (and (eq_attr "type" "mfcr") 268 (eq_attr "cpu" "power8")) 269 "DU_both_power8,cru_power8") 270 271(define_insn_reservation "power8-mfcrf" 3 272 (and (eq_attr "type" "mfcrf") 273 (eq_attr "cpu" "power8")) 274 "DU_first_power8,cru_power8") 275 276 277; BR Unit 278; Branches take dispatch slot 7, but reserve any remaining prior slots to 279; prevent other insns from grabbing them once this is assigned. 280(define_insn_reservation "power8-branch" 3 281 (and (eq_attr "type" "jmpreg,branch") 282 (eq_attr "cpu" "power8")) 283 "(du6_power8\ 284 |du5_power8+du6_power8\ 285 |du4_power8+du5_power8+du6_power8\ 286 |du3_power8+du4_power8+du5_power8+du6_power8\ 287 |du2_power8+du3_power8+du4_power8+du5_power8+du6_power8\ 288 |du1_power8+du2_power8+du3_power8+du4_power8+du5_power8+du6_power8\ 289 |du0_power8+du1_power8+du2_power8+du3_power8+du4_power8+du5_power8+\ 290 du6_power8),bpu_power8") 291 292; Branch updating LR/CTR feeding mf[lr|ctr] 293(define_bypass 4 "power8-branch" "power8-mfjmpr") 294 295 296; VS Unit (includes FP/VSX/VMX/DFP/Crypto) 297(define_insn_reservation "power8-fp" 6 298 (and (eq_attr "type" "fp,dmul") 299 (eq_attr "cpu" "power8")) 300 "DU_any_power8,VSU_power8") 301 302; Additional 3 cycles for any CR result 303(define_bypass 9 "power8-fp" "power8-crlogical,power8-mfcr*,power8-branch") 304 305(define_insn_reservation "power8-fpcompare" 8 306 (and (eq_attr "type" "fpcompare") 307 (eq_attr "cpu" "power8")) 308 "DU_any_power8,VSU_power8") 309 310(define_insn_reservation "power8-sdiv" 27 311 (and (eq_attr "type" "sdiv") 312 (eq_attr "cpu" "power8")) 313 "DU_any_power8,VSU_power8") 314 315(define_insn_reservation "power8-ddiv" 33 316 (and (eq_attr "type" "ddiv") 317 (eq_attr "cpu" "power8")) 318 "DU_any_power8,VSU_power8") 319 320(define_insn_reservation "power8-sqrt" 32 321 (and (eq_attr "type" "ssqrt") 322 (eq_attr "cpu" "power8")) 323 "DU_any_power8,VSU_power8") 324 325(define_insn_reservation "power8-dsqrt" 44 326 (and (eq_attr "type" "dsqrt") 327 (eq_attr "cpu" "power8")) 328 "DU_any_power8,VSU_power8") 329 330(define_insn_reservation "power8-vecsimple" 2 331 (and (eq_attr "type" "vecperm,vecsimple,veccmp") 332 (eq_attr "cpu" "power8")) 333 "DU_any_power8,VSU_power8") 334 335(define_insn_reservation "power8-vecnormal" 6 336 (and (eq_attr "type" "vecfloat,vecdouble") 337 (eq_attr "cpu" "power8")) 338 "DU_any_power8,VSU_power8") 339 340(define_bypass 7 "power8-vecnormal" 341 "power8-vecsimple,power8-veccomplex,power8-fpstore*,\ 342 power8-vecstore") 343 344(define_insn_reservation "power8-veccomplex" 7 345 (and (eq_attr "type" "veccomplex") 346 (eq_attr "cpu" "power8")) 347 "DU_any_power8,VSU_power8") 348 349(define_insn_reservation "power8-vecfdiv" 25 350 (and (eq_attr "type" "vecfdiv") 351 (eq_attr "cpu" "power8")) 352 "DU_any_power8,VSU_power8") 353 354(define_insn_reservation "power8-vecdiv" 31 355 (and (eq_attr "type" "vecdiv") 356 (eq_attr "cpu" "power8")) 357 "DU_any_power8,VSU_power8") 358 359(define_insn_reservation "power8-mffgpr" 5 360 (and (eq_attr "type" "mffgpr") 361 (eq_attr "cpu" "power8")) 362 "DU_any_power8,VSU_power8") 363 364(define_insn_reservation "power8-mftgpr" 6 365 (and (eq_attr "type" "mftgpr") 366 (eq_attr "cpu" "power8")) 367 "DU_any_power8,VSU_power8") 368 369(define_insn_reservation "power8-crypto" 7 370 (and (eq_attr "type" "crypto") 371 (eq_attr "cpu" "power8")) 372 "DU_any_power8,VSU_power8") 373 374