1 /* Definitions of target machine for GNU compiler, for IBM RS/6000. 2 Copyright (C) 1992-2014 Free Software Foundation, Inc. 3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published 9 by the Free Software Foundation; either version 3, or (at your 10 option) any later version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 Under Section 7 of GPL version 3, you are granted additional 18 permissions described in the GCC Runtime Library Exception, version 19 3.1, as published by the Free Software Foundation. 20 21 You should have received a copy of the GNU General Public License and 22 a copy of the GCC Runtime Library Exception along with this program; 23 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 24 <http://www.gnu.org/licenses/>. */ 25 26 /* Note that some other tm.h files include this one and then override 27 many of the definitions. */ 28 29 #ifndef RS6000_OPTS_H 30 #include "config/rs6000/rs6000-opts.h" 31 #endif 32 33 /* Definitions for the object file format. These are set at 34 compile-time. */ 35 36 #define OBJECT_XCOFF 1 37 #define OBJECT_ELF 2 38 #define OBJECT_PEF 3 39 #define OBJECT_MACHO 4 40 41 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF) 42 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF) 43 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF) 44 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO) 45 46 #ifndef TARGET_AIX 47 #define TARGET_AIX 0 48 #endif 49 50 #ifndef TARGET_AIX_OS 51 #define TARGET_AIX_OS 0 52 #endif 53 54 /* Control whether function entry points use a "dot" symbol when 55 ABI_AIX. */ 56 #define DOT_SYMBOLS 1 57 58 /* Default string to use for cpu if not specified. */ 59 #ifndef TARGET_CPU_DEFAULT 60 #define TARGET_CPU_DEFAULT ((char *)0) 61 #endif 62 63 /* If configured for PPC405, support PPC405CR Erratum77. */ 64 #ifdef CONFIG_PPC405CR 65 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405) 66 #else 67 #define PPC405_ERRATUM77 0 68 #endif 69 70 #ifndef TARGET_PAIRED_FLOAT 71 #define TARGET_PAIRED_FLOAT 0 72 #endif 73 74 #ifdef HAVE_AS_POPCNTB 75 #define ASM_CPU_POWER5_SPEC "-mpower5" 76 #else 77 #define ASM_CPU_POWER5_SPEC "-mpower4" 78 #endif 79 80 #ifdef HAVE_AS_DFP 81 #define ASM_CPU_POWER6_SPEC "-mpower6 -maltivec" 82 #else 83 #define ASM_CPU_POWER6_SPEC "-mpower4 -maltivec" 84 #endif 85 86 #ifdef HAVE_AS_POPCNTD 87 #define ASM_CPU_POWER7_SPEC "-mpower7" 88 #else 89 #define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec" 90 #endif 91 92 #ifdef HAVE_AS_POWER8 93 #define ASM_CPU_POWER8_SPEC "-mpower8" 94 #else 95 #define ASM_CPU_POWER8_SPEC ASM_CPU_POWER7_SPEC 96 #endif 97 98 #ifdef HAVE_AS_DCI 99 #define ASM_CPU_476_SPEC "-m476" 100 #else 101 #define ASM_CPU_476_SPEC "-mpower4" 102 #endif 103 104 /* Common ASM definitions used by ASM_SPEC among the various targets for 105 handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to 106 provide the default assembler options if the user uses -mcpu=native, so if 107 you make changes here, make them also there. */ 108 #define ASM_CPU_SPEC \ 109 "%{!mcpu*: \ 110 %{mpowerpc64*: -mppc64} \ 111 %{!mpowerpc64*: %(asm_default)}} \ 112 %{mcpu=native: %(asm_cpu_native)} \ 113 %{mcpu=cell: -mcell} \ 114 %{mcpu=power3: -mppc64} \ 115 %{mcpu=power4: -mpower4} \ 116 %{mcpu=power5: %(asm_cpu_power5)} \ 117 %{mcpu=power5+: %(asm_cpu_power5)} \ 118 %{mcpu=power6: %(asm_cpu_power6) -maltivec} \ 119 %{mcpu=power6x: %(asm_cpu_power6) -maltivec} \ 120 %{mcpu=power7: %(asm_cpu_power7)} \ 121 %{mcpu=power8: %(asm_cpu_power8)} \ 122 %{mcpu=a2: -ma2} \ 123 %{mcpu=powerpc: -mppc} \ 124 %{mcpu=rs64a: -mppc64} \ 125 %{mcpu=401: -mppc} \ 126 %{mcpu=403: -m403} \ 127 %{mcpu=405: -m405} \ 128 %{mcpu=405fp: -m405} \ 129 %{mcpu=440: -m440} \ 130 %{mcpu=440fp: -m440} \ 131 %{mcpu=464: -m440} \ 132 %{mcpu=464fp: -m440} \ 133 %{mcpu=476: %(asm_cpu_476)} \ 134 %{mcpu=476fp: %(asm_cpu_476)} \ 135 %{mcpu=505: -mppc} \ 136 %{mcpu=601: -m601} \ 137 %{mcpu=602: -mppc} \ 138 %{mcpu=603: -mppc} \ 139 %{mcpu=603e: -mppc} \ 140 %{mcpu=ec603e: -mppc} \ 141 %{mcpu=604: -mppc} \ 142 %{mcpu=604e: -mppc} \ 143 %{mcpu=620: -mppc64} \ 144 %{mcpu=630: -mppc64} \ 145 %{mcpu=740: -mppc} \ 146 %{mcpu=750: -mppc} \ 147 %{mcpu=G3: -mppc} \ 148 %{mcpu=7400: -mppc -maltivec} \ 149 %{mcpu=7450: -mppc -maltivec} \ 150 %{mcpu=G4: -mppc -maltivec} \ 151 %{mcpu=801: -mppc} \ 152 %{mcpu=821: -mppc} \ 153 %{mcpu=823: -mppc} \ 154 %{mcpu=860: -mppc} \ 155 %{mcpu=970: -mpower4 -maltivec} \ 156 %{mcpu=G5: -mpower4 -maltivec} \ 157 %{mcpu=8540: -me500} \ 158 %{mcpu=8548: -me500} \ 159 %{mcpu=e300c2: -me300} \ 160 %{mcpu=e300c3: -me300} \ 161 %{mcpu=e500mc: -me500mc} \ 162 %{mcpu=e500mc64: -me500mc64} \ 163 %{mcpu=e5500: -me5500} \ 164 %{mcpu=e6500: -me6500} \ 165 %{maltivec: -maltivec} \ 166 %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \ 167 %{mpower8-vector|mcrypto|mdirect-move|mhtm: %{!mcpu*: %(asm_cpu_power8)}} \ 168 -many" 169 170 #define CPP_DEFAULT_SPEC "" 171 172 #define ASM_DEFAULT_SPEC "" 173 174 /* This macro defines names of additional specifications to put in the specs 175 that can be used in various specifications like CC1_SPEC. Its definition 176 is an initializer with a subgrouping for each command option. 177 178 Each subgrouping contains a string constant, that defines the 179 specification name, and a string constant that used by the GCC driver 180 program. 181 182 Do not define this macro if it does not need to do anything. */ 183 184 #define SUBTARGET_EXTRA_SPECS 185 186 #define EXTRA_SPECS \ 187 { "cpp_default", CPP_DEFAULT_SPEC }, \ 188 { "asm_cpu", ASM_CPU_SPEC }, \ 189 { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \ 190 { "asm_default", ASM_DEFAULT_SPEC }, \ 191 { "cc1_cpu", CC1_CPU_SPEC }, \ 192 { "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \ 193 { "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \ 194 { "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \ 195 { "asm_cpu_power8", ASM_CPU_POWER8_SPEC }, \ 196 { "asm_cpu_476", ASM_CPU_476_SPEC }, \ 197 SUBTARGET_EXTRA_SPECS 198 199 /* -mcpu=native handling only makes sense with compiler running on 200 an PowerPC chip. If changing this condition, also change 201 the condition in driver-rs6000.c. */ 202 #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX) 203 /* In driver-rs6000.c. */ 204 extern const char *host_detect_local_cpu (int argc, const char **argv); 205 #define EXTRA_SPEC_FUNCTIONS \ 206 { "local_cpu_detect", host_detect_local_cpu }, 207 #define HAVE_LOCAL_CPU_DETECT 208 #define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)" 209 210 #else 211 #define ASM_CPU_NATIVE_SPEC "%(asm_default)" 212 #endif 213 214 #ifndef CC1_CPU_SPEC 215 #ifdef HAVE_LOCAL_CPU_DETECT 216 #define CC1_CPU_SPEC \ 217 "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \ 218 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 219 #else 220 #define CC1_CPU_SPEC "" 221 #endif 222 #endif 223 224 /* Architecture type. */ 225 226 /* Define TARGET_MFCRF if the target assembler does not support the 227 optional field operand for mfcr. */ 228 229 #ifndef HAVE_AS_MFCRF 230 #undef TARGET_MFCRF 231 #define TARGET_MFCRF 0 232 #endif 233 234 /* Define TARGET_POPCNTB if the target assembler does not support the 235 popcount byte instruction. */ 236 237 #ifndef HAVE_AS_POPCNTB 238 #undef TARGET_POPCNTB 239 #define TARGET_POPCNTB 0 240 #endif 241 242 /* Define TARGET_FPRND if the target assembler does not support the 243 fp rounding instructions. */ 244 245 #ifndef HAVE_AS_FPRND 246 #undef TARGET_FPRND 247 #define TARGET_FPRND 0 248 #endif 249 250 /* Define TARGET_CMPB if the target assembler does not support the 251 cmpb instruction. */ 252 253 #ifndef HAVE_AS_CMPB 254 #undef TARGET_CMPB 255 #define TARGET_CMPB 0 256 #endif 257 258 /* Define TARGET_MFPGPR if the target assembler does not support the 259 mffpr and mftgpr instructions. */ 260 261 #ifndef HAVE_AS_MFPGPR 262 #undef TARGET_MFPGPR 263 #define TARGET_MFPGPR 0 264 #endif 265 266 /* Define TARGET_DFP if the target assembler does not support decimal 267 floating point instructions. */ 268 #ifndef HAVE_AS_DFP 269 #undef TARGET_DFP 270 #define TARGET_DFP 0 271 #endif 272 273 /* Define TARGET_POPCNTD if the target assembler does not support the 274 popcount word and double word instructions. */ 275 276 #ifndef HAVE_AS_POPCNTD 277 #undef TARGET_POPCNTD 278 #define TARGET_POPCNTD 0 279 #endif 280 281 /* Define the ISA 2.07 flags as 0 if the target assembler does not support the 282 waitasecond instruction. Allow -mpower8-fusion, since it does not add new 283 instructions. */ 284 285 #ifndef HAVE_AS_POWER8 286 #undef TARGET_DIRECT_MOVE 287 #undef TARGET_CRYPTO 288 #undef TARGET_HTM 289 #undef TARGET_P8_VECTOR 290 #define TARGET_DIRECT_MOVE 0 291 #define TARGET_CRYPTO 0 292 #define TARGET_HTM 0 293 #define TARGET_P8_VECTOR 0 294 #endif 295 296 /* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If 297 not, generate the lwsync code as an integer constant. */ 298 #ifdef HAVE_AS_LWSYNC 299 #define TARGET_LWSYNC_INSTRUCTION 1 300 #else 301 #define TARGET_LWSYNC_INSTRUCTION 0 302 #endif 303 304 /* Define TARGET_TLS_MARKERS if the target assembler does not support 305 arg markers for __tls_get_addr calls. */ 306 #ifndef HAVE_AS_TLS_MARKERS 307 #undef TARGET_TLS_MARKERS 308 #define TARGET_TLS_MARKERS 0 309 #else 310 #define TARGET_TLS_MARKERS tls_markers 311 #endif 312 313 #ifndef TARGET_SECURE_PLT 314 #define TARGET_SECURE_PLT 0 315 #endif 316 317 #ifndef TARGET_CMODEL 318 #define TARGET_CMODEL CMODEL_SMALL 319 #endif 320 321 #define TARGET_32BIT (! TARGET_64BIT) 322 323 #ifndef HAVE_AS_TLS 324 #define HAVE_AS_TLS 0 325 #endif 326 327 #ifndef TARGET_LINK_STACK 328 #define TARGET_LINK_STACK 0 329 #endif 330 331 #ifndef SET_TARGET_LINK_STACK 332 #define SET_TARGET_LINK_STACK(X) do { } while (0) 333 #endif 334 335 /* Return 1 for a symbol ref for a thread-local storage symbol. */ 336 #define RS6000_SYMBOL_REF_TLS_P(RTX) \ 337 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) 338 339 #ifdef IN_LIBGCC2 340 /* For libgcc2 we make sure this is a compile time constant */ 341 #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__) 342 #undef TARGET_POWERPC64 343 #define TARGET_POWERPC64 1 344 #else 345 #undef TARGET_POWERPC64 346 #define TARGET_POWERPC64 0 347 #endif 348 #else 349 /* The option machinery will define this. */ 350 #endif 351 352 #define TARGET_DEFAULT (MASK_MULTIPLE | MASK_STRING) 353 354 /* FPU operations supported. 355 Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must 356 also test TARGET_HARD_FLOAT. */ 357 #define TARGET_SINGLE_FLOAT 1 358 #define TARGET_DOUBLE_FLOAT 1 359 #define TARGET_SINGLE_FPU 0 360 #define TARGET_SIMPLE_FPU 0 361 #define TARGET_XILINX_FPU 0 362 363 /* Recast the processor type to the cpu attribute. */ 364 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu) 365 366 /* Define generic processor types based upon current deployment. */ 367 #define PROCESSOR_COMMON PROCESSOR_PPC601 368 #define PROCESSOR_POWERPC PROCESSOR_PPC604 369 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A 370 371 /* Define the default processor. This is overridden by other tm.h files. */ 372 #define PROCESSOR_DEFAULT PROCESSOR_PPC603 373 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A 374 375 /* Specify the dialect of assembler to use. Only new mnemonics are supported 376 starting with GCC 4.8, i.e. just one dialect, but for backwards 377 compatibility with older inline asm ASSEMBLER_DIALECT needs to be 378 defined. */ 379 #define ASSEMBLER_DIALECT 1 380 381 /* Debug support */ 382 #define MASK_DEBUG_STACK 0x01 /* debug stack applications */ 383 #define MASK_DEBUG_ARG 0x02 /* debug argument handling */ 384 #define MASK_DEBUG_REG 0x04 /* debug register handling */ 385 #define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */ 386 #define MASK_DEBUG_COST 0x10 /* debug rtx codes */ 387 #define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */ 388 #define MASK_DEBUG_BUILTIN 0x40 /* debug builtins */ 389 #define MASK_DEBUG_ALL (MASK_DEBUG_STACK \ 390 | MASK_DEBUG_ARG \ 391 | MASK_DEBUG_REG \ 392 | MASK_DEBUG_ADDR \ 393 | MASK_DEBUG_COST \ 394 | MASK_DEBUG_TARGET \ 395 | MASK_DEBUG_BUILTIN) 396 397 #define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK) 398 #define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG) 399 #define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG) 400 #define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR) 401 #define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST) 402 #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET) 403 #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN) 404 405 /* Describe the vector unit used for arithmetic operations. */ 406 extern enum rs6000_vector rs6000_vector_unit[]; 407 408 #define VECTOR_UNIT_NONE_P(MODE) \ 409 (rs6000_vector_unit[(MODE)] == VECTOR_NONE) 410 411 #define VECTOR_UNIT_VSX_P(MODE) \ 412 (rs6000_vector_unit[(MODE)] == VECTOR_VSX) 413 414 #define VECTOR_UNIT_P8_VECTOR_P(MODE) \ 415 (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR) 416 417 #define VECTOR_UNIT_ALTIVEC_P(MODE) \ 418 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC) 419 420 #define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \ 421 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ 422 (int)VECTOR_VSX, \ 423 (int)VECTOR_P8_VECTOR)) 424 425 /* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either 426 altivec (VMX) or VSX vector instructions. P8 vector support is upwards 427 compatible, so allow it as well, rather than changing all of the uses of the 428 macro. */ 429 #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \ 430 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ 431 (int)VECTOR_ALTIVEC, \ 432 (int)VECTOR_P8_VECTOR)) 433 434 /* Describe whether to use VSX loads or Altivec loads. For now, just use the 435 same unit as the vector unit we are using, but we may want to migrate to 436 using VSX style loads even for types handled by altivec. */ 437 extern enum rs6000_vector rs6000_vector_mem[]; 438 439 #define VECTOR_MEM_NONE_P(MODE) \ 440 (rs6000_vector_mem[(MODE)] == VECTOR_NONE) 441 442 #define VECTOR_MEM_VSX_P(MODE) \ 443 (rs6000_vector_mem[(MODE)] == VECTOR_VSX) 444 445 #define VECTOR_MEM_P8_VECTOR_P(MODE) \ 446 (rs6000_vector_mem[(MODE)] == VECTOR_VSX) 447 448 #define VECTOR_MEM_ALTIVEC_P(MODE) \ 449 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC) 450 451 #define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \ 452 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ 453 (int)VECTOR_VSX, \ 454 (int)VECTOR_P8_VECTOR)) 455 456 #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \ 457 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ 458 (int)VECTOR_ALTIVEC, \ 459 (int)VECTOR_P8_VECTOR)) 460 461 /* Return the alignment of a given vector type, which is set based on the 462 vector unit use. VSX for instance can load 32 or 64 bit aligned words 463 without problems, while Altivec requires 128-bit aligned vectors. */ 464 extern int rs6000_vector_align[]; 465 466 #define VECTOR_ALIGN(MODE) \ 467 ((rs6000_vector_align[(MODE)] != 0) \ 468 ? rs6000_vector_align[(MODE)] \ 469 : (int)GET_MODE_BITSIZE ((MODE))) 470 471 /* Determine the element order to use for vector instructions. By 472 default we use big-endian element order when targeting big-endian, 473 and little-endian element order when targeting little-endian. For 474 programs being ported from BE Power to LE Power, it can sometimes 475 be useful to use big-endian element order when targeting little-endian. 476 This is set via -maltivec=be, for example. */ 477 #define VECTOR_ELT_ORDER_BIG \ 478 (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2)) 479 480 /* Element number of the 64-bit value in a 128-bit vector that can be accessed 481 with scalar instructions. */ 482 #define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1) 483 484 /* Alignment options for fields in structures for sub-targets following 485 AIX-like ABI. 486 ALIGN_POWER word-aligns FP doubles (default AIX ABI). 487 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size). 488 489 Override the macro definitions when compiling libobjc to avoid undefined 490 reference to rs6000_alignment_flags due to library's use of GCC alignment 491 macros which use the macros below. */ 492 493 #ifndef IN_TARGET_LIBS 494 #define MASK_ALIGN_POWER 0x00000000 495 #define MASK_ALIGN_NATURAL 0x00000001 496 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL) 497 #else 498 #define TARGET_ALIGN_NATURAL 0 499 #endif 500 501 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128) 502 #define TARGET_IEEEQUAD rs6000_ieeequad 503 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi 504 #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL) 505 506 #define TARGET_SPE_ABI 0 507 #define TARGET_SPE 0 508 #define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64) 509 #define TARGET_FPRS 1 510 #define TARGET_E500_SINGLE 0 511 #define TARGET_E500_DOUBLE 0 512 #define CHECK_E500_OPTIONS do { } while (0) 513 514 /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only. 515 Enable 32-bit fcfid's on any of the switches for newer ISA machines or 516 XILINX. */ 517 #define TARGET_FCFID (TARGET_POWERPC64 \ 518 || TARGET_PPC_GPOPT /* 970/power4 */ \ 519 || TARGET_POPCNTB /* ISA 2.02 */ \ 520 || TARGET_CMPB /* ISA 2.05 */ \ 521 || TARGET_POPCNTD /* ISA 2.06 */ \ 522 || TARGET_XILINX_FPU) 523 524 #define TARGET_FCTIDZ TARGET_FCFID 525 #define TARGET_STFIWX TARGET_PPC_GFXOPT 526 #define TARGET_LFIWAX TARGET_CMPB 527 #define TARGET_LFIWZX TARGET_POPCNTD 528 #define TARGET_FCFIDS TARGET_POPCNTD 529 #define TARGET_FCFIDU TARGET_POPCNTD 530 #define TARGET_FCFIDUS TARGET_POPCNTD 531 #define TARGET_FCTIDUZ TARGET_POPCNTD 532 #define TARGET_FCTIWUZ TARGET_POPCNTD 533 534 #define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) 535 #define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) 536 #define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64) 537 538 /* Byte/char syncs were added as phased in for ISA 2.06B, but are not present 539 in power7, so conditionalize them on p8 features. TImode syncs need quad 540 memory support. */ 541 #define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \ 542 || TARGET_QUAD_MEMORY_ATOMIC \ 543 || TARGET_DIRECT_MOVE) 544 545 #define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC 546 547 /* Power7 has both 32-bit load and store integer for the FPRs, so we don't need 548 to allocate the SDmode stack slot to get the value into the proper location 549 in the register. */ 550 #define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP) 551 552 /* In switching from using target_flags to using rs6000_isa_flags, the options 553 machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map 554 OPTION_MASK_<xxx> back into MASK_<xxx>. */ 555 #define MASK_ALTIVEC OPTION_MASK_ALTIVEC 556 #define MASK_CMPB OPTION_MASK_CMPB 557 #define MASK_CRYPTO OPTION_MASK_CRYPTO 558 #define MASK_DFP OPTION_MASK_DFP 559 #define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE 560 #define MASK_DLMZB OPTION_MASK_DLMZB 561 #define MASK_EABI OPTION_MASK_EABI 562 #define MASK_FPRND OPTION_MASK_FPRND 563 #define MASK_P8_FUSION OPTION_MASK_P8_FUSION 564 #define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT 565 #define MASK_HTM OPTION_MASK_HTM 566 #define MASK_ISEL OPTION_MASK_ISEL 567 #define MASK_MFCRF OPTION_MASK_MFCRF 568 #define MASK_MFPGPR OPTION_MASK_MFPGPR 569 #define MASK_MULHW OPTION_MASK_MULHW 570 #define MASK_MULTIPLE OPTION_MASK_MULTIPLE 571 #define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE 572 #define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR 573 #define MASK_POPCNTB OPTION_MASK_POPCNTB 574 #define MASK_POPCNTD OPTION_MASK_POPCNTD 575 #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT 576 #define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT 577 #define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION 578 #define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT 579 #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN 580 #define MASK_STRING OPTION_MASK_STRING 581 #define MASK_UPDATE OPTION_MASK_UPDATE 582 #define MASK_VSX OPTION_MASK_VSX 583 #define MASK_VSX_TIMODE OPTION_MASK_VSX_TIMODE 584 585 #ifndef IN_LIBGCC2 586 #define MASK_POWERPC64 OPTION_MASK_POWERPC64 587 #endif 588 589 #ifdef TARGET_64BIT 590 #define MASK_64BIT OPTION_MASK_64BIT 591 #endif 592 593 #ifdef TARGET_RELOCATABLE 594 #define MASK_RELOCATABLE OPTION_MASK_RELOCATABLE 595 #endif 596 597 #ifdef TARGET_LITTLE_ENDIAN 598 #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN 599 #endif 600 601 #ifdef TARGET_MINIMAL_TOC 602 #define MASK_MINIMAL_TOC OPTION_MASK_MINIMAL_TOC 603 #endif 604 605 #ifdef TARGET_REGNAMES 606 #define MASK_REGNAMES OPTION_MASK_REGNAMES 607 #endif 608 609 #ifdef TARGET_PROTOTYPE 610 #define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE 611 #endif 612 613 /* For power systems, we want to enable Altivec and VSX builtins even if the 614 user did not use -maltivec or -mvsx to allow the builtins to be used inside 615 of #pragma GCC target or the target attribute to change the code level for a 616 given system. The SPE and Paired builtins are only enabled if you configure 617 the compiler for those builtins, and those machines don't support altivec or 618 VSX. */ 619 620 #define TARGET_EXTRA_BUILTINS (!TARGET_SPE && !TARGET_PAIRED_FLOAT \ 621 && ((TARGET_POWERPC64 \ 622 || TARGET_PPC_GPOPT /* 970/power4 */ \ 623 || TARGET_POPCNTB /* ISA 2.02 */ \ 624 || TARGET_CMPB /* ISA 2.05 */ \ 625 || TARGET_POPCNTD /* ISA 2.06 */ \ 626 || TARGET_ALTIVEC \ 627 || TARGET_VSX \ 628 || TARGET_HARD_FLOAT))) 629 630 /* E500 cores only support plain "sync", not lwsync. */ 631 #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \ 632 || rs6000_cpu == PROCESSOR_PPC8548) 633 634 635 /* Whether SF/DF operations are supported on the E500. */ 636 #define TARGET_SF_SPE (TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT \ 637 && !TARGET_FPRS) 638 639 #define TARGET_DF_SPE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \ 640 && !TARGET_FPRS && TARGET_E500_DOUBLE) 641 642 /* Whether SF/DF operations are supported by by the normal floating point unit 643 (or the vector/scalar unit). */ 644 #define TARGET_SF_FPR (TARGET_HARD_FLOAT && TARGET_FPRS \ 645 && TARGET_SINGLE_FLOAT) 646 647 #define TARGET_DF_FPR (TARGET_HARD_FLOAT && TARGET_FPRS \ 648 && TARGET_DOUBLE_FLOAT) 649 650 /* Whether SF/DF operations are supported by any hardware. */ 651 #define TARGET_SF_INSN (TARGET_SF_FPR || TARGET_SF_SPE) 652 #define TARGET_DF_INSN (TARGET_DF_FPR || TARGET_DF_SPE) 653 654 /* Which machine supports the various reciprocal estimate instructions. */ 655 #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ 656 && TARGET_FPRS && TARGET_SINGLE_FLOAT) 657 658 #define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_FPRS \ 659 && TARGET_DOUBLE_FLOAT \ 660 && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode))) 661 662 #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \ 663 && TARGET_FPRS && TARGET_SINGLE_FLOAT) 664 665 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_FPRS \ 666 && TARGET_DOUBLE_FLOAT \ 667 && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode))) 668 669 /* Whether the various reciprocal divide/square root estimate instructions 670 exist, and whether we should automatically generate code for the instruction 671 by default. */ 672 #define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */ 673 #define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */ 674 #define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */ 675 #define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */ 676 677 extern unsigned char rs6000_recip_bits[]; 678 679 #define RS6000_RECIP_HAVE_RE_P(MODE) \ 680 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE) 681 682 #define RS6000_RECIP_AUTO_RE_P(MODE) \ 683 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE) 684 685 #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \ 686 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE) 687 688 #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \ 689 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE) 690 691 /* The default CPU for TARGET_OPTION_OVERRIDE. */ 692 #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT 693 694 /* Target pragma. */ 695 #define REGISTER_TARGET_PRAGMAS() do { \ 696 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \ 697 targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \ 698 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \ 699 rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \ 700 } while (0) 701 702 /* Target #defines. */ 703 #define TARGET_CPU_CPP_BUILTINS() \ 704 rs6000_cpu_cpp_builtins (pfile) 705 706 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order 707 we're compiling for. Some configurations may need to override it. */ 708 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \ 709 do \ 710 { \ 711 if (BYTES_BIG_ENDIAN) \ 712 { \ 713 builtin_define ("__BIG_ENDIAN__"); \ 714 builtin_define ("_BIG_ENDIAN"); \ 715 builtin_assert ("machine=bigendian"); \ 716 } \ 717 else \ 718 { \ 719 builtin_define ("__LITTLE_ENDIAN__"); \ 720 builtin_define ("_LITTLE_ENDIAN"); \ 721 builtin_assert ("machine=littleendian"); \ 722 } \ 723 } \ 724 while (0) 725 726 /* Target machine storage layout. */ 727 728 /* Define this macro if it is advisable to hold scalars in registers 729 in a wider mode than that declared by the program. In such cases, 730 the value is constrained to be within the bounds of the declared 731 type, but kept valid in the wider mode. The signedness of the 732 extension may differ from that of the type. */ 733 734 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 735 if (GET_MODE_CLASS (MODE) == MODE_INT \ 736 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 737 (MODE) = TARGET_32BIT ? SImode : DImode; 738 739 /* Define this if most significant bit is lowest numbered 740 in instructions that operate on numbered bit-fields. */ 741 /* That is true on RS/6000. */ 742 #define BITS_BIG_ENDIAN 1 743 744 /* Define this if most significant byte of a word is the lowest numbered. */ 745 /* That is true on RS/6000. */ 746 #define BYTES_BIG_ENDIAN 1 747 748 /* Define this if most significant word of a multiword number is lowest 749 numbered. 750 751 For RS/6000 we can decide arbitrarily since there are no machine 752 instructions for them. Might as well be consistent with bits and bytes. */ 753 #define WORDS_BIG_ENDIAN 1 754 755 /* This says that for the IBM long double the larger magnitude double 756 comes first. It's really a two element double array, and arrays 757 don't index differently between little- and big-endian. */ 758 #define LONG_DOUBLE_LARGE_FIRST 1 759 760 #define MAX_BITS_PER_WORD 64 761 762 /* Width of a word, in units (bytes). */ 763 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8) 764 #ifdef IN_LIBGCC2 765 #define MIN_UNITS_PER_WORD UNITS_PER_WORD 766 #else 767 #define MIN_UNITS_PER_WORD 4 768 #endif 769 #define UNITS_PER_FP_WORD 8 770 #define UNITS_PER_ALTIVEC_WORD 16 771 #define UNITS_PER_VSX_WORD 16 772 #define UNITS_PER_SPE_WORD 8 773 #define UNITS_PER_PAIRED_WORD 8 774 775 /* Type used for ptrdiff_t, as a string used in a declaration. */ 776 #define PTRDIFF_TYPE "int" 777 778 /* Type used for size_t, as a string used in a declaration. */ 779 #define SIZE_TYPE "long unsigned int" 780 781 /* Type used for wchar_t, as a string used in a declaration. */ 782 #define WCHAR_TYPE "short unsigned int" 783 784 /* Width of wchar_t in bits. */ 785 #define WCHAR_TYPE_SIZE 16 786 787 /* A C expression for the size in bits of the type `short' on the 788 target machine. If you don't define this, the default is half a 789 word. (If this would be less than one storage unit, it is 790 rounded up to one unit.) */ 791 #define SHORT_TYPE_SIZE 16 792 793 /* A C expression for the size in bits of the type `int' on the 794 target machine. If you don't define this, the default is one 795 word. */ 796 #define INT_TYPE_SIZE 32 797 798 /* A C expression for the size in bits of the type `long' on the 799 target machine. If you don't define this, the default is one 800 word. */ 801 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64) 802 803 /* A C expression for the size in bits of the type `long long' on the 804 target machine. If you don't define this, the default is two 805 words. */ 806 #define LONG_LONG_TYPE_SIZE 64 807 808 /* A C expression for the size in bits of the type `float' on the 809 target machine. If you don't define this, the default is one 810 word. */ 811 #define FLOAT_TYPE_SIZE 32 812 813 /* A C expression for the size in bits of the type `double' on the 814 target machine. If you don't define this, the default is two 815 words. */ 816 #define DOUBLE_TYPE_SIZE 64 817 818 /* A C expression for the size in bits of the type `long double' on 819 the target machine. If you don't define this, the default is two 820 words. */ 821 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size 822 823 /* Define this to set long double type size to use in libgcc2.c, which can 824 not depend on target_flags. */ 825 #ifdef __LONG_DOUBLE_128__ 826 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 827 #else 828 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 829 #endif 830 831 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */ 832 #define WIDEST_HARDWARE_FP_SIZE 64 833 834 /* Width in bits of a pointer. 835 See also the macro `Pmode' defined below. */ 836 extern unsigned rs6000_pointer_size; 837 #define POINTER_SIZE rs6000_pointer_size 838 839 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 840 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64) 841 842 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 843 #define STACK_BOUNDARY \ 844 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \ 845 ? 64 : 128) 846 847 /* Allocation boundary (in *bits*) for the code of a function. */ 848 #define FUNCTION_BOUNDARY 32 849 850 /* No data type wants to be aligned rounder than this. */ 851 #define BIGGEST_ALIGNMENT 128 852 853 /* Alignment of field after `int : 0' in a structure. */ 854 #define EMPTY_FIELD_BOUNDARY 32 855 856 /* Every structure's size must be a multiple of this. */ 857 #define STRUCTURE_SIZE_BOUNDARY 8 858 859 /* A bit-field declared as `int' forces `int' alignment for the struct. */ 860 #define PCC_BITFIELD_TYPE_MATTERS 1 861 862 enum data_align { align_abi, align_opt, align_both }; 863 864 /* A C expression to compute the alignment for a variables in the 865 local store. TYPE is the data type, and ALIGN is the alignment 866 that the object would ordinarily have. */ 867 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 868 rs6000_data_alignment (TYPE, ALIGN, align_both) 869 870 /* Make strings word-aligned so strcpy from constants will be faster. */ 871 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 872 (TREE_CODE (EXP) == STRING_CST \ 873 && (STRICT_ALIGNMENT || !optimize_size) \ 874 && (ALIGN) < BITS_PER_WORD \ 875 ? BITS_PER_WORD \ 876 : (ALIGN)) 877 878 /* Make arrays of chars word-aligned for the same reasons. */ 879 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 880 rs6000_data_alignment (TYPE, ALIGN, align_opt) 881 882 /* Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to 883 64 bits. */ 884 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \ 885 rs6000_data_alignment (TYPE, ALIGN, align_abi) 886 887 /* Nonzero if move instructions will actually fail to work 888 when given unaligned data. */ 889 #define STRICT_ALIGNMENT 0 890 891 /* Define this macro to be the value 1 if unaligned accesses have a cost 892 many times greater than aligned accesses, for example if they are 893 emulated in a trap handler. */ 894 /* Altivec vector memory instructions simply ignore the low bits; SPE vector 895 memory instructions trap on unaligned accesses; VSX memory instructions are 896 aligned to 4 or 8 bytes. */ 897 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \ 898 (STRICT_ALIGNMENT \ 899 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \ 900 || (MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode) \ 901 && (ALIGN) < 32) \ 902 || (VECTOR_MODE_P ((MODE)) && (((int)(ALIGN)) < VECTOR_ALIGN (MODE)))) 903 904 905 /* Standard register usage. */ 906 907 /* Number of actual hardware registers. 908 The hardware registers are assigned numbers for the compiler 909 from 0 to just below FIRST_PSEUDO_REGISTER. 910 All registers that the compiler knows about must be given numbers, 911 even those that are not normally considered general registers. 912 913 RS/6000 has 32 fixed-point registers, 32 floating-point registers, 914 a count register, a link register, and 8 condition register fields, 915 which we view here as separate registers. AltiVec adds 32 vector 916 registers and a VRsave register. 917 918 In addition, the difference between the frame and argument pointers is 919 a function of the number of registers saved, so we need to have a 920 register for AP that will later be eliminated in favor of SP or FP. 921 This is a normal register, but it is fixed. 922 923 We also create a pseudo register for float/int conversions, that will 924 really represent the memory location used. It is represented here as 925 a register, in order to work around problems in allocating stack storage 926 in inline functions. 927 928 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame 929 pointer, which is eventually eliminated in favor of SP or FP. 930 931 The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */ 932 933 #define FIRST_PSEUDO_REGISTER 149 934 935 /* This must be included for pre gcc 3.0 glibc compatibility. */ 936 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77 937 938 /* True if register is an SPE High register. */ 939 #define SPE_HIGH_REGNO_P(N) \ 940 ((N) >= FIRST_SPE_HIGH_REGNO && (N) <= LAST_SPE_HIGH_REGNO) 941 942 /* SPE high registers added as hard regs. 943 The sfp register and 3 HTM registers 944 aren't included in DWARF_FRAME_REGISTERS. */ 945 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4) 946 947 /* The SPE has an additional 32 synthetic registers, with DWARF debug 948 info numbering for these registers starting at 1200. While eh_frame 949 register numbering need not be the same as the debug info numbering, 950 we choose to number these regs for eh_frame at 1200 too. 951 952 We must map them here to avoid huge unwinder tables mostly consisting 953 of unused space. */ 954 #define DWARF_REG_TO_UNWIND_COLUMN(r) \ 955 ((r) >= 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r)) 956 957 /* Use standard DWARF numbering for DWARF debugging information. */ 958 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO) 959 960 /* Use gcc hard register numbering for eh_frame. */ 961 #define DWARF_FRAME_REGNUM(REGNO) \ 962 (SPE_HIGH_REGNO_P (REGNO) ? ((REGNO) - FIRST_SPE_HIGH_REGNO + 1200) : (REGNO)) 963 964 /* Map register numbers held in the call frame info that gcc has 965 collected using DWARF_FRAME_REGNUM to those that should be output in 966 .debug_frame and .eh_frame. We continue to use gcc hard reg numbers 967 for .eh_frame, but use the numbers mandated by the various ABIs for 968 .debug_frame. rs6000_emit_prologue has translated any combination of 969 CR2, CR3, CR4 saves to a save of CR2. The actual code emitted saves 970 the whole of CR, so we map CR2_REGNO to the DWARF reg for CR. */ 971 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \ 972 ((FOR_EH) ? (REGNO) \ 973 : (REGNO) == CR2_REGNO ? 64 \ 974 : DBX_REGISTER_NUMBER (REGNO)) 975 976 /* 1 for registers that have pervasive standard uses 977 and are not available for the register allocator. 978 979 On RS/6000, r1 is used for the stack. On Darwin, r2 is available 980 as a local register; for all other OS's r2 is the TOC pointer. 981 982 cr5 is not supposed to be used. 983 984 On System V implementations, r13 is fixed and not available for use. */ 985 986 #define FIXED_REGISTERS \ 987 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ 988 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 989 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 990 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 991 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \ 992 /* AltiVec registers. */ \ 993 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 994 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 995 1, 1 \ 996 , 1, 1, 1, 1, 1, 1, \ 997 /* SPE High registers. */ \ 998 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 999 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ 1000 } 1001 1002 /* 1 for registers not available across function calls. 1003 These must include the FIXED_REGISTERS and also any 1004 registers that can be used without being saved. 1005 The latter must include the registers where values are returned 1006 and the register where structure-value addresses are passed. 1007 Aside from that, you can include as many other registers as you like. */ 1008 1009 #define CALL_USED_REGISTERS \ 1010 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ 1011 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1012 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ 1013 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1014 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ 1015 /* AltiVec registers. */ \ 1016 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1017 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1018 1, 1 \ 1019 , 1, 1, 1, 1, 1, 1, \ 1020 /* SPE High registers. */ \ 1021 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1022 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ 1023 } 1024 1025 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that 1026 the entire set of `FIXED_REGISTERS' be included. 1027 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS'). 1028 This macro is optional. If not specified, it defaults to the value 1029 of `CALL_USED_REGISTERS'. */ 1030 1031 #define CALL_REALLY_USED_REGISTERS \ 1032 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ 1033 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1034 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ 1035 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1036 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ 1037 /* AltiVec registers. */ \ 1038 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1039 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1040 0, 0 \ 1041 , 0, 0, 0, 0, 0, 0, \ 1042 /* SPE High registers. */ \ 1043 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1044 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \ 1045 } 1046 1047 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) 1048 1049 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20) 1050 #define FIRST_SAVED_FP_REGNO (14+32) 1051 #define FIRST_SAVED_GP_REGNO (FIXED_R13 ? 14 : 13) 1052 1053 /* List the order in which to allocate registers. Each register must be 1054 listed once, even those in FIXED_REGISTERS. 1055 1056 We allocate in the following order: 1057 fp0 (not saved or used for anything) 1058 fp13 - fp2 (not saved; incoming fp arg registers) 1059 fp1 (not saved; return value) 1060 fp31 - fp14 (saved; order given to save least number) 1061 cr7, cr6 (not saved or special) 1062 cr1 (not saved, but used for FP operations) 1063 cr0 (not saved, but used for arithmetic operations) 1064 cr4, cr3, cr2 (saved) 1065 r9 (not saved; best for TImode) 1066 r10, r8-r4 (not saved; highest first for less conflict with params) 1067 r3 (not saved; return value register) 1068 r11 (not saved; later alloc to help shrink-wrap) 1069 r0 (not saved; cannot be base reg) 1070 r31 - r13 (saved; order given to save least number) 1071 r12 (not saved; if used for DImode or DFmode would use r13) 1072 ctr (not saved; when we have the choice ctr is better) 1073 lr (saved) 1074 cr5, r1, r2, ap, ca (fixed) 1075 v0 - v1 (not saved or used for anything) 1076 v13 - v3 (not saved; incoming vector arg registers) 1077 v2 (not saved; incoming vector arg reg; return value) 1078 v19 - v14 (not saved or used for anything) 1079 v31 - v20 (saved; order given to save least number) 1080 vrsave, vscr (fixed) 1081 spe_acc, spefscr (fixed) 1082 sfp (fixed) 1083 tfhar (fixed) 1084 tfiar (fixed) 1085 texasr (fixed) 1086 */ 1087 1088 #if FIXED_R2 == 1 1089 #define MAYBE_R2_AVAILABLE 1090 #define MAYBE_R2_FIXED 2, 1091 #else 1092 #define MAYBE_R2_AVAILABLE 2, 1093 #define MAYBE_R2_FIXED 1094 #endif 1095 1096 #if FIXED_R13 == 1 1097 #define EARLY_R12 12, 1098 #define LATE_R12 1099 #else 1100 #define EARLY_R12 1101 #define LATE_R12 12, 1102 #endif 1103 1104 #define REG_ALLOC_ORDER \ 1105 {32, \ 1106 /* move fr13 (ie 45) later, so if we need TFmode, it does */ \ 1107 /* not use fr14 which is a saved register. */ \ 1108 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \ 1109 33, \ 1110 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ 1111 50, 49, 48, 47, 46, \ 1112 75, 74, 69, 68, 72, 71, 70, \ 1113 MAYBE_R2_AVAILABLE \ 1114 9, 10, 8, 7, 6, 5, 4, \ 1115 3, EARLY_R12 11, 0, \ 1116 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \ 1117 18, 17, 16, 15, 14, 13, LATE_R12 \ 1118 66, 65, \ 1119 73, 1, MAYBE_R2_FIXED 67, 76, \ 1120 /* AltiVec registers. */ \ 1121 77, 78, \ 1122 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \ 1123 79, \ 1124 96, 95, 94, 93, 92, 91, \ 1125 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \ 1126 109, 110, \ 1127 111, 112, 113, 114, 115, 116, \ 1128 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, \ 1129 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, \ 1130 141, 142, 143, 144, 145, 146, 147, 148 \ 1131 } 1132 1133 /* True if register is floating-point. */ 1134 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63) 1135 1136 /* True if register is a condition register. */ 1137 #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO) 1138 1139 /* True if register is a condition register, but not cr0. */ 1140 #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO) 1141 1142 /* True if register is an integer register. */ 1143 #define INT_REGNO_P(N) \ 1144 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM) 1145 1146 /* SPE SIMD registers are just the GPRs. */ 1147 #define SPE_SIMD_REGNO_P(N) ((N) <= 31) 1148 1149 /* PAIRED SIMD registers are just the FPRs. */ 1150 #define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63) 1151 1152 /* True if register is the CA register. */ 1153 #define CA_REGNO_P(N) ((N) == CA_REGNO) 1154 1155 /* True if register is an AltiVec register. */ 1156 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO) 1157 1158 /* True if register is a VSX register. */ 1159 #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N)) 1160 1161 /* Alternate name for any vector register supporting floating point, no matter 1162 which instruction set(s) are available. */ 1163 #define VFLOAT_REGNO_P(N) \ 1164 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N))) 1165 1166 /* Alternate name for any vector register supporting integer, no matter which 1167 instruction set(s) are available. */ 1168 #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N) 1169 1170 /* Alternate name for any vector register supporting logical operations, no 1171 matter which instruction set(s) are available. Allow GPRs as well as the 1172 vector registers. */ 1173 #define VLOGICAL_REGNO_P(N) \ 1174 (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \ 1175 || (TARGET_VSX && FP_REGNO_P (N))) \ 1176 1177 /* Return number of consecutive hard regs needed starting at reg REGNO 1178 to hold something of mode MODE. */ 1179 1180 #define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs[(MODE)][(REGNO)] 1181 1182 /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate 1183 enough space to account for vectors in FP regs. However, TFmode/TDmode 1184 should not use VSX instructions to do a caller save. */ 1185 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 1186 (TARGET_VSX \ 1187 && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \ 1188 && FP_REGNO_P (REGNO) \ 1189 ? V2DFmode \ 1190 : ((MODE) == TFmode && FP_REGNO_P (REGNO)) \ 1191 ? DFmode \ 1192 : ((MODE) == TDmode && FP_REGNO_P (REGNO)) \ 1193 ? DImode \ 1194 : choose_hard_reg_mode ((REGNO), (NREGS), false)) 1195 1196 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ 1197 (((TARGET_32BIT && TARGET_POWERPC64 \ 1198 && (GET_MODE_SIZE (MODE) > 4) \ 1199 && INT_REGNO_P (REGNO)) ? 1 : 0) \ 1200 || (TARGET_VSX && FP_REGNO_P (REGNO) \ 1201 && GET_MODE_SIZE (MODE) > 8 && ((MODE) != TDmode) \ 1202 && ((MODE) != TFmode))) 1203 1204 #define VSX_VECTOR_MODE(MODE) \ 1205 ((MODE) == V4SFmode \ 1206 || (MODE) == V2DFmode) \ 1207 1208 #define ALTIVEC_VECTOR_MODE(MODE) \ 1209 ((MODE) == V16QImode \ 1210 || (MODE) == V8HImode \ 1211 || (MODE) == V4SFmode \ 1212 || (MODE) == V4SImode) 1213 1214 #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \ 1215 (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \ 1216 || (MODE) == V2DImode || (MODE) == V1TImode) 1217 1218 #define SPE_VECTOR_MODE(MODE) \ 1219 ((MODE) == V4HImode \ 1220 || (MODE) == V2SFmode \ 1221 || (MODE) == V1DImode \ 1222 || (MODE) == V2SImode) 1223 1224 #define PAIRED_VECTOR_MODE(MODE) \ 1225 ((MODE) == V2SFmode) 1226 1227 /* Value is TRUE if hard register REGNO can hold a value of 1228 machine-mode MODE. */ 1229 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1230 rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO] 1231 1232 /* Value is 1 if it is a good idea to tie two pseudo registers 1233 when one has mode MODE1 and one has mode MODE2. 1234 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1235 for any hard reg, then this must be 0 for correct output. 1236 1237 PTImode cannot tie with other modes because PTImode is restricted to even 1238 GPR registers, and TImode can go in any GPR as well as VSX registers (PR 1239 57744). */ 1240 #define MODES_TIEABLE_P(MODE1, MODE2) \ 1241 ((MODE1) == PTImode \ 1242 ? (MODE2) == PTImode \ 1243 : (MODE2) == PTImode \ 1244 ? 0 \ 1245 : SCALAR_FLOAT_MODE_P (MODE1) \ 1246 ? SCALAR_FLOAT_MODE_P (MODE2) \ 1247 : SCALAR_FLOAT_MODE_P (MODE2) \ 1248 ? 0 \ 1249 : GET_MODE_CLASS (MODE1) == MODE_CC \ 1250 ? GET_MODE_CLASS (MODE2) == MODE_CC \ 1251 : GET_MODE_CLASS (MODE2) == MODE_CC \ 1252 ? 0 \ 1253 : SPE_VECTOR_MODE (MODE1) \ 1254 ? SPE_VECTOR_MODE (MODE2) \ 1255 : SPE_VECTOR_MODE (MODE2) \ 1256 ? 0 \ 1257 : ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \ 1258 ? ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \ 1259 : ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \ 1260 ? 0 \ 1261 : 1) 1262 1263 /* Post-reload, we can't use any new AltiVec registers, as we already 1264 emitted the vrsave mask. */ 1265 1266 #define HARD_REGNO_RENAME_OK(SRC, DST) \ 1267 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST)) 1268 1269 /* Specify the cost of a branch insn; roughly the number of extra insns that 1270 should be added to avoid a branch. 1271 1272 Set this to 3 on the RS/6000 since that is roughly the average cost of an 1273 unscheduled conditional branch. */ 1274 1275 #define BRANCH_COST(speed_p, predictable_p) 3 1276 1277 /* Override BRANCH_COST heuristic which empirically produces worse 1278 performance for removing short circuiting from the logical ops. */ 1279 1280 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 1281 1282 /* A fixed register used at epilogue generation to address SPE registers 1283 with negative offsets. The 64-bit load/store instructions on the SPE 1284 only take positive offsets (and small ones at that), so we need to 1285 reserve a register for consing up negative offsets. */ 1286 1287 #define FIXED_SCRATCH 0 1288 1289 /* Specify the registers used for certain standard purposes. 1290 The values of these macros are register numbers. */ 1291 1292 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */ 1293 /* #define PC_REGNUM */ 1294 1295 /* Register to use for pushing function arguments. */ 1296 #define STACK_POINTER_REGNUM 1 1297 1298 /* Base register for access to local variables of the function. */ 1299 #define HARD_FRAME_POINTER_REGNUM 31 1300 1301 /* Base register for access to local variables of the function. */ 1302 #define FRAME_POINTER_REGNUM 113 1303 1304 /* Base register for access to arguments of the function. */ 1305 #define ARG_POINTER_REGNUM 67 1306 1307 /* Place to put static chain when calling a function that requires it. */ 1308 #define STATIC_CHAIN_REGNUM 11 1309 1310 1311 /* Define the classes of registers for register constraints in the 1312 machine description. Also define ranges of constants. 1313 1314 One of the classes must always be named ALL_REGS and include all hard regs. 1315 If there is more than one class, another class must be named NO_REGS 1316 and contain no registers. 1317 1318 The name GENERAL_REGS must be the name of a class (or an alias for 1319 another name such as ALL_REGS). This is the class of registers 1320 that is allowed by "g" or "r" in a register constraint. 1321 Also, registers outside this class are allocated only when 1322 instructions express preferences for them. 1323 1324 The classes must be numbered in nondecreasing order; that is, 1325 a larger-numbered class must never be contained completely 1326 in a smaller-numbered class. 1327 1328 For any two classes, it is very desirable that there be another 1329 class that represents their union. */ 1330 1331 /* The RS/6000 has three types of registers, fixed-point, floating-point, and 1332 condition registers, plus three special registers, CTR, and the link 1333 register. AltiVec adds a vector register class. VSX registers overlap the 1334 FPR registers and the Altivec registers. 1335 1336 However, r0 is special in that it cannot be used as a base register. 1337 So make a class for registers valid as base registers. 1338 1339 Also, cr0 is the only condition code register that can be used in 1340 arithmetic insns, so make a separate class for it. */ 1341 1342 enum reg_class 1343 { 1344 NO_REGS, 1345 BASE_REGS, 1346 GENERAL_REGS, 1347 FLOAT_REGS, 1348 ALTIVEC_REGS, 1349 VSX_REGS, 1350 VRSAVE_REGS, 1351 VSCR_REGS, 1352 SPE_ACC_REGS, 1353 SPEFSCR_REGS, 1354 SPR_REGS, 1355 NON_SPECIAL_REGS, 1356 LINK_REGS, 1357 CTR_REGS, 1358 LINK_OR_CTR_REGS, 1359 SPECIAL_REGS, 1360 SPEC_OR_GEN_REGS, 1361 CR0_REGS, 1362 CR_REGS, 1363 NON_FLOAT_REGS, 1364 CA_REGS, 1365 SPE_HIGH_REGS, 1366 ALL_REGS, 1367 LIM_REG_CLASSES 1368 }; 1369 1370 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1371 1372 /* Give names of register classes as strings for dump file. */ 1373 1374 #define REG_CLASS_NAMES \ 1375 { \ 1376 "NO_REGS", \ 1377 "BASE_REGS", \ 1378 "GENERAL_REGS", \ 1379 "FLOAT_REGS", \ 1380 "ALTIVEC_REGS", \ 1381 "VSX_REGS", \ 1382 "VRSAVE_REGS", \ 1383 "VSCR_REGS", \ 1384 "SPE_ACC_REGS", \ 1385 "SPEFSCR_REGS", \ 1386 "SPR_REGS", \ 1387 "NON_SPECIAL_REGS", \ 1388 "LINK_REGS", \ 1389 "CTR_REGS", \ 1390 "LINK_OR_CTR_REGS", \ 1391 "SPECIAL_REGS", \ 1392 "SPEC_OR_GEN_REGS", \ 1393 "CR0_REGS", \ 1394 "CR_REGS", \ 1395 "NON_FLOAT_REGS", \ 1396 "CA_REGS", \ 1397 "SPE_HIGH_REGS", \ 1398 "ALL_REGS" \ 1399 } 1400 1401 /* Define which registers fit in which classes. 1402 This is an initializer for a vector of HARD_REG_SET 1403 of length N_REG_CLASSES. */ 1404 1405 #define REG_CLASS_CONTENTS \ 1406 { \ 1407 /* NO_REGS. */ \ 1408 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ 1409 /* BASE_REGS. */ \ 1410 { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \ 1411 /* GENERAL_REGS. */ \ 1412 { 0xffffffff, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \ 1413 /* FLOAT_REGS. */ \ 1414 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000 }, \ 1415 /* ALTIVEC_REGS. */ \ 1416 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff, 0x00000000 }, \ 1417 /* VSX_REGS. */ \ 1418 { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff, 0x00000000 }, \ 1419 /* VRSAVE_REGS. */ \ 1420 { 0x00000000, 0x00000000, 0x00000000, 0x00002000, 0x00000000 }, \ 1421 /* VSCR_REGS. */ \ 1422 { 0x00000000, 0x00000000, 0x00000000, 0x00004000, 0x00000000 }, \ 1423 /* SPE_ACC_REGS. */ \ 1424 { 0x00000000, 0x00000000, 0x00000000, 0x00008000, 0x00000000 }, \ 1425 /* SPEFSCR_REGS. */ \ 1426 { 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000 }, \ 1427 /* SPR_REGS. */ \ 1428 { 0x00000000, 0x00000000, 0x00000000, 0x00040000, 0x00000000 }, \ 1429 /* NON_SPECIAL_REGS. */ \ 1430 { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000, 0x00000000 }, \ 1431 /* LINK_REGS. */ \ 1432 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000 }, \ 1433 /* CTR_REGS. */ \ 1434 { 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000 }, \ 1435 /* LINK_OR_CTR_REGS. */ \ 1436 { 0x00000000, 0x00000000, 0x00000006, 0x00000000, 0x00000000 }, \ 1437 /* SPECIAL_REGS. */ \ 1438 { 0x00000000, 0x00000000, 0x00000006, 0x00002000, 0x00000000 }, \ 1439 /* SPEC_OR_GEN_REGS. */ \ 1440 { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000, 0x00000000 }, \ 1441 /* CR0_REGS. */ \ 1442 { 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000 }, \ 1443 /* CR_REGS. */ \ 1444 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000, 0x00000000 }, \ 1445 /* NON_FLOAT_REGS. */ \ 1446 { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000, 0x00000000 }, \ 1447 /* CA_REGS. */ \ 1448 { 0x00000000, 0x00000000, 0x00001000, 0x00000000, 0x00000000 }, \ 1449 /* SPE_HIGH_REGS. */ \ 1450 { 0x00000000, 0x00000000, 0x00000000, 0xffe00000, 0x001fffff }, \ 1451 /* ALL_REGS. */ \ 1452 { 0xffffffff, 0xffffffff, 0xfffffffe, 0xffe7ffff, 0x001fffff } \ 1453 } 1454 1455 /* The same information, inverted: 1456 Return the class number of the smallest class containing 1457 reg number REGNO. This could be a conditional expression 1458 or could index an array. */ 1459 1460 extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER]; 1461 1462 #if ENABLE_CHECKING 1463 #define REGNO_REG_CLASS(REGNO) \ 1464 (gcc_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)), \ 1465 rs6000_regno_regclass[(REGNO)]) 1466 1467 #else 1468 #define REGNO_REG_CLASS(REGNO) rs6000_regno_regclass[(REGNO)] 1469 #endif 1470 1471 /* Register classes for various constraints that are based on the target 1472 switches. */ 1473 enum r6000_reg_class_enum { 1474 RS6000_CONSTRAINT_d, /* fpr registers for double values */ 1475 RS6000_CONSTRAINT_f, /* fpr registers for single values */ 1476 RS6000_CONSTRAINT_v, /* Altivec registers */ 1477 RS6000_CONSTRAINT_wa, /* Any VSX register */ 1478 RS6000_CONSTRAINT_wd, /* VSX register for V2DF */ 1479 RS6000_CONSTRAINT_wf, /* VSX register for V4SF */ 1480 RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */ 1481 RS6000_CONSTRAINT_wh, /* FPR register for direct moves. */ 1482 RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */ 1483 RS6000_CONSTRAINT_wj, /* FPR/VSX register for DImode direct moves. */ 1484 RS6000_CONSTRAINT_wk, /* FPR/VSX register for DFmode direct moves. */ 1485 RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */ 1486 RS6000_CONSTRAINT_wm, /* VSX register for direct move */ 1487 RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */ 1488 RS6000_CONSTRAINT_ws, /* VSX register for DF */ 1489 RS6000_CONSTRAINT_wt, /* VSX register for TImode */ 1490 RS6000_CONSTRAINT_wu, /* Altivec register for float load/stores. */ 1491 RS6000_CONSTRAINT_wv, /* Altivec register for double load/stores. */ 1492 RS6000_CONSTRAINT_ww, /* FP or VSX register for vsx float ops. */ 1493 RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */ 1494 RS6000_CONSTRAINT_wy, /* VSX register for SF */ 1495 RS6000_CONSTRAINT_wz, /* FPR register for LFIWZX */ 1496 RS6000_CONSTRAINT_MAX 1497 }; 1498 1499 extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; 1500 1501 /* The class value for index registers, and the one for base regs. */ 1502 #define INDEX_REG_CLASS GENERAL_REGS 1503 #define BASE_REG_CLASS BASE_REGS 1504 1505 /* Return whether a given register class can hold VSX objects. */ 1506 #define VSX_REG_CLASS_P(CLASS) \ 1507 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS) 1508 1509 /* Return whether a given register class targets general purpose registers. */ 1510 #define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS) 1511 1512 /* Given an rtx X being reloaded into a reg required to be 1513 in class CLASS, return the class of reg to actually use. 1514 In general this is just CLASS; but on some machines 1515 in some cases it is preferable to use a more restrictive class. 1516 1517 On the RS/6000, we have to return NO_REGS when we want to reload a 1518 floating-point CONST_DOUBLE to force it to be copied to memory. 1519 1520 We also don't want to reload integer values into floating-point 1521 registers if we can at all help it. In fact, this can 1522 cause reload to die, if it tries to generate a reload of CTR 1523 into a FP register and discovers it doesn't have the memory location 1524 required. 1525 1526 ??? Would it be a good idea to have reload do the converse, that is 1527 try to reload floating modes into FP registers if possible? 1528 */ 1529 1530 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 1531 rs6000_preferred_reload_class_ptr (X, CLASS) 1532 1533 /* Return the register class of a scratch register needed to copy IN into 1534 or out of a register in CLASS in MODE. If it can be done directly, 1535 NO_REGS is returned. */ 1536 1537 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ 1538 rs6000_secondary_reload_class_ptr (CLASS, MODE, IN) 1539 1540 /* If we are copying between FP or AltiVec registers and anything 1541 else, we need a memory location. The exception is when we are 1542 targeting ppc64 and the move to/from fpr to gpr instructions 1543 are available.*/ 1544 1545 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ 1546 rs6000_secondary_memory_needed_ptr (CLASS1, CLASS2, MODE) 1547 1548 /* For cpus that cannot load/store SDmode values from the 64-bit 1549 FP registers without using a full 64-bit load/store, we need 1550 to allocate a full 64-bit stack slot for them. */ 1551 1552 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \ 1553 rs6000_secondary_memory_needed_rtx (MODE) 1554 1555 /* Specify the mode to be used for memory when a secondary memory 1556 location is needed. For cpus that cannot load/store SDmode values 1557 from the 64-bit FP registers without using a full 64-bit 1558 load/store, we need a wider mode. */ 1559 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ 1560 rs6000_secondary_memory_needed_mode (MODE) 1561 1562 /* Return the maximum number of consecutive registers 1563 needed to represent mode MODE in a register of class CLASS. 1564 1565 On RS/6000, this is the size of MODE in words, except in the FP regs, where 1566 a single reg is enough for two words, unless we have VSX, where the FP 1567 registers can hold 128 bits. */ 1568 #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)] 1569 1570 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */ 1571 1572 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1573 rs6000_cannot_change_mode_class_ptr (FROM, TO, CLASS) 1574 1575 /* Stack layout; function entry, exit and calling. */ 1576 1577 /* Define this if pushing a word on the stack 1578 makes the stack pointer a smaller address. */ 1579 #define STACK_GROWS_DOWNWARD 1580 1581 /* Offsets recorded in opcodes are a multiple of this alignment factor. */ 1582 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8))) 1583 1584 /* Define this to nonzero if the nominal address of the stack frame 1585 is at the high-address end of the local variables; 1586 that is, each additional local variable allocated 1587 goes at a more negative offset in the frame. 1588 1589 On the RS/6000, we grow upwards, from the area after the outgoing 1590 arguments. */ 1591 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \ 1592 || (flag_sanitize & SANITIZE_ADDRESS) != 0) 1593 1594 /* Size of the fixed area on the stack */ 1595 #define RS6000_SAVE_AREA \ 1596 ((DEFAULT_ABI == ABI_V4 ? 8 : DEFAULT_ABI == ABI_ELFv2 ? 16 : 24) \ 1597 << (TARGET_64BIT ? 1 : 0)) 1598 1599 /* Stack offset for toc save slot. */ 1600 #define RS6000_TOC_SAVE_SLOT \ 1601 ((DEFAULT_ABI == ABI_ELFv2 ? 12 : 20) << (TARGET_64BIT ? 1 : 0)) 1602 1603 /* Align an address */ 1604 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1)) 1605 1606 /* Offset within stack frame to start allocating local variables at. 1607 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1608 first local allocated. Otherwise, it is the offset to the BEGINNING 1609 of the first local allocated. 1610 1611 On the RS/6000, the frame pointer is the same as the stack pointer, 1612 except for dynamic allocations. So we start after the fixed area and 1613 outgoing parameter area. */ 1614 1615 #define STARTING_FRAME_OFFSET \ 1616 (FRAME_GROWS_DOWNWARD \ 1617 ? 0 \ 1618 : (RS6000_ALIGN (crtl->outgoing_args_size, \ 1619 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \ 1620 + RS6000_SAVE_AREA)) 1621 1622 /* Offset from the stack pointer register to an item dynamically 1623 allocated on the stack, e.g., by `alloca'. 1624 1625 The default value for this macro is `STACK_POINTER_OFFSET' plus the 1626 length of the outgoing arguments. The default is correct for most 1627 machines. See `function.c' for details. */ 1628 #define STACK_DYNAMIC_OFFSET(FUNDECL) \ 1629 (RS6000_ALIGN (crtl->outgoing_args_size, \ 1630 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \ 1631 + (STACK_POINTER_OFFSET)) 1632 1633 /* If we generate an insn to push BYTES bytes, 1634 this says how many the stack pointer really advances by. 1635 On RS/6000, don't define this because there are no push insns. */ 1636 /* #define PUSH_ROUNDING(BYTES) */ 1637 1638 /* Offset of first parameter from the argument pointer register value. 1639 On the RS/6000, we define the argument pointer to the start of the fixed 1640 area. */ 1641 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA 1642 1643 /* Offset from the argument pointer register value to the top of 1644 stack. This is different from FIRST_PARM_OFFSET because of the 1645 register save area. */ 1646 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 1647 1648 /* Define this if stack space is still allocated for a parameter passed 1649 in a register. The value is the number of bytes allocated to this 1650 area. */ 1651 #define REG_PARM_STACK_SPACE(FNDECL) \ 1652 rs6000_reg_parm_stack_space ((FNDECL), false) 1653 1654 /* Define this macro if space guaranteed when compiling a function body 1655 is different to space required when making a call, a situation that 1656 can arise with K&R style function definitions. */ 1657 #define INCOMING_REG_PARM_STACK_SPACE(FNDECL) \ 1658 rs6000_reg_parm_stack_space ((FNDECL), true) 1659 1660 /* Define this if the above stack space is to be considered part of the 1661 space allocated by the caller. */ 1662 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 1663 1664 /* This is the difference between the logical top of stack and the actual sp. 1665 1666 For the RS/6000, sp points past the fixed area. */ 1667 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA 1668 1669 /* Define this if the maximum size of all the outgoing args is to be 1670 accumulated and pushed during the prologue. The amount can be 1671 found in the variable crtl->outgoing_args_size. */ 1672 #define ACCUMULATE_OUTGOING_ARGS 1 1673 1674 /* Define how to find the value returned by a library function 1675 assuming the value has mode MODE. */ 1676 1677 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE)) 1678 1679 /* DRAFT_V4_STRUCT_RET defaults off. */ 1680 #define DRAFT_V4_STRUCT_RET 0 1681 1682 /* Let TARGET_RETURN_IN_MEMORY control what happens. */ 1683 #define DEFAULT_PCC_STRUCT_RETURN 0 1684 1685 /* Mode of stack savearea. 1686 FUNCTION is VOIDmode because calling convention maintains SP. 1687 BLOCK needs Pmode for SP. 1688 NONLOCAL needs twice Pmode to maintain both backchain and SP. */ 1689 #define STACK_SAVEAREA_MODE(LEVEL) \ 1690 (LEVEL == SAVE_FUNCTION ? VOIDmode \ 1691 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode) 1692 1693 /* Minimum and maximum general purpose registers used to hold arguments. */ 1694 #define GP_ARG_MIN_REG 3 1695 #define GP_ARG_MAX_REG 10 1696 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1) 1697 1698 /* Minimum and maximum floating point registers used to hold arguments. */ 1699 #define FP_ARG_MIN_REG 33 1700 #define FP_ARG_AIX_MAX_REG 45 1701 #define FP_ARG_V4_MAX_REG 40 1702 #define FP_ARG_MAX_REG (DEFAULT_ABI == ABI_V4 \ 1703 ? FP_ARG_V4_MAX_REG : FP_ARG_AIX_MAX_REG) 1704 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1) 1705 1706 /* Minimum and maximum AltiVec registers used to hold arguments. */ 1707 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2) 1708 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11) 1709 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1) 1710 1711 /* Maximum number of registers per ELFv2 homogeneous aggregate argument. */ 1712 #define AGGR_ARG_NUM_REG 8 1713 1714 /* Return registers */ 1715 #define GP_ARG_RETURN GP_ARG_MIN_REG 1716 #define FP_ARG_RETURN FP_ARG_MIN_REG 1717 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2) 1718 #define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \ 1719 : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) 1720 #define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? ALTIVEC_ARG_RETURN \ 1721 : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) 1722 1723 /* Flags for the call/call_value rtl operations set up by function_arg */ 1724 #define CALL_NORMAL 0x00000000 /* no special processing */ 1725 /* Bits in 0x00000001 are unused. */ 1726 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */ 1727 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */ 1728 #define CALL_LONG 0x00000008 /* always call indirect */ 1729 #define CALL_LIBCALL 0x00000010 /* libcall */ 1730 1731 /* We don't have prologue and epilogue functions to save/restore 1732 everything for most ABIs. */ 1733 #define WORLD_SAVE_P(INFO) 0 1734 1735 /* 1 if N is a possible register number for a function value 1736 as seen by the caller. 1737 1738 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */ 1739 #define FUNCTION_VALUE_REGNO_P(N) \ 1740 ((N) == GP_ARG_RETURN \ 1741 || ((N) >= FP_ARG_RETURN && (N) <= FP_ARG_MAX_RETURN \ 1742 && TARGET_HARD_FLOAT && TARGET_FPRS) \ 1743 || ((N) >= ALTIVEC_ARG_RETURN && (N) <= ALTIVEC_ARG_MAX_RETURN \ 1744 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)) 1745 1746 /* 1 if N is a possible register number for function argument passing. 1747 On RS/6000, these are r3-r10 and fp1-fp13. 1748 On AltiVec, v2 - v13 are used for passing vectors. */ 1749 #define FUNCTION_ARG_REGNO_P(N) \ 1750 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \ 1751 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \ 1752 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \ 1753 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \ 1754 && TARGET_HARD_FLOAT && TARGET_FPRS)) 1755 1756 /* Define a data type for recording info about an argument list 1757 during the scan of that argument list. This data type should 1758 hold all necessary information about the function itself 1759 and about the args processed so far, enough to enable macros 1760 such as FUNCTION_ARG to determine where the next arg should go. 1761 1762 On the RS/6000, this is a structure. The first element is the number of 1763 total argument words, the second is used to store the next 1764 floating-point register number, and the third says how many more args we 1765 have prototype types for. 1766 1767 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is 1768 the next available GP register, `fregno' is the next available FP 1769 register, and `words' is the number of words used on the stack. 1770 1771 The varargs/stdarg support requires that this structure's size 1772 be a multiple of sizeof(int). */ 1773 1774 typedef struct rs6000_args 1775 { 1776 int words; /* # words used for passing GP registers */ 1777 int fregno; /* next available FP register */ 1778 int vregno; /* next available AltiVec register */ 1779 int nargs_prototype; /* # args left in the current prototype */ 1780 int prototype; /* Whether a prototype was defined */ 1781 int stdarg; /* Whether function is a stdarg function. */ 1782 int call_cookie; /* Do special things for this call */ 1783 int sysv_gregno; /* next available GP register */ 1784 int intoffset; /* running offset in struct (darwin64) */ 1785 int use_stack; /* any part of struct on stack (darwin64) */ 1786 int floats_in_gpr; /* count of SFmode floats taking up 1787 GPR space (darwin64) */ 1788 int named; /* false for varargs params */ 1789 int escapes; /* if function visible outside tu */ 1790 } CUMULATIVE_ARGS; 1791 1792 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1793 for a call to a function whose data type is FNTYPE. 1794 For a library call, FNTYPE is 0. */ 1795 1796 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1797 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \ 1798 N_NAMED_ARGS, FNDECL, VOIDmode) 1799 1800 /* Similar, but when scanning the definition of a procedure. We always 1801 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */ 1802 1803 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ 1804 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \ 1805 1000, current_function_decl, VOIDmode) 1806 1807 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */ 1808 1809 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ 1810 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \ 1811 0, NULL_TREE, MODE) 1812 1813 /* If defined, a C expression which determines whether, and in which 1814 direction, to pad out an argument with extra space. The value 1815 should be of type `enum direction': either `upward' to pad above 1816 the argument, `downward' to pad below, or `none' to inhibit 1817 padding. */ 1818 1819 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE) 1820 1821 #define PAD_VARARGS_DOWN \ 1822 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward) 1823 1824 /* Output assembler code to FILE to increment profiler label # LABELNO 1825 for profiling a function entry. */ 1826 1827 #define FUNCTION_PROFILER(FILE, LABELNO) \ 1828 output_function_profiler ((FILE), (LABELNO)); 1829 1830 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1831 the stack pointer does not matter. No definition is equivalent to 1832 always zero. 1833 1834 On the RS/6000, this is nonzero because we can restore the stack from 1835 its backpointer, which we maintain. */ 1836 #define EXIT_IGNORE_STACK 1 1837 1838 /* Define this macro as a C expression that is nonzero for registers 1839 that are used by the epilogue or the return' pattern. The stack 1840 and frame pointer registers are already be assumed to be used as 1841 needed. */ 1842 1843 #define EPILOGUE_USES(REGNO) \ 1844 ((reload_completed && (REGNO) == LR_REGNO) \ 1845 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \ 1846 || (crtl->calls_eh_return \ 1847 && TARGET_AIX \ 1848 && (REGNO) == 2)) 1849 1850 1851 /* Length in units of the trampoline for entering a nested function. */ 1852 1853 #define TRAMPOLINE_SIZE rs6000_trampoline_size () 1854 1855 /* Definitions for __builtin_return_address and __builtin_frame_address. 1856 __builtin_return_address (0) should give link register (65), enable 1857 this. */ 1858 /* This should be uncommented, so that the link register is used, but 1859 currently this would result in unmatched insns and spilling fixed 1860 registers so we'll leave it for another day. When these problems are 1861 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX. 1862 (mrs) */ 1863 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */ 1864 1865 /* Number of bytes into the frame return addresses can be found. See 1866 rs6000_stack_info in rs6000.c for more information on how the different 1867 abi's store the return address. */ 1868 #define RETURN_ADDRESS_OFFSET \ 1869 ((DEFAULT_ABI == ABI_V4 ? 4 : 8) << (TARGET_64BIT ? 1 : 0)) 1870 1871 /* The current return address is in link register (65). The return address 1872 of anything farther back is accessed normally at an offset of 8 from the 1873 frame pointer. */ 1874 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 1875 (rs6000_return_addr (COUNT, FRAME)) 1876 1877 1878 /* Definitions for register eliminations. 1879 1880 We have two registers that can be eliminated on the RS/6000. First, the 1881 frame pointer register can often be eliminated in favor of the stack 1882 pointer register. Secondly, the argument pointer register can always be 1883 eliminated; it is replaced with either the stack or frame pointer. 1884 1885 In addition, we use the elimination mechanism to see if r30 is needed 1886 Initially we assume that it isn't. If it is, we spill it. This is done 1887 by making it an eliminable register. We replace it with itself so that 1888 if it isn't needed, then existing uses won't be modified. */ 1889 1890 /* This is an array of structures. Each structure initializes one pair 1891 of eliminable registers. The "from" register number is given first, 1892 followed by "to". Eliminations of the same "from" register are listed 1893 in order of preference. */ 1894 #define ELIMINABLE_REGS \ 1895 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1896 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1897 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1898 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1899 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1900 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } } 1901 1902 /* Define the offset between two registers, one to be eliminated, and the other 1903 its replacement, at the start of a routine. */ 1904 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1905 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO)) 1906 1907 /* Addressing modes, and classification of registers for them. */ 1908 1909 #define HAVE_PRE_DECREMENT 1 1910 #define HAVE_PRE_INCREMENT 1 1911 #define HAVE_PRE_MODIFY_DISP 1 1912 #define HAVE_PRE_MODIFY_REG 1 1913 1914 /* Macros to check register numbers against specific register classes. */ 1915 1916 /* These assume that REGNO is a hard or pseudo reg number. 1917 They give nonzero only if REGNO is a hard reg of the suitable class 1918 or a pseudo reg currently allocated to a suitable hard reg. 1919 Since they use reg_renumber, they are safe only once reg_renumber 1920 has been allocated, which happens in reginfo.c during register 1921 allocation. */ 1922 1923 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1924 ((REGNO) < FIRST_PSEUDO_REGISTER \ 1925 ? (REGNO) <= 31 || (REGNO) == 67 \ 1926 || (REGNO) == FRAME_POINTER_REGNUM \ 1927 : (reg_renumber[REGNO] >= 0 \ 1928 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ 1929 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) 1930 1931 #define REGNO_OK_FOR_BASE_P(REGNO) \ 1932 ((REGNO) < FIRST_PSEUDO_REGISTER \ 1933 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \ 1934 || (REGNO) == FRAME_POINTER_REGNUM \ 1935 : (reg_renumber[REGNO] > 0 \ 1936 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ 1937 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) 1938 1939 /* Nonzero if X is a hard reg that can be used as an index 1940 or if it is a pseudo reg in the non-strict case. */ 1941 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \ 1942 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ 1943 || REGNO_OK_FOR_INDEX_P (REGNO (X))) 1944 1945 /* Nonzero if X is a hard reg that can be used as a base reg 1946 or if it is a pseudo reg in the non-strict case. */ 1947 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \ 1948 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ 1949 || REGNO_OK_FOR_BASE_P (REGNO (X))) 1950 1951 1952 /* Maximum number of registers that can appear in a valid memory address. */ 1953 1954 #define MAX_REGS_PER_ADDRESS 2 1955 1956 /* Recognize any constant value that is a valid address. */ 1957 1958 #define CONSTANT_ADDRESS_P(X) \ 1959 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 1960 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ 1961 || GET_CODE (X) == HIGH) 1962 1963 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15) 1964 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \ 1965 && EASY_VECTOR_15((n) >> 1) \ 1966 && ((n) & 1) == 0) 1967 1968 #define EASY_VECTOR_MSB(n,mode) \ 1969 (((unsigned HOST_WIDE_INT)n) == \ 1970 ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1)) 1971 1972 1973 /* Try a machine-dependent way of reloading an illegitimate address 1974 operand. If we find one, push the reload and jump to WIN. This 1975 macro is used in only one place: `find_reloads_address' in reload.c. 1976 1977 Implemented on rs6000 by rs6000_legitimize_reload_address. 1978 Note that (X) is evaluated twice; this is safe in current usage. */ 1979 1980 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 1981 do { \ 1982 int win; \ 1983 (X) = rs6000_legitimize_reload_address_ptr ((X), (MODE), (OPNUM), \ 1984 (int)(TYPE), (IND_LEVELS), &win); \ 1985 if ( win ) \ 1986 goto WIN; \ 1987 } while (0) 1988 1989 #define FIND_BASE_TERM rs6000_find_base_term 1990 1991 /* The register number of the register used to address a table of 1992 static data addresses in memory. In some cases this register is 1993 defined by a processor's "application binary interface" (ABI). 1994 When this macro is defined, RTL is generated for this register 1995 once, as with the stack pointer and frame pointer registers. If 1996 this macro is not defined, it is up to the machine-dependent files 1997 to allocate such a register (if necessary). */ 1998 1999 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30 2000 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM) 2001 2002 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2) 2003 2004 /* Define this macro if the register defined by 2005 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define 2006 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */ 2007 2008 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ 2009 2010 /* A C expression that is nonzero if X is a legitimate immediate 2011 operand on the target machine when generating position independent 2012 code. You can assume that X satisfies `CONSTANT_P', so you need 2013 not check this. You can also assume FLAG_PIC is true, so you need 2014 not check it either. You need not define this macro if all 2015 constants (including `SYMBOL_REF') can be immediate operands when 2016 generating position independent code. */ 2017 2018 /* #define LEGITIMATE_PIC_OPERAND_P (X) */ 2019 2020 /* Define this if some processing needs to be done immediately before 2021 emitting code for an insn. */ 2022 2023 #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) \ 2024 rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS) 2025 2026 /* Specify the machine mode that this machine uses 2027 for the index in the tablejump instruction. */ 2028 #define CASE_VECTOR_MODE SImode 2029 2030 /* Define as C expression which evaluates to nonzero if the tablejump 2031 instruction expects the table to contain offsets from the address of the 2032 table. 2033 Do not define this if the table should contain absolute addresses. */ 2034 #define CASE_VECTOR_PC_RELATIVE 1 2035 2036 /* Define this as 1 if `char' should by default be signed; else as 0. */ 2037 #define DEFAULT_SIGNED_CHAR 0 2038 2039 /* An integer expression for the size in bits of the largest integer machine 2040 mode that should actually be used. */ 2041 2042 /* Allow pairs of registers to be used, which is the intent of the default. */ 2043 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode) 2044 2045 /* Max number of bytes we can move from memory to memory 2046 in one reasonably fast instruction. */ 2047 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8) 2048 #define MAX_MOVE_MAX 8 2049 2050 /* Nonzero if access to memory by bytes is no faster than for words. 2051 Also nonzero if doing byte operations (specifically shifts) in registers 2052 is undesirable. */ 2053 #define SLOW_BYTE_ACCESS 1 2054 2055 /* Define if operations between registers always perform the operation 2056 on the full register even if a narrower mode is specified. */ 2057 #define WORD_REGISTER_OPERATIONS 2058 2059 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 2060 will either zero-extend or sign-extend. The value of this macro should 2061 be the code that says which one of the two operations is implicitly 2062 done, UNKNOWN if none. */ 2063 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 2064 2065 /* Define if loading short immediate values into registers sign extends. */ 2066 #define SHORT_IMMEDIATES_SIGN_EXTEND 2067 2068 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 2069 is done just by pretending it is already truncated. */ 2070 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2071 2072 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */ 2073 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2074 ((VALUE) = ((MODE) == SImode ? 32 : 64), 1) 2075 2076 /* The CTZ patterns return -1 for input of zero. */ 2077 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 1) 2078 2079 /* Specify the machine mode that pointers have. 2080 After generation of rtl, the compiler makes no further distinction 2081 between pointers and any other objects of this machine mode. */ 2082 extern unsigned rs6000_pmode; 2083 #define Pmode ((enum machine_mode)rs6000_pmode) 2084 2085 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */ 2086 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode) 2087 2088 /* Mode of a function address in a call instruction (for indexing purposes). 2089 Doesn't matter on RS/6000. */ 2090 #define FUNCTION_MODE SImode 2091 2092 /* Define this if addresses of constant functions 2093 shouldn't be put through pseudo regs where they can be cse'd. 2094 Desirable on machines where ordinary constants are expensive 2095 but a CALL with constant address is cheap. */ 2096 #define NO_FUNCTION_CSE 2097 2098 /* Define this to be nonzero if shift instructions ignore all but the low-order 2099 few bits. 2100 2101 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED 2102 have been dropped from the PowerPC architecture. */ 2103 #define SHIFT_COUNT_TRUNCATED 0 2104 2105 /* Adjust the length of an INSN. LENGTH is the currently-computed length and 2106 should be adjusted to reflect any required changes. This macro is used when 2107 there is some systematic length adjustment required that would be difficult 2108 to express in the length attribute. */ 2109 2110 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */ 2111 2112 /* Given a comparison code (EQ, NE, etc.) and the first operand of a 2113 COMPARE, return the mode to be used for the comparison. For 2114 floating-point, CCFPmode should be used. CCUNSmode should be used 2115 for unsigned comparisons. CCEQmode should be used when we are 2116 doing an inequality comparison on the result of a 2117 comparison. CCmode should be used in all other cases. */ 2118 2119 #define SELECT_CC_MODE(OP,X,Y) \ 2120 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \ 2121 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \ 2122 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \ 2123 ? CCEQmode : CCmode)) 2124 2125 /* Can the condition code MODE be safely reversed? This is safe in 2126 all cases on this port, because at present it doesn't use the 2127 trapping FP comparisons (fcmpo). */ 2128 #define REVERSIBLE_CC_MODE(MODE) 1 2129 2130 /* Given a condition code and a mode, return the inverse condition. */ 2131 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE) 2132 2133 2134 /* Control the assembler format that we output. */ 2135 2136 /* A C string constant describing how to begin a comment in the target 2137 assembler language. The compiler assumes that the comment will end at 2138 the end of the line. */ 2139 #define ASM_COMMENT_START " #" 2140 2141 /* Flag to say the TOC is initialized */ 2142 extern int toc_initialized; 2143 2144 /* Macro to output a special constant pool entry. Go to WIN if we output 2145 it. Otherwise, it is written the usual way. 2146 2147 On the RS/6000, toc entries are handled this way. */ 2148 2149 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \ 2150 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \ 2151 { \ 2152 output_toc (FILE, X, LABELNO, MODE); \ 2153 goto WIN; \ 2154 } \ 2155 } 2156 2157 #ifdef HAVE_GAS_WEAK 2158 #define RS6000_WEAK 1 2159 #else 2160 #define RS6000_WEAK 0 2161 #endif 2162 2163 #if RS6000_WEAK 2164 /* Used in lieu of ASM_WEAKEN_LABEL. */ 2165 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \ 2166 do \ 2167 { \ 2168 fputs ("\t.weak\t", (FILE)); \ 2169 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2170 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ 2171 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 2172 { \ 2173 if (TARGET_XCOFF) \ 2174 fputs ("[DS]", (FILE)); \ 2175 fputs ("\n\t.weak\t.", (FILE)); \ 2176 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2177 } \ 2178 fputc ('\n', (FILE)); \ 2179 if (VAL) \ 2180 { \ 2181 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \ 2182 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ 2183 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 2184 { \ 2185 fputs ("\t.set\t.", (FILE)); \ 2186 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2187 fputs (",.", (FILE)); \ 2188 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \ 2189 fputc ('\n', (FILE)); \ 2190 } \ 2191 } \ 2192 } \ 2193 while (0) 2194 #endif 2195 2196 #if HAVE_GAS_WEAKREF 2197 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \ 2198 do \ 2199 { \ 2200 fputs ("\t.weakref\t", (FILE)); \ 2201 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2202 fputs (", ", (FILE)); \ 2203 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ 2204 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ 2205 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 2206 { \ 2207 fputs ("\n\t.weakref\t.", (FILE)); \ 2208 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2209 fputs (", .", (FILE)); \ 2210 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ 2211 } \ 2212 fputc ('\n', (FILE)); \ 2213 } while (0) 2214 #endif 2215 2216 /* This implements the `alias' attribute. */ 2217 #undef ASM_OUTPUT_DEF_FROM_DECLS 2218 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \ 2219 do \ 2220 { \ 2221 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ 2222 const char *name = IDENTIFIER_POINTER (TARGET); \ 2223 if (TREE_CODE (DECL) == FUNCTION_DECL \ 2224 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 2225 { \ 2226 if (TREE_PUBLIC (DECL)) \ 2227 { \ 2228 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ 2229 { \ 2230 fputs ("\t.globl\t.", FILE); \ 2231 RS6000_OUTPUT_BASENAME (FILE, alias); \ 2232 putc ('\n', FILE); \ 2233 } \ 2234 } \ 2235 else if (TARGET_XCOFF) \ 2236 { \ 2237 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ 2238 { \ 2239 fputs ("\t.lglobl\t.", FILE); \ 2240 RS6000_OUTPUT_BASENAME (FILE, alias); \ 2241 putc ('\n', FILE); \ 2242 fputs ("\t.lglobl\t", FILE); \ 2243 RS6000_OUTPUT_BASENAME (FILE, alias); \ 2244 putc ('\n', FILE); \ 2245 } \ 2246 } \ 2247 fputs ("\t.set\t.", FILE); \ 2248 RS6000_OUTPUT_BASENAME (FILE, alias); \ 2249 fputs (",.", FILE); \ 2250 RS6000_OUTPUT_BASENAME (FILE, name); \ 2251 fputc ('\n', FILE); \ 2252 } \ 2253 ASM_OUTPUT_DEF (FILE, alias, name); \ 2254 } \ 2255 while (0) 2256 2257 #define TARGET_ASM_FILE_START rs6000_file_start 2258 2259 /* Output to assembler file text saying following lines 2260 may contain character constants, extra white space, comments, etc. */ 2261 2262 #define ASM_APP_ON "" 2263 2264 /* Output to assembler file text saying following lines 2265 no longer contain unusual constructs. */ 2266 2267 #define ASM_APP_OFF "" 2268 2269 /* How to refer to registers in assembler output. 2270 This sequence is indexed by compiler's hard-register-number (see above). */ 2271 2272 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ 2273 2274 #define REGISTER_NAMES \ 2275 { \ 2276 &rs6000_reg_names[ 0][0], /* r0 */ \ 2277 &rs6000_reg_names[ 1][0], /* r1 */ \ 2278 &rs6000_reg_names[ 2][0], /* r2 */ \ 2279 &rs6000_reg_names[ 3][0], /* r3 */ \ 2280 &rs6000_reg_names[ 4][0], /* r4 */ \ 2281 &rs6000_reg_names[ 5][0], /* r5 */ \ 2282 &rs6000_reg_names[ 6][0], /* r6 */ \ 2283 &rs6000_reg_names[ 7][0], /* r7 */ \ 2284 &rs6000_reg_names[ 8][0], /* r8 */ \ 2285 &rs6000_reg_names[ 9][0], /* r9 */ \ 2286 &rs6000_reg_names[10][0], /* r10 */ \ 2287 &rs6000_reg_names[11][0], /* r11 */ \ 2288 &rs6000_reg_names[12][0], /* r12 */ \ 2289 &rs6000_reg_names[13][0], /* r13 */ \ 2290 &rs6000_reg_names[14][0], /* r14 */ \ 2291 &rs6000_reg_names[15][0], /* r15 */ \ 2292 &rs6000_reg_names[16][0], /* r16 */ \ 2293 &rs6000_reg_names[17][0], /* r17 */ \ 2294 &rs6000_reg_names[18][0], /* r18 */ \ 2295 &rs6000_reg_names[19][0], /* r19 */ \ 2296 &rs6000_reg_names[20][0], /* r20 */ \ 2297 &rs6000_reg_names[21][0], /* r21 */ \ 2298 &rs6000_reg_names[22][0], /* r22 */ \ 2299 &rs6000_reg_names[23][0], /* r23 */ \ 2300 &rs6000_reg_names[24][0], /* r24 */ \ 2301 &rs6000_reg_names[25][0], /* r25 */ \ 2302 &rs6000_reg_names[26][0], /* r26 */ \ 2303 &rs6000_reg_names[27][0], /* r27 */ \ 2304 &rs6000_reg_names[28][0], /* r28 */ \ 2305 &rs6000_reg_names[29][0], /* r29 */ \ 2306 &rs6000_reg_names[30][0], /* r30 */ \ 2307 &rs6000_reg_names[31][0], /* r31 */ \ 2308 \ 2309 &rs6000_reg_names[32][0], /* fr0 */ \ 2310 &rs6000_reg_names[33][0], /* fr1 */ \ 2311 &rs6000_reg_names[34][0], /* fr2 */ \ 2312 &rs6000_reg_names[35][0], /* fr3 */ \ 2313 &rs6000_reg_names[36][0], /* fr4 */ \ 2314 &rs6000_reg_names[37][0], /* fr5 */ \ 2315 &rs6000_reg_names[38][0], /* fr6 */ \ 2316 &rs6000_reg_names[39][0], /* fr7 */ \ 2317 &rs6000_reg_names[40][0], /* fr8 */ \ 2318 &rs6000_reg_names[41][0], /* fr9 */ \ 2319 &rs6000_reg_names[42][0], /* fr10 */ \ 2320 &rs6000_reg_names[43][0], /* fr11 */ \ 2321 &rs6000_reg_names[44][0], /* fr12 */ \ 2322 &rs6000_reg_names[45][0], /* fr13 */ \ 2323 &rs6000_reg_names[46][0], /* fr14 */ \ 2324 &rs6000_reg_names[47][0], /* fr15 */ \ 2325 &rs6000_reg_names[48][0], /* fr16 */ \ 2326 &rs6000_reg_names[49][0], /* fr17 */ \ 2327 &rs6000_reg_names[50][0], /* fr18 */ \ 2328 &rs6000_reg_names[51][0], /* fr19 */ \ 2329 &rs6000_reg_names[52][0], /* fr20 */ \ 2330 &rs6000_reg_names[53][0], /* fr21 */ \ 2331 &rs6000_reg_names[54][0], /* fr22 */ \ 2332 &rs6000_reg_names[55][0], /* fr23 */ \ 2333 &rs6000_reg_names[56][0], /* fr24 */ \ 2334 &rs6000_reg_names[57][0], /* fr25 */ \ 2335 &rs6000_reg_names[58][0], /* fr26 */ \ 2336 &rs6000_reg_names[59][0], /* fr27 */ \ 2337 &rs6000_reg_names[60][0], /* fr28 */ \ 2338 &rs6000_reg_names[61][0], /* fr29 */ \ 2339 &rs6000_reg_names[62][0], /* fr30 */ \ 2340 &rs6000_reg_names[63][0], /* fr31 */ \ 2341 \ 2342 &rs6000_reg_names[64][0], /* was mq */ \ 2343 &rs6000_reg_names[65][0], /* lr */ \ 2344 &rs6000_reg_names[66][0], /* ctr */ \ 2345 &rs6000_reg_names[67][0], /* ap */ \ 2346 \ 2347 &rs6000_reg_names[68][0], /* cr0 */ \ 2348 &rs6000_reg_names[69][0], /* cr1 */ \ 2349 &rs6000_reg_names[70][0], /* cr2 */ \ 2350 &rs6000_reg_names[71][0], /* cr3 */ \ 2351 &rs6000_reg_names[72][0], /* cr4 */ \ 2352 &rs6000_reg_names[73][0], /* cr5 */ \ 2353 &rs6000_reg_names[74][0], /* cr6 */ \ 2354 &rs6000_reg_names[75][0], /* cr7 */ \ 2355 \ 2356 &rs6000_reg_names[76][0], /* ca */ \ 2357 \ 2358 &rs6000_reg_names[77][0], /* v0 */ \ 2359 &rs6000_reg_names[78][0], /* v1 */ \ 2360 &rs6000_reg_names[79][0], /* v2 */ \ 2361 &rs6000_reg_names[80][0], /* v3 */ \ 2362 &rs6000_reg_names[81][0], /* v4 */ \ 2363 &rs6000_reg_names[82][0], /* v5 */ \ 2364 &rs6000_reg_names[83][0], /* v6 */ \ 2365 &rs6000_reg_names[84][0], /* v7 */ \ 2366 &rs6000_reg_names[85][0], /* v8 */ \ 2367 &rs6000_reg_names[86][0], /* v9 */ \ 2368 &rs6000_reg_names[87][0], /* v10 */ \ 2369 &rs6000_reg_names[88][0], /* v11 */ \ 2370 &rs6000_reg_names[89][0], /* v12 */ \ 2371 &rs6000_reg_names[90][0], /* v13 */ \ 2372 &rs6000_reg_names[91][0], /* v14 */ \ 2373 &rs6000_reg_names[92][0], /* v15 */ \ 2374 &rs6000_reg_names[93][0], /* v16 */ \ 2375 &rs6000_reg_names[94][0], /* v17 */ \ 2376 &rs6000_reg_names[95][0], /* v18 */ \ 2377 &rs6000_reg_names[96][0], /* v19 */ \ 2378 &rs6000_reg_names[97][0], /* v20 */ \ 2379 &rs6000_reg_names[98][0], /* v21 */ \ 2380 &rs6000_reg_names[99][0], /* v22 */ \ 2381 &rs6000_reg_names[100][0], /* v23 */ \ 2382 &rs6000_reg_names[101][0], /* v24 */ \ 2383 &rs6000_reg_names[102][0], /* v25 */ \ 2384 &rs6000_reg_names[103][0], /* v26 */ \ 2385 &rs6000_reg_names[104][0], /* v27 */ \ 2386 &rs6000_reg_names[105][0], /* v28 */ \ 2387 &rs6000_reg_names[106][0], /* v29 */ \ 2388 &rs6000_reg_names[107][0], /* v30 */ \ 2389 &rs6000_reg_names[108][0], /* v31 */ \ 2390 &rs6000_reg_names[109][0], /* vrsave */ \ 2391 &rs6000_reg_names[110][0], /* vscr */ \ 2392 &rs6000_reg_names[111][0], /* spe_acc */ \ 2393 &rs6000_reg_names[112][0], /* spefscr */ \ 2394 &rs6000_reg_names[113][0], /* sfp */ \ 2395 &rs6000_reg_names[114][0], /* tfhar */ \ 2396 &rs6000_reg_names[115][0], /* tfiar */ \ 2397 &rs6000_reg_names[116][0], /* texasr */ \ 2398 \ 2399 &rs6000_reg_names[117][0], /* SPE rh0. */ \ 2400 &rs6000_reg_names[118][0], /* SPE rh1. */ \ 2401 &rs6000_reg_names[119][0], /* SPE rh2. */ \ 2402 &rs6000_reg_names[120][0], /* SPE rh3. */ \ 2403 &rs6000_reg_names[121][0], /* SPE rh4. */ \ 2404 &rs6000_reg_names[122][0], /* SPE rh5. */ \ 2405 &rs6000_reg_names[123][0], /* SPE rh6. */ \ 2406 &rs6000_reg_names[124][0], /* SPE rh7. */ \ 2407 &rs6000_reg_names[125][0], /* SPE rh8. */ \ 2408 &rs6000_reg_names[126][0], /* SPE rh9. */ \ 2409 &rs6000_reg_names[127][0], /* SPE rh10. */ \ 2410 &rs6000_reg_names[128][0], /* SPE rh11. */ \ 2411 &rs6000_reg_names[129][0], /* SPE rh12. */ \ 2412 &rs6000_reg_names[130][0], /* SPE rh13. */ \ 2413 &rs6000_reg_names[131][0], /* SPE rh14. */ \ 2414 &rs6000_reg_names[132][0], /* SPE rh15. */ \ 2415 &rs6000_reg_names[133][0], /* SPE rh16. */ \ 2416 &rs6000_reg_names[134][0], /* SPE rh17. */ \ 2417 &rs6000_reg_names[135][0], /* SPE rh18. */ \ 2418 &rs6000_reg_names[136][0], /* SPE rh19. */ \ 2419 &rs6000_reg_names[137][0], /* SPE rh20. */ \ 2420 &rs6000_reg_names[138][0], /* SPE rh21. */ \ 2421 &rs6000_reg_names[139][0], /* SPE rh22. */ \ 2422 &rs6000_reg_names[140][0], /* SPE rh22. */ \ 2423 &rs6000_reg_names[141][0], /* SPE rh24. */ \ 2424 &rs6000_reg_names[142][0], /* SPE rh25. */ \ 2425 &rs6000_reg_names[143][0], /* SPE rh26. */ \ 2426 &rs6000_reg_names[144][0], /* SPE rh27. */ \ 2427 &rs6000_reg_names[145][0], /* SPE rh28. */ \ 2428 &rs6000_reg_names[146][0], /* SPE rh29. */ \ 2429 &rs6000_reg_names[147][0], /* SPE rh30. */ \ 2430 &rs6000_reg_names[148][0], /* SPE rh31. */ \ 2431 } 2432 2433 /* Table of additional register names to use in user input. */ 2434 2435 #define ADDITIONAL_REGISTER_NAMES \ 2436 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \ 2437 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \ 2438 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \ 2439 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \ 2440 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \ 2441 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \ 2442 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \ 2443 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \ 2444 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \ 2445 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \ 2446 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \ 2447 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \ 2448 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \ 2449 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \ 2450 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \ 2451 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \ 2452 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \ 2453 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \ 2454 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \ 2455 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \ 2456 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \ 2457 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \ 2458 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \ 2459 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \ 2460 {"vrsave", 109}, {"vscr", 110}, \ 2461 {"spe_acc", 111}, {"spefscr", 112}, \ 2462 /* no additional names for: lr, ctr, ap */ \ 2463 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \ 2464 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \ 2465 {"cc", 68}, {"sp", 1}, {"toc", 2}, \ 2466 /* CA is only part of XER, but we do not model the other parts (yet). */ \ 2467 {"xer", 76}, \ 2468 /* VSX registers overlaid on top of FR, Altivec registers */ \ 2469 {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \ 2470 {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \ 2471 {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \ 2472 {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \ 2473 {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \ 2474 {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \ 2475 {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \ 2476 {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \ 2477 {"vs32", 77}, {"vs33", 78}, {"vs34", 79}, {"vs35", 80}, \ 2478 {"vs36", 81}, {"vs37", 82}, {"vs38", 83}, {"vs39", 84}, \ 2479 {"vs40", 85}, {"vs41", 86}, {"vs42", 87}, {"vs43", 88}, \ 2480 {"vs44", 89}, {"vs45", 90}, {"vs46", 91}, {"vs47", 92}, \ 2481 {"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \ 2482 {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \ 2483 {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \ 2484 {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \ 2485 /* Transactional Memory Facility (HTM) Registers. */ \ 2486 {"tfhar", 114}, {"tfiar", 115}, {"texasr", 116}, \ 2487 /* SPE high registers. */ \ 2488 {"rh0", 117}, {"rh1", 118}, {"rh2", 119}, {"rh3", 120}, \ 2489 {"rh4", 121}, {"rh5", 122}, {"rh6", 123}, {"rh7", 124}, \ 2490 {"rh8", 125}, {"rh9", 126}, {"rh10", 127}, {"rh11", 128}, \ 2491 {"rh12", 129}, {"rh13", 130}, {"rh14", 131}, {"rh15", 132}, \ 2492 {"rh16", 133}, {"rh17", 134}, {"rh18", 135}, {"rh19", 136}, \ 2493 {"rh20", 137}, {"rh21", 138}, {"rh22", 139}, {"rh23", 140}, \ 2494 {"rh24", 141}, {"rh25", 142}, {"rh26", 143}, {"rh27", 144}, \ 2495 {"rh28", 145}, {"rh29", 146}, {"rh30", 147}, {"rh31", 148}, \ 2496 } 2497 2498 /* This is how to output an element of a case-vector that is relative. */ 2499 2500 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2501 do { char buf[100]; \ 2502 fputs ("\t.long ", FILE); \ 2503 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \ 2504 assemble_name (FILE, buf); \ 2505 putc ('-', FILE); \ 2506 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \ 2507 assemble_name (FILE, buf); \ 2508 putc ('\n', FILE); \ 2509 } while (0) 2510 2511 /* This is how to output an assembler line 2512 that says to advance the location counter 2513 to a multiple of 2**LOG bytes. */ 2514 2515 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 2516 if ((LOG) != 0) \ 2517 fprintf (FILE, "\t.align %d\n", (LOG)) 2518 2519 /* How to align the given loop. */ 2520 #define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL) 2521 2522 /* Alignment guaranteed by __builtin_malloc. */ 2523 /* FIXME: 128-bit alignment is guaranteed by glibc for TARGET_64BIT. 2524 However, specifying the stronger guarantee currently leads to 2525 a regression in SPEC CPU2006 437.leslie3d. The stronger 2526 guarantee should be implemented here once that's fixed. */ 2527 #define MALLOC_ABI_ALIGNMENT (64) 2528 2529 /* Pick up the return address upon entry to a procedure. Used for 2530 dwarf2 unwind information. This also enables the table driven 2531 mechanism. */ 2532 2533 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO) 2534 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO) 2535 2536 /* Describe how we implement __builtin_eh_return. */ 2537 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM) 2538 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10) 2539 2540 /* Print operand X (an rtx) in assembler syntax to file FILE. 2541 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2542 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 2543 2544 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 2545 2546 /* Define which CODE values are valid. */ 2547 2548 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '&') 2549 2550 /* Print a memory address as an operand to reference that memory location. */ 2551 2552 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 2553 2554 /* For switching between functions with different target attributes. */ 2555 #define SWITCHABLE_TARGET 1 2556 2557 /* uncomment for disabling the corresponding default options */ 2558 /* #define MACHINE_no_sched_interblock */ 2559 /* #define MACHINE_no_sched_speculative */ 2560 /* #define MACHINE_no_sched_speculative_load */ 2561 2562 /* General flags. */ 2563 extern int frame_pointer_needed; 2564 2565 /* Classification of the builtin functions as to which switches enable the 2566 builtin, and what attributes it should have. We used to use the target 2567 flags macros, but we've run out of bits, so we now map the options into new 2568 settings used here. */ 2569 2570 /* Builtin attributes. */ 2571 #define RS6000_BTC_SPECIAL 0x00000000 /* Special function. */ 2572 #define RS6000_BTC_UNARY 0x00000001 /* normal unary function. */ 2573 #define RS6000_BTC_BINARY 0x00000002 /* normal binary function. */ 2574 #define RS6000_BTC_TERNARY 0x00000003 /* normal ternary function. */ 2575 #define RS6000_BTC_PREDICATE 0x00000004 /* predicate function. */ 2576 #define RS6000_BTC_ABS 0x00000005 /* Altivec/VSX ABS function. */ 2577 #define RS6000_BTC_EVSEL 0x00000006 /* SPE EVSEL function. */ 2578 #define RS6000_BTC_DST 0x00000007 /* Altivec DST function. */ 2579 #define RS6000_BTC_TYPE_MASK 0x0000000f /* Mask to isolate types */ 2580 2581 #define RS6000_BTC_MISC 0x00000000 /* No special attributes. */ 2582 #define RS6000_BTC_CONST 0x00000100 /* uses no global state. */ 2583 #define RS6000_BTC_PURE 0x00000200 /* reads global state/mem. */ 2584 #define RS6000_BTC_FP 0x00000400 /* depends on rounding mode. */ 2585 #define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */ 2586 2587 /* Miscellaneous information. */ 2588 #define RS6000_BTC_SPR 0x01000000 /* function references SPRs. */ 2589 #define RS6000_BTC_VOID 0x02000000 /* function has no return value. */ 2590 #define RS6000_BTC_OVERLOADED 0x04000000 /* function is overloaded. */ 2591 #define RS6000_BTC_32BIT 0x08000000 /* function references SPRs. */ 2592 #define RS6000_BTC_64BIT 0x10000000 /* function references SPRs. */ 2593 #define RS6000_BTC_MISC_MASK 0x1f000000 /* Mask of the misc info. */ 2594 2595 /* Convenience macros to document the instruction type. */ 2596 #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */ 2597 #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */ 2598 2599 /* Builtin targets. For now, we reuse the masks for those options that are in 2600 target flags, and pick three random bits for SPE, paired and ldbl128 which 2601 aren't in target_flags. */ 2602 #define RS6000_BTM_ALWAYS 0 /* Always enabled. */ 2603 #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */ 2604 #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */ 2605 #define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */ 2606 #define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */ 2607 #define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */ 2608 #define RS6000_BTM_SPE MASK_STRING /* E500 */ 2609 #define RS6000_BTM_PAIRED MASK_MULHW /* 750CL paired insns. */ 2610 #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */ 2611 #define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */ 2612 #define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */ 2613 #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */ 2614 #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */ 2615 #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */ 2616 #define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */ 2617 #define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */ 2618 #define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */ 2619 2620 #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \ 2621 | RS6000_BTM_VSX \ 2622 | RS6000_BTM_P8_VECTOR \ 2623 | RS6000_BTM_CRYPTO \ 2624 | RS6000_BTM_FRE \ 2625 | RS6000_BTM_FRES \ 2626 | RS6000_BTM_FRSQRTE \ 2627 | RS6000_BTM_FRSQRTES \ 2628 | RS6000_BTM_HTM \ 2629 | RS6000_BTM_POPCNTD \ 2630 | RS6000_BTM_CELL \ 2631 | RS6000_BTM_DFP \ 2632 | RS6000_BTM_HARD_FLOAT \ 2633 | RS6000_BTM_LDBL128) 2634 2635 /* Define builtin enum index. */ 2636 2637 #undef RS6000_BUILTIN_1 2638 #undef RS6000_BUILTIN_2 2639 #undef RS6000_BUILTIN_3 2640 #undef RS6000_BUILTIN_A 2641 #undef RS6000_BUILTIN_D 2642 #undef RS6000_BUILTIN_E 2643 #undef RS6000_BUILTIN_H 2644 #undef RS6000_BUILTIN_P 2645 #undef RS6000_BUILTIN_Q 2646 #undef RS6000_BUILTIN_S 2647 #undef RS6000_BUILTIN_X 2648 2649 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2650 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2651 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2652 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2653 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2654 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2655 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2656 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2657 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2658 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2659 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2660 2661 enum rs6000_builtins 2662 { 2663 #include "rs6000-builtin.def" 2664 2665 RS6000_BUILTIN_COUNT 2666 }; 2667 2668 #undef RS6000_BUILTIN_1 2669 #undef RS6000_BUILTIN_2 2670 #undef RS6000_BUILTIN_3 2671 #undef RS6000_BUILTIN_A 2672 #undef RS6000_BUILTIN_D 2673 #undef RS6000_BUILTIN_E 2674 #undef RS6000_BUILTIN_H 2675 #undef RS6000_BUILTIN_P 2676 #undef RS6000_BUILTIN_Q 2677 #undef RS6000_BUILTIN_S 2678 #undef RS6000_BUILTIN_X 2679 2680 enum rs6000_builtin_type_index 2681 { 2682 RS6000_BTI_NOT_OPAQUE, 2683 RS6000_BTI_opaque_V2SI, 2684 RS6000_BTI_opaque_V2SF, 2685 RS6000_BTI_opaque_p_V2SI, 2686 RS6000_BTI_opaque_V4SI, 2687 RS6000_BTI_V16QI, 2688 RS6000_BTI_V1TI, 2689 RS6000_BTI_V2SI, 2690 RS6000_BTI_V2SF, 2691 RS6000_BTI_V2DI, 2692 RS6000_BTI_V2DF, 2693 RS6000_BTI_V4HI, 2694 RS6000_BTI_V4SI, 2695 RS6000_BTI_V4SF, 2696 RS6000_BTI_V8HI, 2697 RS6000_BTI_unsigned_V16QI, 2698 RS6000_BTI_unsigned_V1TI, 2699 RS6000_BTI_unsigned_V8HI, 2700 RS6000_BTI_unsigned_V4SI, 2701 RS6000_BTI_unsigned_V2DI, 2702 RS6000_BTI_bool_char, /* __bool char */ 2703 RS6000_BTI_bool_short, /* __bool short */ 2704 RS6000_BTI_bool_int, /* __bool int */ 2705 RS6000_BTI_bool_long, /* __bool long */ 2706 RS6000_BTI_pixel, /* __pixel */ 2707 RS6000_BTI_bool_V16QI, /* __vector __bool char */ 2708 RS6000_BTI_bool_V8HI, /* __vector __bool short */ 2709 RS6000_BTI_bool_V4SI, /* __vector __bool int */ 2710 RS6000_BTI_bool_V2DI, /* __vector __bool long */ 2711 RS6000_BTI_pixel_V8HI, /* __vector __pixel */ 2712 RS6000_BTI_long, /* long_integer_type_node */ 2713 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */ 2714 RS6000_BTI_long_long, /* long_long_integer_type_node */ 2715 RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */ 2716 RS6000_BTI_INTQI, /* intQI_type_node */ 2717 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */ 2718 RS6000_BTI_INTHI, /* intHI_type_node */ 2719 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */ 2720 RS6000_BTI_INTSI, /* intSI_type_node */ 2721 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */ 2722 RS6000_BTI_INTDI, /* intDI_type_node */ 2723 RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */ 2724 RS6000_BTI_INTTI, /* intTI_type_node */ 2725 RS6000_BTI_UINTTI, /* unsigned_intTI_type_node */ 2726 RS6000_BTI_float, /* float_type_node */ 2727 RS6000_BTI_double, /* double_type_node */ 2728 RS6000_BTI_long_double, /* long_double_type_node */ 2729 RS6000_BTI_dfloat64, /* dfloat64_type_node */ 2730 RS6000_BTI_dfloat128, /* dfloat128_type_node */ 2731 RS6000_BTI_void, /* void_type_node */ 2732 RS6000_BTI_MAX 2733 }; 2734 2735 2736 #define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI]) 2737 #define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF]) 2738 #define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI]) 2739 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI]) 2740 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI]) 2741 #define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI]) 2742 #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI]) 2743 #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF]) 2744 #define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI]) 2745 #define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF]) 2746 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI]) 2747 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI]) 2748 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF]) 2749 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI]) 2750 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI]) 2751 #define unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V1TI]) 2752 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI]) 2753 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI]) 2754 #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI]) 2755 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char]) 2756 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short]) 2757 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int]) 2758 #define bool_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long]) 2759 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel]) 2760 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI]) 2761 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI]) 2762 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI]) 2763 #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI]) 2764 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI]) 2765 2766 #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long]) 2767 #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long]) 2768 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long]) 2769 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long]) 2770 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI]) 2771 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI]) 2772 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI]) 2773 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI]) 2774 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI]) 2775 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI]) 2776 #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI]) 2777 #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI]) 2778 #define intTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTTI]) 2779 #define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI]) 2780 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float]) 2781 #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double]) 2782 #define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double]) 2783 #define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64]) 2784 #define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128]) 2785 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void]) 2786 2787 extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX]; 2788 extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT]; 2789 2790