1 /* 2 * Copyright (c) 1995, 1996 Cygnus Support 3 * 4 * The authors hereby grant permission to use, copy, modify, distribute, 5 * and license this software and its documentation for any purpose, provided 6 * that existing copyright notices are retained in all copies and that this 7 * notice is included verbatim in any distributions. No written agreement, 8 * license, or royalty fee is required for any of the authorized uses. 9 * Modifications to this software may be copyrighted by their authors 10 * and need not follow the licensing terms described here, provided that 11 * the new terms are clearly indicated on the first page of each file where 12 * they apply. 13 */ 14 15 #define STACK_SIZE 16 * 1024 16 #define TRAP_STACK_SIZE 4 * 1024 17 #define NUM_REGS 20 18 19 #ifdef SL933 20 #define NUMBER_OF_REGISTER_WINDOWS 6 21 #else 22 #define NUMBER_OF_REGISTER_WINDOWS 8 23 #endif 24 25 #if (NUMBER_OF_REGISTER_WINDOWS == 8) 26 #define SPARC_PSR_CWP_MASK 0x07 /* bits 0 - 4 */ 27 #elif (NUMBER_OF_REGISTER_WINDOWS == 16) 28 #define SPARC_PSR_CWP_MASK 0x0F /* bits 0 - 4 */ 29 #elif (NUMBER_OF_REGISTER_WINDOWS == 32) 30 #define SPARC_PSR_CWP_MASK 0x1F /* bits 0 - 4 */ 31 #else 32 #error "Unsupported number of register windows for this cpu" 33 #endif 34 35 /* The traptable has to be the first code in a boot PROM. */ 36 37 /* 38 * Entry for traps which jump to a programmer-specified trap handler. 39 */ 40 41 #define TRAP(_handler) \ 42 sethi %hi(_handler), %l3 ; \ 43 jmpl %l3+%lo(_handler), %g0 ; \ 44 mov %wim, %l0 ; \ 45 nop 46 47 /* Unexcpected trap will halt the processor by forcing it to error state */ 48 #if 1 49 #define BAD_TRAP ta 0; nop; nop; nop; 50 #else 51 #define BAD_TRAP \ 52 mov %psr, l0 ; \ 53 mov 0x0, %o0 ; \ 54 sethi %hi(SYM(bad_trap)), l4 ; \ 55 jmp l4+%lo(SYM(bad_trap)); 56 #endif 57 58 /* Software trap. Treat as BAD_TRAP for the time being... */ 59 #if 1 60 #define SOFT_TRAP BAD_TRAP 61 #else 62 #define SOFT_TRAP \ 63 mov $psr, $l0 ; \ 64 mov 0x0, $o0 ; \ 65 sethi $hi(SYM(soft_trap)), l4 ; \ 66 jmp l4+$lo(SYM(soft_trap)); 67 #endif 68 69 #define PSR_INIT 0x10c0 /* Disable traps, set s and ps */ 70 #define TBR_INIT 0 71 #define WIM_INIT 2 72 #define SP_INIT 0x023ffff0 73 74 /* Macros for reading and writing to arbitrary address spaces. Note that ASI 75 must be a constant (sorry, but the SPARC can only specify ASIs as part of an 76 instruction. */ 77 78 #define read_asi(ASI, LOC) \ 79 ({ \ 80 unsigned int val; \ 81 __asm__ volatile ("lda [%r1]%2,%0" : "=r" (val) : "rJ" (LOC), "I" (ASI)); \ 82 val; \ 83 }) 84 85 #define write_asi(ASI, LOC, VAL) \ 86 __asm__ volatile ("sta %0,[%r1]%2" : : "r" (VAL), "rJ" (LOC), "I" (ASI)); 87 88 /* 89 * Use this when modifying registers that cause memory to be modified. This 90 * will cause GCC to reload all values after this point. 91 */ 92 #define write_asi_volatile(ASI, LOC, VAL) \ 93 __asm__ volatile ("sta %0,[%r1]%2" : : "r" (VAL), "rJ" (LOC), "I" (ASI) \ 94 : "memory"); 95 96 #define WRITE_PC(x) registers[PC] = x; registers[NPC] = x + 4; 97 98 /* 99 * Processor Status Register (psr) 100 * 101 * 31 28|27 24|23 20|19 12|11 9|7|6|5|4 0 102 * +------+-------+-------+-------+------+-+-+-+--------+ 103 * | impl | ver | icc | res. | pil | | | | cwp | 104 * +------+-------+-------+-------+------+-+-+-+--------+ 105 * S P E 106 * S T 107 * if ET = 1, traps are enabled, 0 means disabled. 108 * if S = 1, you're in supervisor mode, 0 means user mode. 109 * cwp points to the current window. 110 * 111 * Trap Base Register (tbr) 112 * 113 * 31 12|11 4|3 0 114 * +--------------+--------------+------+ 115 * | tba | tt | null | 116 * +--------------+--------------+------+ 117 * 118 * tba contains the most sig. 20 bits of the tbr base address 119 * tt is the trap number. 120 * 121 * Window Invalid Register (wim) 122 * 31 8| 7| 6| 5| 4| 3| 2| 1| 0 123 * +-------------+--+--+--+--+--+--+--+--+ 124 * | res. |w7|w6|w5|w4|w3|w2|w1|w0| 125 * +-------------+--+--+--+--+--+--+--+--+ 126 */ 127 128