1 ifndef __regtn20inc 2__regtn20inc equ 1 3 save 4 listing off ; kein Listing ueber diesen File 5 6;**************************************************************************** 7;* * 8;* AS 1.42 - File REGTN20.INC * 9;* * 10;* Contains Bit & Register Definitions for ATtiny20 * 11;* * 12;**************************************************************************** 13 14;---------------------------------------------------------------------------- 15; Memory Limits 16 17RAMSTART equ 0x40,data ; Start Address SRAM 18RAMEND equ 0xbf,data ; End Address SRAM 19FLASHEND label 2047 ; End Address Flash 20 21;---------------------------------------------------------------------------- 22; Chip Configuration 23 24RSTFLR port 0x3b ; Reset Flag Register 25WDRF avrbit RSTFLR,3 ; Watchdog Reset Flag 26BORF avrbit RSTFLR,2 ; Brown-out Reset Flag 27EXTRF avrbit RSTFLR,1 ; External Reset Flag 28PORF avrbit RSTFLR,0 ; Power-on Reset Flag 29 30OSCCAL port 0x39 ; Oscillator Calibration 31 32CLKPSR port 0x36 ; Clock Prescaler Register 33CLKPS0 avrbit CLKPSR,0 ; Clock Prescaler Select 34CLKPS1 avrbit CLKPSR,1 35CLKPS2 avrbit CLKPSR,2 36CLKPS3 avrbit CLKPSR,3 37 38CLKMSR port 0x37 ; Clock Main Settings Register 39CLKMS0 avrbit CLKMSR,0 ; Clock Main Select Bits 40CLKMS1 avrbit CLKMSR,1 41 42MCUCR port 0x3a ; MCU Control Register 43SE avrbit MCUCR,0 ; Sleep Mode Enable 44SM0 avrbit MCUCR,1 ; Sleep Mode Select 45SM1 avrbit MCUCR,2 46SM2 avrbit MCUCR,3 47BODS avrbit MCUCR,4 ; BOD Sleep 48 49PRR port 0x35 ; Power Reduction Register 50PRADC avrbit PRR,0 ; Power Reduction A/D Converter 51PRTIM0 avrbit PRR,1 ; Power Reduction Timer/Counter 0 52PRTIM1 avrbit PRR,2 ; Power Reduction Timer/Counter 1 53PRSPI avrbit PRR,3 ; Power Reduction SPI 54PRTWI avrbit PRR,4 ; Power Reduction TWI 55 56CCP port 0x3c ; Configuration Change Protection Register 57 58;---------------------------------------------------------------------------- 59; EEPROM/Flash Access 60 61NVMCSR port 0x32 ; Non-Volatile Memory Control and Status Register 62NVMBSY avrbit NVMCSR,7 ; Non-Volatile Memory Busy 63 64NVMCMD port 0x33 ; Non-Volatile Memory Command Register 65NVMCMD0 avrbit NVMCMD,0 ; Non-Volatile Memory Command 66NVMCMD1 avrbit NVMCMD,1 67NVMCMD2 avrbit NVMCMD,2 68NVMCMD3 avrbit NVMCMD,3 69NVMCMD4 avrbit NVMCMD,4 70NVMCMD5 avrbit NVMCMD,5 71 72;---------------------------------------------------------------------------- 73; GPIO 74 75PINA port 0x00 ; Port A @ 0x00 (IO) ff. 76PUEA port 0x03 ; Pull-Up Enable Port A 77PUEA0 avrbit PUEA,0 78PUEA1 avrbit PUEA,1 79PUEA2 avrbit PUEA,2 80PUEA3 avrbit PUEA,3 81PUEA4 avrbit PUEA,4 82PUEA5 avrbit PUEA,5 83PUEA6 avrbit PUEA,6 84PUEA7 avrbit PUEA,7 85PINB port 0x04 ; Port B @ 0x03 (IO) ff. 86__PORTB_BITS equ 0x0f ; (bits 0..3) 87PUEB port 0x07 ; Pull-Up Enable Port B 88PUEB0 avrbit PUEB,0 89PUEB1 avrbit PUEB,1 90PUEB2 avrbit PUEB,2 91PUEB3 avrbit PUEB,3 92 93PCMSK0 port 0x09 ; Pin-Change Mask Register 0 94PCINT0 avrbit PCMSK0,0 ; Enable Pin-Change Interrupt 0 95PCINT1 avrbit PCMSK0,1 ; Enable Pin-Change Interrupt 1 96PCINT2 avrbit PCMSK0,2 ; Enable Pin-Change Interrupt 2 97PCINT3 avrbit PCMSK0,3 ; Enable Pin-Change Interrupt 3 98PCINT4 avrbit PCMSK0,4 ; Enable Pin-Change Interrupt 4 99PCINT5 avrbit PCMSK0,5 ; Enable Pin-Change Interrupt 5 100PCINT6 avrbit PCMSK0,6 ; Enable Pin-Change Interrupt 6 101PCINT7 avrbit PCMSK0,7 ; Enable Pin-Change Interrupt 7 102 103PCMSK1 port 0x0a ; Pin-Change Mask Register 1 104PCINT8 avrbit PCMSK1,0 ; Enable Pin-Change Interrupt 8 105PCINT9 avrbit PCMSK1,1 ; Enable Pin-Change Interrupt 9 106PCINT10 avrbit PCMSK1,2 ; Enable Pin-Change Interrupt 10 107PCINT11 avrbit PCMSK1,3 ; Enable Pin-Change Interrupt 11 108 109 110PORTCR port 0x08 ; Port Control Register 111BBMA avrbit PORTCR,0 ; Break-Before-Make Mode Enable Port A 112BBMB avrbit PORTCR,1 ; Break-Before-Make Mode Enable Port B 113 114QTCSR port 0x34 ; QTouch Control and Status Register 115 116;---------------------------------------------------------------------------- 117; Interrupt Vectors 118 119 enumconf 1,code 120 enum INT0_vect=1 ; External Interrupt Request 0 121 nextenum PCINT0_vect ; Pin Change Interrupt 0 122 nextenum PCINT1_vect ; Pin Change Interrupt 1 123 nextenum WDT_vect ; Watchdog Time-out Interrupt 124 nextenum TIM1_CAPT_vect ; Timer/Counter 1 Capture 125 nextenum TIM1_COMPA_vect ; Timer/Counter 1 Compare Match A 126 nextenum TIM1_COMPB_vect ; Timer/Counter 1 Compare Match B 127 nextenum TIM1_OVF_vect ; Timer/Counter 1 Overflow 128 nextenum TIM0_COMPA_vect ; Timer/Counter 0 Compare Match A 129 nextenum TIM0_COMPB_vect ; Timer/Counter 0 Compare Match B 130 nextenum TIM0_OVF_vect ; Timer/Counter 0 Overflow 131 nextenum ANA_COMP_vect ; Analog Comparator 132 nextenum ADC_vect ; ADC Conversion Complete 133 nextenum TWI_SLAVE_vect ; Two-Wire Interface 134 nextenum SPI_vect ; Serial Peripheral Interface 135 nextenum QTRIP_vect ; Touch Sensing 136 137;---------------------------------------------------------------------------- 138; External Interrupts 139 140ISC00 avrbit MCUCR,6 ; Interrupt Sense Control 0 141ISC01 avrbit MCUCR,7 142 143GIMSK port 0x0c ; General Interrupt Mask Register 144INT0 avrbit GIMSK,0 ; Enable External Interrupt 0 145PCIE0 avrbit GIMSK,4 ; Enable Pin-Change Interrupt 0 146PCIE1 avrbit GIMSK,5 ; Enable Pin-Change Interrupt 1 147 148GIFR port 0x0b ; General Interrupt Flag Register 149INTF0 avrbit GIFR,0 ; External Interrupt 0 Occured 150PCIF0 avrbit GIFR,4 ; Pin-Change Interrupt 0 Occured 151PCIF1 avrbit GIFR,5 ; Pin-Change Interrupt 1 Occured 152 153;---------------------------------------------------------------------------- 154; Timers 155 156TCCR0A port 0x19 ; Timer/Counter 0 Control Register A 157WGM00 avrbit TCCR0A,0 ; Timer/Counter 0 Waveform Generation Mode 158WGM01 avrbit TCCR0A,1 159COM0B0 avrbit TCCR0A,4 ; Timer/Counter 0 Output Compare Mode B 160COM0B1 avrbit TCCR0A,5 161COM0A0 avrbit TCCR0A,6 ; Timer/Counter 0 Output Compare Mode A 162COM0A1 avrbit TCCR0A,7 163TCCR0B port 0x18 ; Timer/Counter 0 Control Register B 164CS00 avrbit TCCR0B,0 ; Timer/Counter 0 Clock Select 165CS01 avrbit TCCR0B,1 166CS02 avrbit TCCR0B,2 167WGM02 avrbit TCCR0B,3 168FOC0B avrbit TCCR0B,6 ; Timer/Counter 0 Force Output Compare Match B 169FOC0A avrbit TCCR0B,7 ; Timer/Counter 0 Force Output Compare Match A 170TCNT0 port 0x17 ; Timer/Counter 0 Value 171OCR0A port 0x16 ; Timer/Counter 0 Output Compare Value A 172OCR0B port 0x15 ; Timer/Counter 0 Output Compare Value B 173 174TCCR1A port 0x24 ; Timer/Counter 1 Control Register A 175WGM10 avrbit TCCR1A,0 ; Timer/Counter 1 Waveform Generation Mode 176WGM11 avrbit TCCR1A,1 177COM1B0 avrbit TCCR1A,4 ; Timer/Counter 1 Output Compare Mode B 178COM1B1 avrbit TCCR1A,5 179COM1A0 avrbit TCCR1A,6 ; Timer/Counter 1 Output Compare Mode A 180COM1A1 avrbit TCCR1A,7 181TCCR1B port 0x23 ; Timer/Counter 1 Control Register B 182CS10 avrbit TCCR1B,0 ; Timer/Counter 1 Clock Select 183CS11 avrbit TCCR1B,1 184CS12 avrbit TCCR1B,2 185WGM12 avrbit TCCR1B,3 186WGM13 avrbit TCCR1B,4 187ICES1 avrbit TCCR1B,6 ; Timer/Counter 1 Input Capture Edge Select 188ICNC1 avrbit TCCR1B,7 ; Timer/Counter 1 Input Capture Noise Canceler 189TCCR1C port 0x22 ; Timer/Counter 1 Control Register C 190FOC1B avrbit TCCR1C,6 ; Timer/Counter 1 Force Output Compare Match B 191FOC1A avrbit TCCR1C,7 ; Timer/Counter 1 Force Output Compare Match A 192TCNT1L port 0x20 ; Timer/Counter 1 Value LSB 193TCNT1H port 0x21 ; Timer/Counter 1 Value MSB 194OCR1AL port 0x1f ; Timer/Counter 1 Output Compare Value A LSB 195OCR1AH port 0x1e ; Timer/Counter 1 Output Compare Value A MSB 196OCR1BL port 0x1c ; Timer/Counter 1 Output Compare Value B LSB 197OCR1BH port 0x1d ; Timer/Counter 1 Output Compare Value B MSB 198ICR1L port 0x1a ; Timer/Counter 1 Input Capture Register LSB 199ICR1H port 0x1b ; Timer/Counter 1 Input Capture Register MSB 200 201TIMSK port 0x26 ; Timer/Counter Interrupt Mask Register 202TOIE0 avrbit TIMSK,0 ; Timer/Counter 0 Overflow Interrupt Enable 203OCIE0A avrbit TIMSK,1 ; Timer/Counter 0 Output Compare Interrupt Enable A 204OCIE0B avrbit TIMSK,2 ; Timer/Counter 0 Output Compare Interrupt Enable B 205TOIE1 avrbit TIMSK,3 ; Timer/Counter 1 Overflow Interrupt Enable 206OCIE1A avrbit TIMSK,4 ; Timer/Counter 1 Output Compare Interrupt Enable A 207OCIE1B avrbit TIMSK,5 ; Timer/Counter 1 Output Compare Interrupt Enable B 208ICE1 avrbit TIMSK,7 ; Timer/Counter 1 Input Capture Interrupt Enable 209 210TIFR port 0x25 ; Timer/Counter Interrupt Status Register 211 212GTCCR port 0x27 ; General Timer/Counter Control Register 213PSR avrbit GTCCR,0 ; Prescaler Reset Timer/Counter 0/1 214TSM avrbit GTCCR,7 ; Timer/Counter Synchronization Mode 215 216;---------------------------------------------------------------------------- 217; Watchdog Timer 218 219WDTCSR port 0x31 ; Watchdog Control/Status Register 220WDP0 avrbit WDTCSR,0 ; Prescaler 221WDP1 avrbit WDTCSR,1 222WDP2 avrbit WDTCSR,2 223WDE avrbit WDTCSR,3 ; Enable Watchdog 224WDP3 avrbit WDTCSR,5 225WDIE avrbit WDTCSR,6 ; Watchdog Interrupt Enable 226WDIF avrbit WDTCSR,7 ; Watchdog Interrupt Flag 227 228;---------------------------------------------------------------------------- 229; Analog Comparator 230 231ACSRA port 0x14 ; Analog Comparator Control and Status Register A 232ACIS0 avrbit ACSRA,0 ; Interrupt-Mode 233ACIS1 avrbit ACSRA,1 234ACIC avrbit ACSRA,2 ; Use Comparator As Capture Signal For Timer 0? 235ACIE avrbit ACSRA,3 ; Interrupt Enable 236ACI avrbit ACSRA,4 ; Interrupt Flag 237ACO avrbit ACSRA,5 ; Analog Comparator Output 238ACBG avrbit ACSRA,6 ; Enable Bandgap 239ACD avrbit ACSRA,7 ; Disable 240 241ACSRB port 0x13 ; Analog Comparator Control and Status Register B 242ACIRS0 avrbit ACSRB,0 ; Reserved for QTouch 243ACIRS1 avrbit ACSRB,1 244ACME avrbit ACSRB,2 ; Analog Comparator Multiplexer Enable 245ACCE avrbit ACSRB,3 ; Reserved for QTouch 246ACLP avrbit ACSRB,5 ; Reserved for QTouch 247HLEV avrbit ACSRB,6 ; Hysteresis Level 248HSEL avrbit ACSRB,7 ; Hysteresis Select 249 250;---------------------------------------------------------------------------- 251; A/D Converter 252 253ADMUX port 0x10 ; ADC Multiplexer Selection Register 254MUX0 avrbit ADMUX,0 ; Analog Channel Selection 255MUX1 avrbit ADMUX,1 256MUX2 avrbit ADMUX,2 257MUX3 avrbit ADMUX,3 258ADC0EN avrbit ADMUX,4 ; Reserved for QTouch 259REFEN avrbit ADMUX,5 ; Enable Reference 260REFS avrbit ADMUX,6 ; Reference Selection 261 262ADCSRA port 0x12 ; ADC Control/Status Register A 263ADEN avrbit ADCSRA,7 ; Enable ADC 264ADSC avrbit ADCSRA,6 ; Start Conversion 265ADATE avrbit ADCSRA,5 ; ADC Auto Trigger Enable 266ADIF avrbit ADCSRA,4 ; Interrupt Flag 267ADIE avrbit ADCSRA,3 ; Interrupt Enable 268ADPS2 avrbit ADCSRA,2 ; Prescaler Select 269ADPS1 avrbit ADCSRA,1 270ADPS0 avrbit ADCSRA,0 271 272ADCSRB port 0x11 ; ADC Control/Status Register A 273ADTS0 avrbit ADCSRB,0 ; ADC Auto Trigger Source 274ADTS1 avrbit ADCSRB,1 275ADTS2 avrbit ADCSRB,2 276ADLAR avrbit ADCSRB,3 ; ADC Left Adjust Result 277VDPD avrbit ADCSRB,6 ; Reserved for QTouch 278VDEN avrbit ADCSRB,7 ; Reserved for QTouch 279 280ADCL port 0x0e ; ADC Conversion Result LSB 281ADCH port 0x0f ; ADC Conversion Result MSB 282 283DIDR0 port 0x0d ; Digital Input Disable Register 0 284ADC0D avrbit DIDR0,0 ; ADC0 Digital Input Disable 285ADC1D avrbit DIDR0,1 ; ADC1 Digital Input Disable 286ADC2D avrbit DIDR0,2 ; ADC2 Digital Input Disable 287ADC3D avrbit DIDR0,3 ; ADC3 Digital Input Disable 288ADC4D avrbit DIDR0,4 ; ADC4 Digital Input Disable 289ADC5D avrbit DIDR0,5 ; ADC5 Digital Input Disable 290ADC6D avrbit DIDR0,6 ; ADC6 Digital Input Disable 291ADC7D avrbit DIDR0,7 ; ADC7 Digital Input Disable 292 293;---------------------------------------------------------------------------- 294; SPI 295 296SPCR port 0x30 ; SPI Control Register 297SPR0 avrbit SPCR,0 ; Clock Select 298SPR1 avrbit SPCR,1 299CPHA avrbit SPCR,2 ; Clock Phase 300CPOL avrbit SPCR,3 ; Clock Polarity 301MSTR avrbit SPCR,4 ; Master/Slave Selection 302DORD avrbit SPCR,5 ; Bit Order 303SPE avrbit SPCR,6 ; Enable SPI 304SPIE avrbit SPCR,7 ; SPI Interrupt Enable 305 306SPSR port 0x2f ; SPI Status Register 307SPI2X avrbit SPSR,0 ; Double Speed Mode 308WCOL avrbit SPSR,6 ; Write Collision 309SPIF avrbit SPSR,7 ; SPI Interrupt Occured? 310 311SPDR port 0x2e ; SPI Data Register 312 313;---------------------------------------------------------------------------- 314; SPI 315 316TWSCRA port 0x2d ; TWI Slave Control Register A 317TWSME avrbit TWSCRA,0 ; TWI Smart Mode Enable 318TWPME avrbit TWSCRA,1 ; TWI Promiscuous Mode Enable 319TWSIE avrbit TWSCRA,2 ; TWI Stop Interrupt Enable 320TWEN avrbit TWSCRA,3 ; TWI Enable 321TWASIE avrbit TWSCRA,4 ; TWI Address/Stop Interrupt Enable 322TWDIE avrbit TWSCRA,5 ; TWI Data Interrupt Enable 323TWSHE avrbit TWSCRA,7 ; TWI SDA Hold Time Enable 324 325TWSCRB port 0x2c ; TWI Slave Control Register B 326TWCMD0 avrbit TWSCRB,0 ; TWI Command 327TWCMD1 avrbit TWSCRB,1 328TWAA avrbit TWSCRB,2 ; TWI Acknowledge Action 329 330TWSSRA port 0x2b ; TWI Slave Status Register A 331TWAS avrbit TWSSRA,0 ; TWI Address or Stop 332TWDIR avrbit TWSSRA,1 ; TWI Read/Write Direction 333TWBE avrbit TWSSRA,2 ; TWI Bus Error 334TWC avrbit TWSSRA,3 ; TWI Collision 335TWRA avrbit TWSSRA,4 ; TWI Receive Acknowledge 336TWCH avrbit TWSSRA,5 ; TWI Clock Hold 337TWASIF avrbit TWSSRA,6 ; TWI Address/Stop Interrupt Flag 338TWDIF avrbit TWSSRA,7 ; TWI Data Interrupt Flag 339 340TWSA port 0x2a ; TWI Slave Address Register 341 342TWSAM port 0x29 ; TWI Slave Address Mask Register 343TWAE avrbit TWSAM,0 ; TWI Address Enable 344 345TWSD port 0x28 ; TWI Slave Data Register 346 347 restore 348 349 endif ; __regtn20inc 350