1 ifndef __s12z_cpmu_inc 2__s12z_cpmu_inc equ 1 3 4 save 5 listing off ; no listing over this file 6 7;**************************************************************************** 8;* * 9;* AS 1.42 - File S12ZCPMU.INC * 10;* * 11;* Contains Bit & Register Definitions for S12Z CPMU * 12;* * 13;**************************************************************************** 14 15CPMURESERVED00 equ $06C0 16CPMURESERVED01 equ $06C1 17CPMURESERVED02 equ $06C2 18CPMURFLG equ $06C3 ; Reset Flags Register 19PORF s12zbit CPMURFLG,6 ; Power on Reset Flag 20LVRF s12zbit CPMURFLG,5 ; Low Voltage Reset Flag 21COPRF s12zbit CPMURFLG,3 ; COP Reset Flag 22OMRF s12zbit CPMURFLG,1 ; Oscillator Clock Monitor Reset Flag 23PMRF s12zbit CPMURFLG,0 ; PLL Clock Monitor Reset Flag 24CPMUSYNR equ $06C4 ; Synthesizer Register 25VCOFRQ s12zfld CPMUSYNR,2:6 ; VCO gain 26SYNDIV s12zfld CPMUSYNR,6:0 ; Divider 27CPMUREFDIV equ $06C5 ; Reference Divider Register 28REFFRQ s12zfld CPMUREFDIV,2:6 ; REFFRQ 29REFDIV s12zfld CPMUREFDIV,4:0 ; Divider 30CPMUPOSTDIV equ $06C6 ; Post Divider Register 31POSTDIV s12zfld CPMUPOSTDIV,5:0 ; Divider 32CPMUIFLG equ $06C7 ; Interrupt Flags Register 33RTIF s12zbit CPMUIFLG,7 ; Real Time Interrupt Flag 34LOCKIF s12zbit CPMUIFLG,4 ; PLL Lock Interrupt Flag 35LOCK s12zbit CPMUIFLG,3 ; Lock Status Bit 36OSCIF s12zbit CPMUIFLG,1 ; Oscillator Interrupt Flag 37UPOSC s12zbit CPMUIFLG,0 ; Oscillator Status Bit 38CPMUINT equ $06C8 ; Interrupt Enable Register 39RTIE s12zbit CPMUINT,7 ; Real Time Interrupt Enable Bit 40LOCKIE s12zbit CPMUINT,4 ; PLL Lock Interrupt Enable Bit 41OSCIE s12zbit CPMUINT,0 ; Oscillator Corrupt Interrupt Enable Bit 42CPMUCLKS equ $06C9 ; Clock Select Register 43PLLSEL s12zbit CPMUCLKS,7 ; PLL Select Bit 44PSTP s12zbit CPMUCLKS,6 ; Pseudo Stop Bit 45CSAD s12zbit CPMUCLKS,5 ; COP in Stop Mode ACLK Disable 46COPOSCSEL1 s12zbit CPMUCLKS,4 ; COP Clock Select 1 47PRE s12zbit CPMUCLKS,3 ; RTI Enable During Pseudo Stop Bit 48PCE s12zbit CPMUCLKS,2 ; COP Enable During Pseudo Stop Bit 49RTIOSCSEL s12zbit CPMUCLKS,1 ; RTI Clock Select 50COPOSCSEL0 s12zbit CPMUCLKS,0 ; COP Clock Select 0 51CPMUPLL equ $06CA ; PLL Control Register 52FM1 s12zbit CPMUPLL,5 ; PLL Frequency Modulation Enable Bits 53FM0 s12zbit CPMUPLL,4 54CPMURTI equ $06CB ; RTI Control Register 55RTDEC s12zbit CPMURTI,7 ; Decimal or Binary Divider Select Bit 56RTR s12zfld CPMURTI,7:0 ; Real Time Interrupt Prescale Rate Select Bits (4..6) 57 ; Real Time Interrupt Modulus Counter Select Bits (0..3) 58CPMUCOP equ $06CC ; COP Control Register 59WCOP s12zbit CPMUCOP,7 ; Window COP Mode Bit 60RSBCK s12zbit CPMUCOP,6 ; COP and RTI Stop in Active BDM Mode Bit 61WRTMASK s12zbit CPMUCOP,5 ; Write Mask for WCOP and CR[2:0] Bit 62CR s12zfld CPMUCOP,3:0 ; COP Watchdog Timer Rate Select 63CPMUTEST0 equ $06CD 64CPMUTEST1 equ $06CE 65CPMUARMCOP equ $06CF ; COP Timer Arm/Reset Register 66CPMUHTCTL equ $06D0 ; High Temperature Control Register 67VSEL s12zbit CPMUHTCTL,5 ; Voltage Access Select Bit 68HTE s12zbit CPMUHTCTL,3 ; High Temperature Sensor/Bandgap Voltage Enable Bit 69HTDS s12zbit CPMUHTCTL,2 ; High Temperature Detect Status Bit 70HTIE s12zbit CPMUHTCTL,1 ; High Temperature Interrupt Enable Bit 71HTIF s12zbit CPMUHTCTL,0 ; High Temperature Interrupt Flag 72CPMULVCTL equ $06D1 ; Low Voltage Control Register 73LVDS s12zbit CPMULVCTL,2 ; Low-Voltage Detect Status Bit 74LVIE s12zbit CPMULVCTL,1 ; Low-Voltage Interrupt Enable Bit 75LVIF s12zbit CPMULVCTL,0 ; Low-Voltage Interrupt Flag 76CPMUAPICTL equ $06D2 ; Autonomous Periodical Interrupt Control Register 77APICLK s12zbit CPMUAPICTL,7 ; Autonomous Periodical Interrupt Clock Select Bit 78APIES s12zbit CPMUAPICTL,4 ; Autonomous Periodical Interrupt External Select Bit 79APIEA s12zbit CPMUAPICTL,3 ; Autonomous Periodical Interrupt External Access Enable Bit 80APIFE s12zbit CPMUAPICTL,2 ; Autonomous Periodical Interrupt Feature Enable Bit 81APIE s12zbit CPMUAPICTL,1 ; Autonomous Periodical Interrupt Enable Bit 82APIF s12zbit CPMUAPICTL,0 ; Autonomous Periodical Interrupt Flag 83CPMUACLKTR equ $06D3 ; Autonomous Clock Trimming Register 84ACLKTR s12zfld CPMUACLKTR,6:2 ; Autonomous Clock Period Trimming Bits 85CPMUAPIR equ $06D4 ; Autonomous Periodical Interrupt Rate (16 bit) 86CPMUAPIRH equ $06D4 ; Autonomous Periodical Interrupt Rate MSB 87CPMUAPIRL equ $06D5 ; Autonomous Periodical Interrupt Rate LSB 88CPMUTEST3 equ $06D6 89CPMUHTTR equ $06D7 ; High Temperature Trimming Register 90HTOE s12zbit CPMUHTTR,7 ; High Temperature Offset Enable Bit 91HTTR s12zfld CPMUHTTR,4:0 ; High Temperature Trimming Bits 92CPMUIRCTRIMH equ $06D8 ; IRC1M Trim Register MSB 93TCTRIM s12zfld CPMUIRCTRIMH,5:3; IRC1M temperature coefficient Trim Bits 94IRCTRIM s12zfld.w CPMUIRCTRIMH,10:0; IRC1M Frequency Trim Bits 95CPMUIRCTRIML equ $06D9 ; IRC1M Trim Register LSB 96CPMUOSC equ $06DA ; Oscillator Register 97OSCE s12zbit CPMUOSC,7 ; Oscillator Enable Bit 98CPMUPROT equ $06DB ; Protection Register 99PROT s12zbit CPMUPROT,0 ; Clock Configuration Registers Protection 100CPMUTEST2 equ $06DC 101CPMUVREGCTL equ $06DD ; Voltage Regulator Control Register 102EXTCON s12zbit CPMUVREGCTL,2 ; External voltage regulator Enable Bit for VDDC domain 103EXTXON s12zbit CPMUVREGCTL,1 ; External voltage regulator Enable Bit for VDDX domain 104INTXON s12zbit CPMUVREGCTL,0 ; Internal voltage regulator Enable Bit for VDDX domain 105CPMUOSC2 equ $06DE ; Oscillator Register 2 106OMRE s12zbit CPMUOSC2,1 ; select the mode of the external oscillator 107OSCMOD s12zbit CPMUOSC2,0 ; enable the oscillator clock monitor reset 108CPMURESERVED1F equ $06DF 109 110 restore ; re-enable listing 111 112 endif ; __s12z_cpmu_inc 113