1 ifndef _artim16inc ; avoid multiple inclusion 2_artim16inc equ 1 3 4 save 5 listing off ; no listing over this file 6 7;**************************************************************************** 8;* * 9;* AS 1.42 - File ARTIM16.INC * 10;* * 11;* contains SFR and Bit Definitions for ST62xx 16 Bit AR Timer * 12;* * 13;**************************************************************************** 14 15SCR1 sfr 0e8h ; Status Control Register 1 16PSC bfield SCR1,6,2 ; Clock Prescaler 17RELOAD bit 5,SCR1 ; Reload Enabled 18RUNRES bit 4,SCR1 ; Run/Reset 19OVFIEN bit 3,SCR1 ; Overflow Interrupt Enable 20OVFFLG bit 2,SCR1 ; Overflow Occured 21OVFMD bit 1,SCR1 ; Overflow Output Mode 22SCR2 sfr 0e1h ; Status Control Register 2 23CP1ERR bit 6,SCR2 ; CP1 Error Flag 24CP2ERR bit 5,SCR2 ; CP2 Error Flag 25CP1IEN bit 4,SCR2 ; CP1 Interrupt Enable 26CP1FLG bit 3,SCR2 ; CP1 Interrupt Flag 27CP1POL bit 2,SCR2 ; CP1 Edge Polarity Select 28RLDSEL bfield SCR2,0,2 ; Reload Source Select 29SCR3 sfr 0e2h ; Status Control Register 3 30CP2POL bit 7,SCR3 ; CP2 Edge Polarity Select 31CP2IEN bit 6,SCR3 ; CP2 Interrupt Enable 32CP2FLG bit 5,SCR3 ; CP2 Interrupt Flag 33CMPIEN bit 4,SCR3 ; Compare Interrupt Enable 34CMFLG bit 3,SCR3 ; Compare Flag 35ZEROIEN bit 2,SCR3 ; Compare to Zero Int Enable 36ZEROFLG bit 1,SCR3 ; Compare to Zero Flag 37PWMMD bit 0,SCR3 ; PWM Output Mode Control 38SCR4 sfr 0e3h ; Status Control Register 4 39OVFPOL bit 3,SCR4 ; Overflow Output Polarity 40OVFEN bit 2,SCR4 ; Overflow Output Enable 41PMPOL bit 1,SCR4 ; PWM Output Polarity 42PWMEN bit 0,SCR4 ; PWM Output Enable 43RLCPH sfr 0e9h ; Reload/Capture Register High Byte 44RLCPL sfr 0eah ; Reload/Capture Register Low Byte 45CPH sfr 0ebh ; Capture Register High Byte 46CPL sfr 0ech ; Capture Register Low Byte 47CMPH sfr 0edh ; Compare Register High Byte 48CMPL sfr 0eeh ; Compare Register Low Byte 49MASKH sfr 0efh ; Mask Register High Byte 50MASKL sfr 0e0h ; Mask Register Low Byte 51 52 restore 53 endif ; _artim16inc 54