1 ifndef __stm8stim3inc ; avoid multiple inclusion 2__stm8stim3inc equ 1 3 4 save 5 listing off ; no listing over this file 6 7;**************************************************************************** 8;* * 9;* AS 1.42 - File TIM3.INC * 10;* * 11;* contains SFR and Bit Definitions for STM8S Timer 3 * 12;* * 13;**************************************************************************** 14 15__deftim3 macro Base,DIER 16TIM3_CR1 label Base+$00 ; TIM3 control register 1 17TIM3_ARPE bit TIM3_CR1,7 ; Auto-reload preload enable 18TIM3_OPM bit TIM3_CR1,3 ; One-pulse mode 19TIM3_URS bit TIM3_CR1,2 ; Update request source 20TIM3_UDIS bit TIM3_CR1,1 ; Update disable 21TIM3_CEN bit TIM3_CR1,0 ; Counter enable 22TIM3_IER label Base+DIER+$01 ; TIM3 interrupt enable register 23TIM3_CC3IE bit TIM3_IER,3 ; Capture/compare 3 interrupt enable 24TIM3_CC2IE bit TIM3_IER,2 ; Capture/compare 2 interrupt enable 25TIM3_CC1IE bit TIM3_IER,1 ; Capture/compare 1 interrupt enable 26TIM3_UIE bit TIM3_IER,0 ; Update interrupt enable 27TIM3_SR1 label Base+DIER+$02 ; TIM3 status register 1 28TIM3_CC3IF bit TIM3_SR1,3 ; Capture/compare 3 interrupt flag 29TIM3_CC2IF bit TIM3_SR1,2 ; Capture/compare 2 interrupt flag 30TIM3_CC1IF bit TIM3_SR1,1 ; Capture/compare 1 interrupt flag 31TIM3_UIF bit TIM3_SR1,0 ; Update interrupt flag 32TIM3_SR2 label Base+DIER+$03 ; TIM3 status register 2 33TIM3_CC3OF bit TIM3_SR2,3 ; Capture/compare 3 overcapture flag 34TIM3_CC2OF bit TIM3_SR2,2 ; Capture/compare 2 overcapture flag 35TIM3_CC1OF bit TIM3_SR2,1 ; Capture/compare 1 overcapture flag 36TIM3_EGR label Base+DIER+$04 ; TIM3 event generation register 37TIM3_CC3G bit TIM3_EGR,3 ; Capture/compare 3 generation 38TIM3_CC2G bit TIM3_EGR,2 ; Capture/compare 2 generation 39TIM3_CC1G bit TIM3_EGR,1 ; Capture/compare 1 generation 40TIM3_UG bit TIM3_EGR,0 ; Update generation 41TIM3_CCMR1 label Base+DIER+$05 ; TIM3 capture/compare mode register 1 42TIM3_OC1M bfield TIM3_CCMR1,4,3 ; Output compare 1 mode 43TIM3_OC1PE bit TIM3_CCMR1,3 ; Output compare 1 preload enable 44TIM3_CC1S bfield TIM3_CCMR1,0,2 ; Capture/compare 1 selection 45TIM3_IC1F bfield TIM3_CCMR1,4,4 ; Input capture 1 filter 46TIM3_IC1PSC bfield TIM3_CCMR1,2,2 ; Input capture 1 prescaler 47TIM3_CCMR2 label Base+DIER+$06 ; TIM3 capture/compare mode register 2 48TIM3_OC2M bfield TIM3_CCMR2,4,3 ; Output compare 2 mode 49TIM3_OC2PE bit TIM3_CCMR2,3 ; Output compare 2 preload enable 50TIM3_CC2S bfield TIM3_CCMR2,0,2 ; Capture/compare 2 selection 51TIM3_IC2F bfield TIM3_CCMR2,4,4 ; Input capture 2 filter 52TIM3_IC2PSC bfield TIM3_CCMR2,2,2 ; Input capture 2 prescaler 53TIM3_CCER1 label Base+DIER+$07 ; TIM3 capture/compare enable register 1 54TIM3_CC2P bit TIM3_CCER1,5 ; Capture/compare 2 output polarity 55TIM3_CC2E bit TIM3_CCER1,4 ; Capture/compare 2 output enable 56TIM3_CC1P bit TIM3_CCER1,1 ; Capture/compare 1 output polarity 57TIM3_CC1E bit TIM3_CCER1,0 ; Capture/Compare 1 output Enable 58TIM3_CNTRH label Base+DIER+$08 ; TIM3 counter high 59TIM3_CNTRL label Base+DIER+$09 ; TIM3 counter low 60TIM3_PSCR label Base+DIER+$0a ; TIM3 prescaler register 61TIM3_ARRH label Base+DIER+$0b ; TIM3 auto-reload register high 62TIM3_ARRL label Base+DIER+$0c ; TIM3 auto-reload register low 63TIM3_CCR1H label Base+DIER+$0d ; TIM3 capture/compare register 1 high 64TIM3_CCR1L label Base+DIER+$0e ; TIM3 capture/compare register 1 low 65TIM3_CCR2H label Base+DIER+$0f ; TIM3 capture/compare reg. 2 high 66TIM3_CCR2L label Base+DIER+$10 ; TIM3 capture/compare register 2 low 67 endm 68 69 restore 70 endif ; __stm8stim3inc 71