1;; Machine description for AArch64 architecture. 2;; Copyright (C) 2009-2020 Free Software Foundation, Inc. 3;; Contributed by ARM Ltd. 4;; 5;; This file is part of GCC. 6;; 7;; GCC is free software; you can redistribute it and/or modify it 8;; under the terms of the GNU General Public License as published by 9;; the Free Software Foundation; either version 3, or (at your option) 10;; any later version. 11;; 12;; GCC is distributed in the hope that it will be useful, but 13;; WITHOUT ANY WARRANTY; without even the implied warranty of 14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15;; General Public License for more details. 16;; 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21(define_register_constraint "k" "STACK_REG" 22 "@internal The stack register.") 23 24(define_register_constraint "Ucs" "TAILCALL_ADDR_REGS" 25 "@internal Registers suitable for an indirect tail call") 26 27(define_register_constraint "w" "FP_REGS" 28 "Floating point and SIMD vector registers.") 29 30(define_register_constraint "Upa" "PR_REGS" 31 "SVE predicate registers p0 - p15.") 32 33(define_register_constraint "Upl" "PR_LO_REGS" 34 "SVE predicate registers p0 - p7.") 35 36(define_register_constraint "x" "FP_LO_REGS" 37 "Floating point and SIMD vector registers V0 - V15.") 38 39(define_register_constraint "y" "FP_LO8_REGS" 40 "Floating point and SIMD vector registers V0 - V7.") 41 42(define_constraint "c" 43 "@internal The condition code register." 44 (match_operand 0 "cc_register")) 45 46(define_constraint "I" 47 "A constant that can be used with an ADD operation." 48 (and (match_code "const_int") 49 (match_test "aarch64_uimm12_shift (ival)"))) 50 51(define_constraint "Uaa" 52 "@internal A constant that matches two uses of add instructions." 53 (and (match_code "const_int") 54 (match_test "aarch64_pluslong_strict_immedate (op, VOIDmode)"))) 55 56(define_constraint "Uai" 57 "@internal 58 A constraint that matches a VG-based constant that can be added by 59 a single INC or DEC." 60 (match_operand 0 "aarch64_sve_scalar_inc_dec_immediate")) 61 62(define_constraint "Uav" 63 "@internal 64 A constraint that matches a VG-based constant that can be added by 65 a single ADDVL or ADDPL." 66 (match_operand 0 "aarch64_sve_addvl_addpl_immediate")) 67 68(define_constraint "Uat" 69 "@internal 70 A constraint that matches a VG-based constant that can be added by 71 using multiple instructions, with one temporary register." 72 (match_operand 0 "aarch64_split_add_offset_immediate")) 73 74(define_constraint "J" 75 "A constant that can be used with a SUB operation (once negated)." 76 (and (match_code "const_int") 77 (match_test "aarch64_uimm12_shift (-ival)"))) 78 79;; We can't use the mode of a CONST_INT to determine the context in 80;; which it is being used, so we must have a separate constraint for 81;; each context. 82 83(define_constraint "K" 84 "A constant that can be used with a 32-bit logical operation." 85 (and (match_code "const_int") 86 (match_test "aarch64_bitmask_imm (ival, SImode)"))) 87 88(define_constraint "L" 89 "A constant that can be used with a 64-bit logical operation." 90 (and (match_code "const_int") 91 (match_test "aarch64_bitmask_imm (ival, DImode)"))) 92 93(define_constraint "M" 94 "A constant that can be used with a 32-bit MOV immediate operation." 95 (and (match_code "const_int") 96 (match_test "aarch64_move_imm (ival, SImode)"))) 97 98(define_constraint "N" 99 "A constant that can be used with a 64-bit MOV immediate operation." 100 (and (match_code "const_int") 101 (match_test "aarch64_move_imm (ival, DImode)"))) 102 103(define_constraint "Uti" 104 "A constant that can be used with a 128-bit MOV immediate operation." 105 (and (ior (match_code "const_int") 106 (match_code "const_wide_int")) 107 (match_test "aarch64_mov128_immediate (op)"))) 108 109(define_constraint "UsO" 110 "A constant that can be used with a 32-bit and operation." 111 (and (match_code "const_int") 112 (match_test "aarch64_and_bitmask_imm (ival, SImode)"))) 113 114(define_constraint "UsP" 115 "A constant that can be used with a 64-bit and operation." 116 (and (match_code "const_int") 117 (match_test "aarch64_and_bitmask_imm (ival, DImode)"))) 118 119(define_constraint "S" 120 "A constraint that matches an absolute symbolic address." 121 (and (match_code "const,symbol_ref,label_ref") 122 (match_test "aarch64_symbolic_address_p (op)"))) 123 124(define_constraint "Y" 125 "Floating point constant zero." 126 (and (match_code "const_double") 127 (match_test "aarch64_float_const_zero_rtx_p (op)"))) 128 129(define_constraint "Z" 130 "Integer or floating-point constant zero." 131 (match_test "op == CONST0_RTX (GET_MODE (op))")) 132 133(define_constraint "Ush" 134 "A constraint that matches an absolute symbolic address high part." 135 (and (match_code "high") 136 (match_test "aarch64_valid_symref (XEXP (op, 0), GET_MODE (XEXP (op, 0)))"))) 137 138(define_constraint "Usa" 139 "@internal 140 A constraint that matches an absolute symbolic address that can be 141 loaded by a single ADR." 142 (and (match_code "const,symbol_ref,label_ref") 143 (match_test "aarch64_symbolic_address_p (op)") 144 (match_test "aarch64_mov_operand_p (op, GET_MODE (op))"))) 145 146(define_constraint "Uss" 147 "@internal 148 A constraint that matches an immediate shift constant in SImode." 149 (and (match_code "const_int") 150 (match_test "(unsigned HOST_WIDE_INT) ival < 32"))) 151 152(define_constraint "Usn" 153 "A constant that can be used with a CCMN operation (once negated)." 154 (and (match_code "const_int") 155 (match_test "IN_RANGE (ival, -31, 0)"))) 156 157(define_constraint "Usd" 158 "@internal 159 A constraint that matches an immediate shift constant in DImode." 160 (and (match_code "const_int") 161 (match_test "(unsigned HOST_WIDE_INT) ival < 64"))) 162 163(define_constraint "Usf" 164 "@internal Usf is a symbol reference under the context where plt stub allowed." 165 (and (match_code "symbol_ref") 166 (match_test "!(aarch64_is_noplt_call_p (op) 167 || aarch64_is_long_call_p (op))"))) 168 169(define_constraint "Usg" 170 "@internal 171 A constraint that matches an immediate right shift constant in SImode 172 suitable for a SISD instruction." 173 (and (match_code "const_int") 174 (match_test "IN_RANGE (ival, 1, 31)"))) 175 176(define_constraint "Usj" 177 "@internal 178 A constraint that matches an immediate right shift constant in DImode 179 suitable for a SISD instruction." 180 (and (match_code "const_int") 181 (match_test "IN_RANGE (ival, 1, 63)"))) 182 183(define_constraint "UsM" 184 "@internal 185 A constraint that matches the immediate constant -1." 186 (match_test "op == constm1_rtx")) 187 188(define_constraint "Ulc" 189 "@internal 190 A constraint that matches a constant integer whose bits are consecutive ones 191 from the MSB." 192 (and (match_code "const_int") 193 (match_test "aarch64_high_bits_all_ones_p (ival)"))) 194 195(define_constraint "Usv" 196 "@internal 197 A constraint that matches a VG-based constant that can be loaded by 198 a single CNT[BHWD]." 199 (match_operand 0 "aarch64_sve_cnt_immediate")) 200 201(define_constraint "Usi" 202 "@internal 203 A constraint that matches an immediate operand valid for 204 the SVE INDEX instruction." 205 (match_operand 0 "aarch64_sve_index_immediate")) 206 207(define_constraint "Ui1" 208 "@internal 209 A constraint that matches the immediate constant +1." 210 (match_test "op == const1_rtx")) 211 212(define_constraint "Ui2" 213 "@internal 214 A constraint that matches the integers 0...3." 215 (and (match_code "const_int") 216 (match_test "(unsigned HOST_WIDE_INT) ival <= 3"))) 217 218(define_constraint "Ui3" 219 "@internal 220 A constraint that matches the integers 0...4." 221 (and (match_code "const_int") 222 (match_test "(unsigned HOST_WIDE_INT) ival <= 4"))) 223 224(define_constraint "Ui7" 225 "@internal 226 A constraint that matches the integers 0...7." 227 (and (match_code "const_int") 228 (match_test "(unsigned HOST_WIDE_INT) ival <= 7"))) 229 230(define_constraint "Up3" 231 "@internal 232 A constraint that matches the integers 2^(0...4)." 233 (and (match_code "const_int") 234 (match_test "(unsigned) exact_log2 (ival) <= 4"))) 235 236(define_constraint "Uph" 237 "@internal 238 A constraint that matches HImode integers zero extendable to 239 SImode plus_operand." 240 (and (match_code "const_int") 241 (match_test "aarch64_plushi_immediate (op, VOIDmode)"))) 242 243(define_memory_constraint "Q" 244 "A memory address which uses a single base register with no offset." 245 (and (match_code "mem") 246 (match_test "REG_P (XEXP (op, 0))"))) 247 248(define_memory_constraint "Ust" 249 "@internal 250 A memory address with 9bit unscaled offset." 251 (match_operand 0 "aarch64_9bit_offset_memory_operand")) 252 253(define_memory_constraint "Ump" 254 "@internal 255 A memory address suitable for a load/store pair operation." 256 (and (match_code "mem") 257 (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0), 258 true, ADDR_QUERY_LDP_STP)"))) 259 260;; Used for storing or loading pairs in an AdvSIMD register using an STP/LDP 261;; as a vector-concat. The address mode uses the same constraints as if it 262;; were for a single value. 263(define_memory_constraint "Umn" 264 "@internal 265 A memory address suitable for a load/store pair operation." 266 (and (match_code "mem") 267 (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0), 268 true, 269 ADDR_QUERY_LDP_STP_N)"))) 270 271(define_address_constraint "UPb" 272 "@internal 273 An address valid for SVE PRFB instructions." 274 (match_test "aarch64_sve_prefetch_operand_p (op, VNx16QImode)")) 275 276(define_address_constraint "UPd" 277 "@internal 278 An address valid for SVE PRFD instructions." 279 (match_test "aarch64_sve_prefetch_operand_p (op, VNx2DImode)")) 280 281(define_address_constraint "UPh" 282 "@internal 283 An address valid for SVE PRFH instructions." 284 (match_test "aarch64_sve_prefetch_operand_p (op, VNx8HImode)")) 285 286(define_address_constraint "UPw" 287 "@internal 288 An address valid for SVE PRFW instructions." 289 (match_test "aarch64_sve_prefetch_operand_p (op, VNx4SImode)")) 290 291(define_memory_constraint "Utf" 292 "@internal 293 An address valid for SVE LDFF1 instructions." 294 (and (match_code "mem") 295 (match_test "aarch64_sve_ldff1_operand_p (op)"))) 296 297(define_memory_constraint "Utn" 298 "@internal 299 An address valid for SVE LDNF1 instructions." 300 (and (match_code "mem") 301 (match_test "aarch64_sve_ldnf1_operand_p (op)"))) 302 303(define_memory_constraint "Utr" 304 "@internal 305 An address valid for SVE LDR and STR instructions (as distinct from 306 LD[1234] and ST[1234] patterns)." 307 (and (match_code "mem") 308 (match_test "aarch64_sve_ldr_operand_p (op)"))) 309 310(define_memory_constraint "Utv" 311 "@internal 312 An address valid for loading/storing opaque structure 313 types wider than TImode." 314 (and (match_code "mem") 315 (match_test "aarch64_simd_mem_operand_p (op)"))) 316 317(define_memory_constraint "Utq" 318 "@internal 319 An address valid for loading or storing a 128-bit AdvSIMD register" 320 (and (match_code "mem") 321 (match_test "aarch64_legitimate_address_p (V2DImode, 322 XEXP (op, 0), 1)"))) 323 324(define_memory_constraint "UtQ" 325 "@internal 326 An address valid for SVE LD1RQs." 327 (and (match_code "mem") 328 (match_test "aarch64_sve_ld1rq_operand_p (op)"))) 329 330(define_memory_constraint "UOb" 331 "@internal 332 An address valid for SVE LD1ROH." 333 (and (match_code "mem") 334 (match_test "aarch64_sve_ld1ro_operand_p (op, QImode)"))) 335 336(define_memory_constraint "UOh" 337 "@internal 338 An address valid for SVE LD1ROH." 339 (and (match_code "mem") 340 (match_test "aarch64_sve_ld1ro_operand_p (op, HImode)"))) 341 342 343(define_memory_constraint "UOw" 344 "@internal 345 An address valid for SVE LD1ROW." 346 (and (match_code "mem") 347 (match_test "aarch64_sve_ld1ro_operand_p (op, SImode)"))) 348 349(define_memory_constraint "UOd" 350 "@internal 351 An address valid for SVE LD1ROD." 352 (and (match_code "mem") 353 (match_test "aarch64_sve_ld1ro_operand_p (op, DImode)"))) 354 355(define_memory_constraint "Uty" 356 "@internal 357 An address valid for SVE LD1Rs." 358 (and (match_code "mem") 359 (match_test "aarch64_sve_ld1r_operand_p (op)"))) 360 361(define_memory_constraint "Utx" 362 "@internal 363 An address valid for SVE structure mov patterns (as distinct from 364 LD[234] and ST[234] patterns)." 365 (match_operand 0 "aarch64_sve_struct_memory_operand")) 366 367(define_constraint "Ufc" 368 "A floating point constant which can be used with an\ 369 FMOV immediate operation." 370 (and (match_code "const_double,const_vector") 371 (match_test "aarch64_float_const_representable_p (op)"))) 372 373(define_constraint "Uvi" 374 "A floating point constant which can be used with a\ 375 MOVI immediate operation." 376 (and (match_code "const_double") 377 (match_test "aarch64_can_const_movi_rtx_p (op, GET_MODE (op))"))) 378 379(define_constraint "Do" 380 "@internal 381 A constraint that matches vector of immediates for orr." 382 (and (match_code "const_vector") 383 (match_test "aarch64_simd_valid_immediate (op, NULL, 384 AARCH64_CHECK_ORR)"))) 385 386(define_constraint "Db" 387 "@internal 388 A constraint that matches vector of immediates for bic." 389 (and (match_code "const_vector") 390 (match_test "aarch64_simd_valid_immediate (op, NULL, 391 AARCH64_CHECK_BIC)"))) 392 393(define_constraint "Dn" 394 "@internal 395 A constraint that matches vector of immediates." 396 (and (match_code "const,const_vector") 397 (match_test "aarch64_simd_valid_immediate (op, NULL)"))) 398 399(define_constraint "Dh" 400 "@internal 401 A constraint that matches an immediate operand valid for\ 402 AdvSIMD scalar move in HImode." 403 (and (match_code "const_int") 404 (match_test "aarch64_simd_scalar_immediate_valid_for_move (op, 405 HImode)"))) 406 407(define_constraint "Dq" 408 "@internal 409 A constraint that matches an immediate operand valid for\ 410 AdvSIMD scalar move in QImode." 411 (and (match_code "const_int") 412 (match_test "aarch64_simd_scalar_immediate_valid_for_move (op, 413 QImode)"))) 414 415(define_constraint "Dt" 416 "@internal 417 A const_double which is the reciprocal of an exact power of two, can be 418 used in an scvtf with fract bits operation" 419 (and (match_code "const_double") 420 (match_test "aarch64_fpconst_pow2_recip (op) > 0"))) 421 422(define_constraint "Dl" 423 "@internal 424 A constraint that matches vector of immediates for left shifts." 425 (and (match_code "const,const_vector") 426 (match_test "aarch64_simd_shift_imm_p (op, GET_MODE (op), 427 true)"))) 428 429(define_constraint "Dr" 430 "@internal 431 A constraint that matches vector of immediates for right shifts." 432 (and (match_code "const,const_vector") 433 (match_test "aarch64_simd_shift_imm_p (op, GET_MODE (op), 434 false)"))) 435(define_constraint "Dz" 436 "@internal 437 A constraint that matches a vector of immediate zero." 438 (and (match_code "const,const_vector") 439 (match_test "op == CONST0_RTX (GET_MODE (op))"))) 440 441(define_constraint "Dm" 442 "@internal 443 A constraint that matches a vector of immediate minus one." 444 (and (match_code "const,const_vector") 445 (match_test "op == CONST1_RTX (GET_MODE (op))"))) 446 447(define_constraint "Dd" 448 "@internal 449 A constraint that matches an integer immediate operand valid\ 450 for AdvSIMD scalar operations in DImode." 451 (and (match_code "const_int") 452 (match_test "aarch64_can_const_movi_rtx_p (op, DImode)"))) 453 454(define_constraint "Ds" 455 "@internal 456 A constraint that matches an integer immediate operand valid\ 457 for AdvSIMD scalar operations in SImode." 458 (and (match_code "const_int") 459 (match_test "aarch64_can_const_movi_rtx_p (op, SImode)"))) 460 461(define_address_constraint "Dp" 462 "@internal 463 An address valid for a prefetch instruction." 464 (match_test "aarch64_address_valid_for_prefetch_p (op, true)")) 465 466(define_constraint "vgb" 467 "@internal 468 A constraint that matches an immediate offset valid for SVE LD1B 469 gather instructions." 470 (match_operand 0 "aarch64_sve_gather_immediate_b")) 471 472(define_constraint "vgd" 473 "@internal 474 A constraint that matches an immediate offset valid for SVE LD1D 475 gather instructions." 476 (match_operand 0 "aarch64_sve_gather_immediate_d")) 477 478(define_constraint "vgh" 479 "@internal 480 A constraint that matches an immediate offset valid for SVE LD1H 481 gather instructions." 482 (match_operand 0 "aarch64_sve_gather_immediate_h")) 483 484(define_constraint "vgw" 485 "@internal 486 A constraint that matches an immediate offset valid for SVE LD1W 487 gather instructions." 488 (match_operand 0 "aarch64_sve_gather_immediate_w")) 489 490(define_constraint "vsa" 491 "@internal 492 A constraint that matches an immediate operand valid for SVE 493 arithmetic instructions." 494 (match_operand 0 "aarch64_sve_arith_immediate")) 495 496(define_constraint "vsb" 497 "@internal 498 A constraint that matches an immediate operand valid for SVE UMAX 499 and UMIN operations." 500 (match_operand 0 "aarch64_sve_vsb_immediate")) 501 502(define_constraint "vsc" 503 "@internal 504 A constraint that matches a signed immediate operand valid for SVE 505 CMP instructions." 506 (match_operand 0 "aarch64_sve_cmp_vsc_immediate")) 507 508(define_constraint "vss" 509 "@internal 510 A constraint that matches a signed immediate operand valid for SVE 511 DUP instructions." 512 (match_test "aarch64_sve_dup_immediate_p (op)")) 513 514(define_constraint "vsd" 515 "@internal 516 A constraint that matches an unsigned immediate operand valid for SVE 517 CMP instructions." 518 (match_operand 0 "aarch64_sve_cmp_vsd_immediate")) 519 520(define_constraint "vsi" 521 "@internal 522 A constraint that matches a vector count operand valid for SVE INC and 523 DEC instructions." 524 (match_operand 0 "aarch64_sve_vector_inc_dec_immediate")) 525 526(define_constraint "vsn" 527 "@internal 528 A constraint that matches an immediate operand whose negative 529 is valid for SVE SUB instructions." 530 (match_operand 0 "aarch64_sve_sub_arith_immediate")) 531 532(define_constraint "vsQ" 533 "@internal 534 Like vsa, but additionally check that the immediate is nonnegative 535 when interpreted as a signed value." 536 (match_operand 0 "aarch64_sve_qadd_immediate")) 537 538(define_constraint "vsS" 539 "@internal 540 Like vsn, but additionally check that the immediate is negative 541 when interpreted as a signed value." 542 (match_operand 0 "aarch64_sve_qsub_immediate")) 543 544(define_constraint "vsl" 545 "@internal 546 A constraint that matches an immediate operand valid for SVE logical 547 operations." 548 (match_operand 0 "aarch64_sve_logical_immediate")) 549 550(define_constraint "vsm" 551 "@internal 552 A constraint that matches an immediate operand valid for SVE MUL, 553 SMAX and SMIN operations." 554 (match_operand 0 "aarch64_sve_vsm_immediate")) 555 556(define_constraint "vsA" 557 "@internal 558 A constraint that matches an immediate operand valid for SVE FADD 559 and FSUB operations." 560 (match_operand 0 "aarch64_sve_float_arith_immediate")) 561 562;; "B" for "bound". 563(define_constraint "vsB" 564 "@internal 565 A constraint that matches an immediate operand valid for SVE FMAX 566 and FMIN operations." 567 (match_operand 0 "aarch64_sve_float_maxmin_immediate")) 568 569(define_constraint "vsM" 570 "@internal 571 A constraint that matches an immediate operand valid for SVE FMUL 572 operations." 573 (match_operand 0 "aarch64_sve_float_mul_immediate")) 574 575(define_constraint "vsN" 576 "@internal 577 A constraint that matches the negative of vsA" 578 (match_operand 0 "aarch64_sve_float_negated_arith_immediate")) 579