1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992-2020 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com),
4 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 #define IN_TARGET_CODE 1
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "backend.h"
28 #include "target.h"
29 #include "rtl.h"
30 #include "tree.h"
31 #include "df.h"
32 #include "memmodel.h"
33 #include "tm_p.h"
34 #include "stringpool.h"
35 #include "attribs.h"
36 #include "optabs.h"
37 #include "regs.h"
38 #include "emit-rtl.h"
39 #include "recog.h"
40 #include "diagnostic-core.h"
41 #include "alias.h"
42 #include "stor-layout.h"
43 #include "varasm.h"
44 #include "calls.h"
45 #include "conditions.h"
46 #include "output.h"
47 #include "insn-attr.h"
48 #include "flags.h"
49 #include "explow.h"
50 #include "expr.h"
51 #include "tm-constrs.h"
52 #include "builtins.h"
53
54 /* This file should be included last. */
55 #include "target-def.h"
56
57 /* Classifies a h8300_src_operand or h8300_dst_operand.
58
59 H8OP_IMMEDIATE
60 A constant operand of some sort.
61
62 H8OP_REGISTER
63 An ordinary register.
64
65 H8OP_MEM_ABSOLUTE
66 A memory reference with a constant address.
67
68 H8OP_MEM_BASE
69 A memory reference with a register as its address.
70
71 H8OP_MEM_COMPLEX
72 Some other kind of memory reference. */
73 enum h8300_operand_class
74 {
75 H8OP_IMMEDIATE,
76 H8OP_REGISTER,
77 H8OP_MEM_ABSOLUTE,
78 H8OP_MEM_BASE,
79 H8OP_MEM_COMPLEX,
80 NUM_H8OPS
81 };
82
83 /* For a general two-operand instruction, element [X][Y] gives
84 the length of the opcode fields when the first operand has class
85 (X + 1) and the second has class Y. */
86 typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS];
87
88 /* Forward declarations. */
89 static const char *byte_reg (rtx, int);
90 static int h8300_interrupt_function_p (tree);
91 static int h8300_saveall_function_p (tree);
92 static int h8300_monitor_function_p (tree);
93 static int h8300_os_task_function_p (tree);
94 static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT, bool);
95 static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT);
96 static unsigned int compute_saved_regs (void);
97 static const char *cond_string (enum rtx_code);
98 static unsigned int h8300_asm_insn_count (const char *);
99 static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
100 static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
101 static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
102 static void h8300_print_operand_address (FILE *, machine_mode, rtx);
103 static void h8300_print_operand (FILE *, rtx, int);
104 static bool h8300_print_operand_punct_valid_p (unsigned char code);
105 #ifndef OBJECT_FORMAT_ELF
106 static void h8300_asm_named_section (const char *, unsigned int, tree);
107 #endif
108 static int h8300_register_move_cost (machine_mode, reg_class_t, reg_class_t);
109 static int h8300_and_costs (rtx);
110 static int h8300_shift_costs (rtx);
111 static void h8300_push_pop (int, int, bool, bool);
112 static int h8300_stack_offset_p (rtx, int);
113 static int h8300_ldm_stm_regno (rtx, int, int, int);
114 static void h8300_reorg (void);
115 static unsigned int h8300_constant_length (rtx);
116 static unsigned int h8300_displacement_length (rtx, int);
117 static unsigned int h8300_classify_operand (rtx, int, enum h8300_operand_class *);
118 static unsigned int h8300_length_from_table (rtx, rtx, const h8300_length_table *);
119 static unsigned int h8300_unary_length (rtx);
120 static unsigned int h8300_short_immediate_length (rtx);
121 static unsigned int h8300_bitfield_length (rtx, rtx);
122 static unsigned int h8300_binary_length (rtx_insn *, const h8300_length_table *);
123 static bool h8300_short_move_mem_p (rtx, enum rtx_code);
124 static unsigned int h8300_move_length (rtx *, const h8300_length_table *);
125 static bool h8300_hard_regno_scratch_ok (unsigned int);
126 static rtx h8300_get_index (rtx, machine_mode mode, int *);
127
128 /* CPU_TYPE, says what cpu we're compiling for. */
129 int cpu_type;
130
131 /* True if a #pragma interrupt has been seen for the current function. */
132 static int pragma_interrupt;
133
134 /* True if a #pragma saveall has been seen for the current function. */
135 static int pragma_saveall;
136
137 static const char *const names_big[] =
138 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
139
140 static const char *const names_extended[] =
141 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
142
143 static const char *const names_upper_extended[] =
144 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
145
146 /* Points to one of the above. */
147 /* ??? The above could be put in an array indexed by CPU_TYPE. */
148 const char * const *h8_reg_names;
149
150 /* Various operations needed by the following, indexed by CPU_TYPE. */
151
152 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
153
154 /* Value of MOVE_RATIO. */
155 int h8300_move_ratio;
156
157 /* See below where shifts are handled for explanation of this enum. */
158
159 enum shift_alg
160 {
161 SHIFT_INLINE,
162 SHIFT_ROT_AND,
163 SHIFT_SPECIAL,
164 SHIFT_LOOP
165 };
166
167 /* Symbols of the various shifts which can be used as indices. */
168
169 enum shift_type
170 {
171 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
172 };
173
174 /* Macros to keep the shift algorithm tables small. */
175 #define INL SHIFT_INLINE
176 #define ROT SHIFT_ROT_AND
177 #define LOP SHIFT_LOOP
178 #define SPC SHIFT_SPECIAL
179
180 /* The shift algorithms for each machine, mode, shift type, and shift
181 count are defined below. The three tables below correspond to
182 QImode, HImode, and SImode, respectively. Each table is organized
183 by, in the order of indices, machine, shift type, and shift count. */
184
185 static enum shift_alg shift_alg_qi[3][3][8] = {
186 {
187 /* TARGET_H8300 */
188 /* 0 1 2 3 4 5 6 7 */
189 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
190 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
191 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
192 },
193 {
194 /* TARGET_H8300H */
195 /* 0 1 2 3 4 5 6 7 */
196 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
197 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
198 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
199 },
200 {
201 /* TARGET_H8300S */
202 /* 0 1 2 3 4 5 6 7 */
203 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
204 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
205 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
206 }
207 };
208
209 static enum shift_alg shift_alg_hi[3][3][16] = {
210 {
211 /* TARGET_H8300 */
212 /* 0 1 2 3 4 5 6 7 */
213 /* 8 9 10 11 12 13 14 15 */
214 { INL, INL, INL, INL, INL, INL, INL, SPC,
215 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
216 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
217 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
218 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
219 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
220 },
221 {
222 /* TARGET_H8300H */
223 /* 0 1 2 3 4 5 6 7 */
224 /* 8 9 10 11 12 13 14 15 */
225 { INL, INL, INL, INL, INL, INL, INL, SPC,
226 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
227 { INL, INL, INL, INL, INL, INL, INL, SPC,
228 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
229 { INL, INL, INL, INL, INL, INL, INL, SPC,
230 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
231 },
232 {
233 /* TARGET_H8300S */
234 /* 0 1 2 3 4 5 6 7 */
235 /* 8 9 10 11 12 13 14 15 */
236 { INL, INL, INL, INL, INL, INL, INL, INL,
237 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
238 { INL, INL, INL, INL, INL, INL, INL, INL,
239 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
240 { INL, INL, INL, INL, INL, INL, INL, INL,
241 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
242 }
243 };
244
245 static enum shift_alg shift_alg_si[3][3][32] = {
246 {
247 /* TARGET_H8300 */
248 /* 0 1 2 3 4 5 6 7 */
249 /* 8 9 10 11 12 13 14 15 */
250 /* 16 17 18 19 20 21 22 23 */
251 /* 24 25 26 27 28 29 30 31 */
252 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
253 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
254 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
255 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
256 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
257 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
258 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
259 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
260 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
261 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
262 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
263 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
264 },
265 {
266 /* TARGET_H8300H */
267 /* 0 1 2 3 4 5 6 7 */
268 /* 8 9 10 11 12 13 14 15 */
269 /* 16 17 18 19 20 21 22 23 */
270 /* 24 25 26 27 28 29 30 31 */
271 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
272 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
273 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
274 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
275 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
276 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
277 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
278 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
279 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
280 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
281 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
282 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
283 },
284 {
285 /* TARGET_H8300S */
286 /* 0 1 2 3 4 5 6 7 */
287 /* 8 9 10 11 12 13 14 15 */
288 /* 16 17 18 19 20 21 22 23 */
289 /* 24 25 26 27 28 29 30 31 */
290 { INL, INL, INL, INL, INL, INL, INL, INL,
291 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
292 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
293 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
294 { INL, INL, INL, INL, INL, INL, INL, INL,
295 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
296 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
297 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
298 { INL, INL, INL, INL, INL, INL, INL, INL,
299 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
300 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
301 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
302 }
303 };
304
305 #undef INL
306 #undef ROT
307 #undef LOP
308 #undef SPC
309
310 enum h8_cpu
311 {
312 H8_300,
313 H8_300H,
314 H8_S
315 };
316
317 /* Initialize various cpu specific globals at start up. */
318
319 static void
h8300_option_override(void)320 h8300_option_override (void)
321 {
322 static const char *const h8_push_ops[2] = { "push" , "push.l" };
323 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
324 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
325
326 #ifndef OBJECT_FORMAT_ELF
327 if (TARGET_H8300SX)
328 {
329 error ("%<-msx%> is not supported in coff");
330 target_flags |= MASK_H8300S;
331 }
332 #endif
333
334 if (TARGET_H8300)
335 {
336 cpu_type = (int) CPU_H8300;
337 h8_reg_names = names_big;
338 }
339 else
340 {
341 /* For this we treat the H8/300H and H8S the same. */
342 cpu_type = (int) CPU_H8300H;
343 h8_reg_names = names_extended;
344 }
345 h8_push_op = h8_push_ops[cpu_type];
346 h8_pop_op = h8_pop_ops[cpu_type];
347 h8_mov_op = h8_mov_ops[cpu_type];
348
349 if (!TARGET_H8300S && TARGET_MAC)
350 {
351 error ("%<-ms2600%> is used without %<-ms%>");
352 target_flags |= MASK_H8300S_1;
353 }
354
355 if (TARGET_H8300 && TARGET_NORMAL_MODE)
356 {
357 error ("%<-mn%> is used without %<-mh%> or %<-ms%> or %<-msx%>");
358 target_flags ^= MASK_NORMAL_MODE;
359 }
360
361 if (! TARGET_H8300S && TARGET_EXR)
362 {
363 error ("%<-mexr%> is used without %<-ms%>");
364 target_flags |= MASK_H8300S_1;
365 }
366
367 if (TARGET_H8300 && TARGET_INT32)
368 {
369 error ("%<-mint32%> is not supported for H8300 and H8300L targets");
370 target_flags ^= MASK_INT32;
371 }
372
373 if ((!TARGET_H8300S && TARGET_EXR) && (!TARGET_H8300SX && TARGET_EXR))
374 {
375 error ("%<-mexr%> is used without %<-ms%> or %<-msx%>");
376 target_flags |= MASK_H8300S_1;
377 }
378
379 if ((!TARGET_H8300S && TARGET_NEXR) && (!TARGET_H8300SX && TARGET_NEXR))
380 {
381 warning (OPT_mno_exr, "%<-mno-exr%> is valid only with %<-ms%> or "
382 "%<-msx%> - option ignored");
383 }
384
385 #ifdef H8300_LINUX
386 if ((TARGET_NORMAL_MODE))
387 {
388 error ("%<-mn%> is not supported for linux targets");
389 target_flags ^= MASK_NORMAL_MODE;
390 }
391 #endif
392
393 /* Some of the shifts are optimized for speed by default.
394 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
395 If optimizing for size, change shift_alg for those shift to
396 SHIFT_LOOP. */
397 if (optimize_size)
398 {
399 /* H8/300 */
400 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
401 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
402 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
403 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
404
405 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
406 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
407
408 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
409 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
410
411 /* H8/300H */
412 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
413 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
414
415 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
416 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
417
418 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
419 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
420 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
421 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
422
423 /* H8S */
424 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
425 }
426
427 /* Work out a value for MOVE_RATIO. */
428 if (!TARGET_H8300SX)
429 {
430 /* Memory-memory moves are quite expensive without the
431 h8sx instructions. */
432 h8300_move_ratio = 3;
433 }
434 else if (flag_omit_frame_pointer)
435 {
436 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
437 sometimes be as short as two individual memory-to-memory moves,
438 but since they use all the call-saved registers, it seems better
439 to allow up to three moves here. */
440 h8300_move_ratio = 4;
441 }
442 else if (optimize_size)
443 {
444 /* In this case we don't use movmd sequences since they tend
445 to be longer than calls to memcpy(). Memory-to-memory
446 moves are cheaper than for !TARGET_H8300SX, so it makes
447 sense to have a slightly higher threshold. */
448 h8300_move_ratio = 4;
449 }
450 else
451 {
452 /* We use movmd sequences for some moves since it can be quicker
453 than calling memcpy(). The sequences will need to save and
454 restore er6 though, so bump up the cost. */
455 h8300_move_ratio = 6;
456 }
457
458 /* This target defaults to strict volatile bitfields. */
459 if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
460 flag_strict_volatile_bitfields = 1;
461 }
462
463 /* Return the byte register name for a register rtx X. B should be 0
464 if you want a lower byte register. B should be 1 if you want an
465 upper byte register. */
466
467 static const char *
byte_reg(rtx x,int b)468 byte_reg (rtx x, int b)
469 {
470 static const char *const names_small[] = {
471 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
472 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
473 };
474
475 gcc_assert (REG_P (x));
476
477 return names_small[REGNO (x) * 2 + b];
478 }
479
480 /* REGNO must be saved/restored across calls if this macro is true. */
481
482 #define WORD_REG_USED(regno) \
483 (regno < SP_REG \
484 /* No need to save registers if this function will not return. */ \
485 && ! TREE_THIS_VOLATILE (current_function_decl) \
486 && (h8300_saveall_function_p (current_function_decl) \
487 /* Save any call saved register that was used. */ \
488 || (df_regs_ever_live_p (regno) \
489 && !call_used_or_fixed_reg_p (regno)) \
490 /* Save the frame pointer if it was used. */ \
491 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
492 /* Save any register used in an interrupt handler. */ \
493 || (h8300_current_function_interrupt_function_p () \
494 && df_regs_ever_live_p (regno)) \
495 /* Save call clobbered registers in non-leaf interrupt \
496 handlers. */ \
497 || (h8300_current_function_interrupt_function_p () \
498 && call_used_or_fixed_reg_p (regno) \
499 && !crtl->is_leaf)))
500
501 /* We use this to wrap all emitted insns in the prologue. */
502 static rtx_insn *
F(rtx_insn * x,bool set_it)503 F (rtx_insn *x, bool set_it)
504 {
505 if (set_it)
506 RTX_FRAME_RELATED_P (x) = 1;
507 return x;
508 }
509
510 /* Mark all the subexpressions of the PARALLEL rtx PAR as
511 frame-related. Return PAR.
512
513 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
514 PARALLEL rtx other than the first if they do not have the
515 FRAME_RELATED flag set on them. */
516 static rtx
Fpa(rtx par)517 Fpa (rtx par)
518 {
519 int len = XVECLEN (par, 0);
520 int i;
521
522 for (i = 0; i < len; i++)
523 RTX_FRAME_RELATED_P (XVECEXP (par, 0, i)) = 1;
524
525 return par;
526 }
527
528 /* Output assembly language to FILE for the operation OP with operand size
529 SIZE to adjust the stack pointer. */
530
531 static void
h8300_emit_stack_adjustment(int sign,HOST_WIDE_INT size,bool in_prologue)532 h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size, bool in_prologue)
533 {
534 /* If the frame size is 0, we don't have anything to do. */
535 if (size == 0)
536 return;
537
538 /* H8/300 cannot add/subtract a large constant with a single
539 instruction. If a temporary register is available, load the
540 constant to it and then do the addition. */
541 if (TARGET_H8300
542 && size > 4
543 && !h8300_current_function_interrupt_function_p ()
544 && !(cfun->static_chain_decl != NULL && sign < 0))
545 {
546 rtx r3 = gen_rtx_REG (Pmode, 3);
547 F (emit_insn (gen_movhi (r3, GEN_INT (sign * size))), in_prologue);
548 F (emit_insn (gen_addhi3 (stack_pointer_rtx,
549 stack_pointer_rtx, r3)), in_prologue);
550 }
551 else
552 {
553 /* The stack adjustment made here is further optimized by the
554 splitter. In case of H8/300, the splitter always splits the
555 addition emitted here to make the adjustment interrupt-safe.
556 FIXME: We don't always tag those, because we don't know what
557 the splitter will do. */
558 if (Pmode == HImode)
559 {
560 rtx_insn *x = emit_insn (gen_addhi3 (stack_pointer_rtx,
561 stack_pointer_rtx,
562 GEN_INT (sign * size)));
563 if (size < 4)
564 F (x, in_prologue);
565 }
566 else
567 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
568 stack_pointer_rtx, GEN_INT (sign * size))), in_prologue);
569 }
570 }
571
572 /* Round up frame size SIZE. */
573
574 static HOST_WIDE_INT
round_frame_size(HOST_WIDE_INT size)575 round_frame_size (HOST_WIDE_INT size)
576 {
577 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
578 & -STACK_BOUNDARY / BITS_PER_UNIT);
579 }
580
581 /* Compute which registers to push/pop.
582 Return a bit vector of registers. */
583
584 static unsigned int
compute_saved_regs(void)585 compute_saved_regs (void)
586 {
587 unsigned int saved_regs = 0;
588 int regno;
589
590 /* Construct a bit vector of registers to be pushed/popped. */
591 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
592 {
593 if (WORD_REG_USED (regno))
594 saved_regs |= 1 << regno;
595 }
596
597 /* Don't push/pop the frame pointer as it is treated separately. */
598 if (frame_pointer_needed)
599 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM);
600
601 return saved_regs;
602 }
603
604 /* Emit an insn to push register RN. */
605
606 static rtx
push(int rn,bool in_prologue)607 push (int rn, bool in_prologue)
608 {
609 rtx reg = gen_rtx_REG (word_mode, rn);
610 rtx x;
611
612 if (TARGET_H8300)
613 x = gen_push_h8300 (reg);
614 else if (!TARGET_NORMAL_MODE)
615 x = gen_push_h8300hs_advanced (reg);
616 else
617 x = gen_push_h8300hs_normal (reg);
618 x = F (emit_insn (x), in_prologue);
619 add_reg_note (x, REG_INC, stack_pointer_rtx);
620 return x;
621 }
622
623 /* Emit an insn to pop register RN. */
624
625 static rtx
pop(int rn)626 pop (int rn)
627 {
628 rtx reg = gen_rtx_REG (word_mode, rn);
629 rtx x;
630
631 if (TARGET_H8300)
632 x = gen_pop_h8300 (reg);
633 else if (!TARGET_NORMAL_MODE)
634 x = gen_pop_h8300hs_advanced (reg);
635 else
636 x = gen_pop_h8300hs_normal (reg);
637 x = emit_insn (x);
638 add_reg_note (x, REG_INC, stack_pointer_rtx);
639 return x;
640 }
641
642 /* Emit an instruction to push or pop NREGS consecutive registers
643 starting at register REGNO. POP_P selects a pop rather than a
644 push and RETURN_P is true if the instruction should return.
645
646 It must be possible to do the requested operation in a single
647 instruction. If NREGS == 1 && !RETURN_P, use a normal push
648 or pop insn. Otherwise emit a parallel of the form:
649
650 (parallel
651 [(return) ;; if RETURN_P
652 (save or restore REGNO)
653 (save or restore REGNO + 1)
654 ...
655 (save or restore REGNO + NREGS - 1)
656 (set sp (plus sp (const_int adjust)))] */
657
658 static void
h8300_push_pop(int regno,int nregs,bool pop_p,bool return_p)659 h8300_push_pop (int regno, int nregs, bool pop_p, bool return_p)
660 {
661 int i, j;
662 rtvec vec;
663 rtx sp, offset, x;
664
665 /* See whether we can use a simple push or pop. */
666 if (!return_p && nregs == 1)
667 {
668 if (pop_p)
669 pop (regno);
670 else
671 push (regno, false);
672 return;
673 }
674
675 /* We need one element for the return insn, if present, one for each
676 register, and one for stack adjustment. */
677 vec = rtvec_alloc ((return_p ? 1 : 0) + nregs + 1);
678 sp = stack_pointer_rtx;
679 i = 0;
680
681 /* Add the return instruction. */
682 if (return_p)
683 {
684 RTVEC_ELT (vec, i) = ret_rtx;
685 i++;
686 }
687
688 /* Add the register moves. */
689 for (j = 0; j < nregs; j++)
690 {
691 rtx lhs, rhs;
692
693 if (pop_p)
694 {
695 /* Register REGNO + NREGS - 1 is popped first. Before the
696 stack adjustment, its slot is at address @sp. */
697 lhs = gen_rtx_REG (SImode, regno + j);
698 rhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp,
699 (nregs - j - 1) * 4));
700 }
701 else
702 {
703 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
704 lhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp, (j + 1) * -4));
705 rhs = gen_rtx_REG (SImode, regno + j);
706 }
707 RTVEC_ELT (vec, i + j) = gen_rtx_SET (lhs, rhs);
708 }
709
710 /* Add the stack adjustment. */
711 offset = GEN_INT ((pop_p ? nregs : -nregs) * 4);
712 RTVEC_ELT (vec, i + j) = gen_rtx_SET (sp, gen_rtx_PLUS (Pmode, sp, offset));
713
714 x = gen_rtx_PARALLEL (VOIDmode, vec);
715 if (!pop_p)
716 x = Fpa (x);
717
718 if (return_p)
719 emit_jump_insn (x);
720 else
721 emit_insn (x);
722 }
723
724 /* Return true if X has the value sp + OFFSET. */
725
726 static int
h8300_stack_offset_p(rtx x,int offset)727 h8300_stack_offset_p (rtx x, int offset)
728 {
729 if (offset == 0)
730 return x == stack_pointer_rtx;
731
732 return (GET_CODE (x) == PLUS
733 && XEXP (x, 0) == stack_pointer_rtx
734 && GET_CODE (XEXP (x, 1)) == CONST_INT
735 && INTVAL (XEXP (x, 1)) == offset);
736 }
737
738 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
739 something that may be an ldm or stm instruction. If it fits
740 the required template, return the register it loads or stores,
741 otherwise return -1.
742
743 LOAD_P is true if X should be a load, false if it should be a store.
744 NREGS is the number of registers that the whole instruction is expected
745 to load or store. INDEX is the index of the register that X should
746 load or store, relative to the lowest-numbered register. */
747
748 static int
h8300_ldm_stm_regno(rtx x,int load_p,int index,int nregs)749 h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs)
750 {
751 int regindex, memindex, offset;
752
753 if (load_p)
754 regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4;
755 else
756 memindex = 0, regindex = 1, offset = (index + 1) * -4;
757
758 if (GET_CODE (x) == SET
759 && GET_CODE (XEXP (x, regindex)) == REG
760 && GET_CODE (XEXP (x, memindex)) == MEM
761 && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset))
762 return REGNO (XEXP (x, regindex));
763
764 return -1;
765 }
766
767 /* Return true if the elements of VEC starting at FIRST describe an
768 ldm or stm instruction (LOAD_P says which). */
769
770 int
h8300_ldm_stm_parallel(rtvec vec,int load_p,int first)771 h8300_ldm_stm_parallel (rtvec vec, int load_p, int first)
772 {
773 rtx last;
774 int nregs, i, regno, adjust;
775
776 /* There must be a stack adjustment, a register move, and at least one
777 other operation (a return or another register move). */
778 if (GET_NUM_ELEM (vec) < 3)
779 return false;
780
781 /* Get the range of registers to be pushed or popped. */
782 nregs = GET_NUM_ELEM (vec) - first - 1;
783 regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs);
784
785 /* Check that the call to h8300_ldm_stm_regno succeeded and
786 that we're only dealing with GPRs. */
787 if (regno < 0 || regno + nregs > 8)
788 return false;
789
790 /* 2-register h8s instructions must start with an even-numbered register.
791 3- and 4-register instructions must start with er0 or er4. */
792 if (!TARGET_H8300SX)
793 {
794 if ((regno & 1) != 0)
795 return false;
796 if (nregs > 2 && (regno & 3) != 0)
797 return false;
798 }
799
800 /* Check the other loads or stores. */
801 for (i = 1; i < nregs; i++)
802 if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs)
803 != regno + i)
804 return false;
805
806 /* Check the stack adjustment. */
807 last = RTVEC_ELT (vec, first + nregs);
808 adjust = (load_p ? nregs : -nregs) * 4;
809 return (GET_CODE (last) == SET
810 && SET_DEST (last) == stack_pointer_rtx
811 && h8300_stack_offset_p (SET_SRC (last), adjust));
812 }
813
814 /* This is what the stack looks like after the prolog of
815 a function with a frame has been set up:
816
817 <args>
818 PC
819 FP <- fp
820 <locals>
821 <saved registers> <- sp
822
823 This is what the stack looks like after the prolog of
824 a function which doesn't have a frame:
825
826 <args>
827 PC
828 <locals>
829 <saved registers> <- sp
830 */
831
832 /* Generate RTL code for the function prologue. */
833
834 void
h8300_expand_prologue(void)835 h8300_expand_prologue (void)
836 {
837 int regno;
838 int saved_regs;
839 int n_regs;
840
841 /* If the current function has the OS_Task attribute set, then
842 we have a naked prologue. */
843 if (h8300_os_task_function_p (current_function_decl))
844 return;
845
846 if (h8300_monitor_function_p (current_function_decl))
847 /* The monitor function act as normal functions, which means it
848 can accept parameters and return values. In addition to this,
849 interrupts are masked in prologue and return with "rte" in epilogue. */
850 emit_insn (gen_monitor_prologue ());
851
852 if (frame_pointer_needed)
853 {
854 /* Push fp. */
855 push (HARD_FRAME_POINTER_REGNUM, true);
856 F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx), true);
857 }
858
859 /* Push the rest of the registers in ascending order. */
860 saved_regs = compute_saved_regs ();
861 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
862 {
863 n_regs = 1;
864 if (saved_regs & (1 << regno))
865 {
866 if (TARGET_H8300S)
867 {
868 /* See how many registers we can push at the same time. */
869 if ((TARGET_H8300SX || (regno & 3) == 0)
870 && ((saved_regs >> regno) & 0x0f) == 0x0f)
871 n_regs = 4;
872
873 else if ((TARGET_H8300SX || (regno & 3) == 0)
874 && ((saved_regs >> regno) & 0x07) == 0x07)
875 n_regs = 3;
876
877 else if ((TARGET_H8300SX || (regno & 1) == 0)
878 && ((saved_regs >> regno) & 0x03) == 0x03)
879 n_regs = 2;
880 }
881
882 h8300_push_pop (regno, n_regs, false, false);
883 }
884 }
885
886 /* Leave room for locals. */
887 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true);
888
889 if (flag_stack_usage_info)
890 current_function_static_stack_size
891 = round_frame_size (get_frame_size ())
892 + (__builtin_popcount (saved_regs) * UNITS_PER_WORD)
893 + (frame_pointer_needed ? UNITS_PER_WORD : 0);
894 }
895
896 /* Return nonzero if we can use "rts" for the function currently being
897 compiled. */
898
899 int
h8300_can_use_return_insn_p(void)900 h8300_can_use_return_insn_p (void)
901 {
902 return (reload_completed
903 && !frame_pointer_needed
904 && get_frame_size () == 0
905 && compute_saved_regs () == 0);
906 }
907
908 /* Generate RTL code for the function epilogue. */
909
910 void
h8300_expand_epilogue(void)911 h8300_expand_epilogue (void)
912 {
913 int regno;
914 int saved_regs;
915 int n_regs;
916 HOST_WIDE_INT frame_size;
917 bool returned_p;
918
919 if (h8300_os_task_function_p (current_function_decl))
920 /* OS_Task epilogues are nearly naked -- they just have an
921 rts instruction. */
922 return;
923
924 frame_size = round_frame_size (get_frame_size ());
925 returned_p = false;
926
927 /* Deallocate locals. */
928 h8300_emit_stack_adjustment (1, frame_size, false);
929
930 /* Pop the saved registers in descending order. */
931 saved_regs = compute_saved_regs ();
932 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
933 {
934 n_regs = 1;
935 if (saved_regs & (1 << regno))
936 {
937 if (TARGET_H8300S)
938 {
939 /* See how many registers we can pop at the same time. */
940 if ((TARGET_H8300SX || (regno & 3) == 3)
941 && ((saved_regs << 3 >> regno) & 0x0f) == 0x0f)
942 n_regs = 4;
943
944 else if ((TARGET_H8300SX || (regno & 3) == 2)
945 && ((saved_regs << 2 >> regno) & 0x07) == 0x07)
946 n_regs = 3;
947
948 else if ((TARGET_H8300SX || (regno & 1) == 1)
949 && ((saved_regs << 1 >> regno) & 0x03) == 0x03)
950 n_regs = 2;
951 }
952
953 /* See if this pop would be the last insn before the return.
954 If so, use rte/l or rts/l instead of pop or ldm.l. */
955 if (TARGET_H8300SX
956 && !frame_pointer_needed
957 && frame_size == 0
958 && (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0)
959 returned_p = true;
960
961 h8300_push_pop (regno - n_regs + 1, n_regs, true, returned_p);
962 }
963 }
964
965 /* Pop frame pointer if we had one. */
966 if (frame_pointer_needed)
967 {
968 if (TARGET_H8300SX)
969 returned_p = true;
970 h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, true, returned_p);
971 }
972
973 if (!returned_p)
974 emit_jump_insn (ret_rtx);
975 }
976
977 /* Return nonzero if the current function is an interrupt
978 function. */
979
980 int
h8300_current_function_interrupt_function_p(void)981 h8300_current_function_interrupt_function_p (void)
982 {
983 return (h8300_interrupt_function_p (current_function_decl));
984 }
985
986 int
h8300_current_function_monitor_function_p()987 h8300_current_function_monitor_function_p ()
988 {
989 return (h8300_monitor_function_p (current_function_decl));
990 }
991
992 /* Output assembly code for the start of the file. */
993
994 static void
h8300_file_start(void)995 h8300_file_start (void)
996 {
997 default_file_start ();
998
999 if (TARGET_H8300SX)
1000 fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file);
1001 else if (TARGET_H8300S)
1002 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
1003 else if (TARGET_H8300H)
1004 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
1005 }
1006
1007 /* Output assembly language code for the end of file. */
1008
1009 static void
h8300_file_end(void)1010 h8300_file_end (void)
1011 {
1012 fputs ("\t.end\n", asm_out_file);
1013 }
1014
1015 /* Split an add of a small constant into two adds/subs insns.
1016
1017 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
1018 instead of adds/subs. */
1019
1020 void
split_adds_subs(machine_mode mode,rtx * operands)1021 split_adds_subs (machine_mode mode, rtx *operands)
1022 {
1023 HOST_WIDE_INT val = INTVAL (operands[1]);
1024 rtx reg = operands[0];
1025 HOST_WIDE_INT sign = 1;
1026 HOST_WIDE_INT amount;
1027 rtx (*gen_add) (rtx, rtx, rtx);
1028
1029 /* Force VAL to be positive so that we do not have to consider the
1030 sign. */
1031 if (val < 0)
1032 {
1033 val = -val;
1034 sign = -1;
1035 }
1036
1037 switch (mode)
1038 {
1039 case E_HImode:
1040 gen_add = gen_addhi3;
1041 break;
1042
1043 case E_SImode:
1044 gen_add = gen_addsi3;
1045 break;
1046
1047 default:
1048 gcc_unreachable ();
1049 }
1050
1051 /* Try different amounts in descending order. */
1052 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
1053 amount > 0;
1054 amount /= 2)
1055 {
1056 for (; val >= amount; val -= amount)
1057 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
1058 }
1059
1060 return;
1061 }
1062
1063 /* Handle machine specific pragmas for compatibility with existing
1064 compilers for the H8/300.
1065
1066 pragma saveall generates prologue/epilogue code which saves and
1067 restores all the registers on function entry.
1068
1069 pragma interrupt saves and restores all registers, and exits with
1070 an rte instruction rather than an rts. A pointer to a function
1071 with this attribute may be safely used in an interrupt vector. */
1072
1073 void
h8300_pr_interrupt(struct cpp_reader * pfile ATTRIBUTE_UNUSED)1074 h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1075 {
1076 pragma_interrupt = 1;
1077 }
1078
1079 void
h8300_pr_saveall(struct cpp_reader * pfile ATTRIBUTE_UNUSED)1080 h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1081 {
1082 pragma_saveall = 1;
1083 }
1084
1085 /* If the next function argument ARG is to be passed in a register, return
1086 a reg RTX for the hard register in which to pass the argument. CUM
1087 represents the state after the last argument. If the argument is to
1088 be pushed, NULL_RTX is returned.
1089
1090 On the H8/300 all normal args are pushed, unless -mquickcall in which
1091 case the first 3 arguments are passed in registers. */
1092
1093 static rtx
h8300_function_arg(cumulative_args_t cum_v,const function_arg_info & arg)1094 h8300_function_arg (cumulative_args_t cum_v, const function_arg_info &arg)
1095 {
1096 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1097
1098 static const char *const hand_list[] = {
1099 "__main",
1100 "__cmpsi2",
1101 "__divhi3",
1102 "__modhi3",
1103 "__udivhi3",
1104 "__umodhi3",
1105 "__divsi3",
1106 "__modsi3",
1107 "__udivsi3",
1108 "__umodsi3",
1109 "__mulhi3",
1110 "__mulsi3",
1111 "__reg_memcpy",
1112 "__reg_memset",
1113 "__ucmpsi2",
1114 0,
1115 };
1116
1117 rtx result = NULL_RTX;
1118 const char *fname;
1119 int regpass = 0;
1120
1121 /* Never pass unnamed arguments in registers. */
1122 if (!arg.named)
1123 return NULL_RTX;
1124
1125 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1126 if (TARGET_QUICKCALL)
1127 regpass = 3;
1128
1129 /* If calling hand written assembler, use 4 regs of args. */
1130 if (cum->libcall)
1131 {
1132 const char * const *p;
1133
1134 fname = XSTR (cum->libcall, 0);
1135
1136 /* See if this libcall is one of the hand coded ones. */
1137 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1138 ;
1139
1140 if (*p)
1141 regpass = 4;
1142 }
1143
1144 if (regpass)
1145 {
1146 int size = arg.promoted_size_in_bytes ();
1147 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1148 && cum->nbytes / UNITS_PER_WORD <= 3)
1149 result = gen_rtx_REG (arg.mode, cum->nbytes / UNITS_PER_WORD);
1150 }
1151
1152 return result;
1153 }
1154
1155 /* Update the data in CUM to advance over argument ARG. */
1156
1157 static void
h8300_function_arg_advance(cumulative_args_t cum_v,const function_arg_info & arg)1158 h8300_function_arg_advance (cumulative_args_t cum_v,
1159 const function_arg_info &arg)
1160 {
1161 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1162
1163 cum->nbytes += ((arg.promoted_size_in_bytes () + UNITS_PER_WORD - 1)
1164 & -UNITS_PER_WORD);
1165 }
1166
1167
1168 /* Implements TARGET_REGISTER_MOVE_COST.
1169
1170 Any SI register-to-register move may need to be reloaded,
1171 so inmplement h8300_register_move_cost to return > 2 so that reload never
1172 shortcuts. */
1173
1174 static int
h8300_register_move_cost(machine_mode mode ATTRIBUTE_UNUSED,reg_class_t from,reg_class_t to)1175 h8300_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
1176 reg_class_t from, reg_class_t to)
1177 {
1178 if (from == MAC_REGS || to == MAC_REG)
1179 return 6;
1180 else
1181 return 3;
1182 }
1183
1184 /* Compute the cost of an and insn. */
1185
1186 static int
h8300_and_costs(rtx x)1187 h8300_and_costs (rtx x)
1188 {
1189 rtx operands[4];
1190
1191 if (GET_MODE (x) == QImode)
1192 return 1;
1193
1194 if (GET_MODE (x) != HImode
1195 && GET_MODE (x) != SImode)
1196 return 100;
1197
1198 operands[0] = NULL;
1199 operands[1] = XEXP (x, 0);
1200 operands[2] = XEXP (x, 1);
1201 operands[3] = x;
1202 return compute_logical_op_length (GET_MODE (x), operands) / 2;
1203 }
1204
1205 /* Compute the cost of a shift insn. */
1206
1207 static int
h8300_shift_costs(rtx x)1208 h8300_shift_costs (rtx x)
1209 {
1210 rtx operands[4];
1211
1212 if (GET_MODE (x) != QImode
1213 && GET_MODE (x) != HImode
1214 && GET_MODE (x) != SImode)
1215 return 100;
1216
1217 operands[0] = NULL;
1218 operands[1] = NULL;
1219 operands[2] = XEXP (x, 1);
1220 operands[3] = x;
1221 return compute_a_shift_length (NULL, operands) / 2;
1222 }
1223
1224 /* Worker function for TARGET_RTX_COSTS. */
1225
1226 static bool
h8300_rtx_costs(rtx x,machine_mode mode ATTRIBUTE_UNUSED,int outer_code,int opno ATTRIBUTE_UNUSED,int * total,bool speed)1227 h8300_rtx_costs (rtx x, machine_mode mode ATTRIBUTE_UNUSED, int outer_code,
1228 int opno ATTRIBUTE_UNUSED, int *total, bool speed)
1229 {
1230 int code = GET_CODE (x);
1231
1232 if (TARGET_H8300SX && outer_code == MEM)
1233 {
1234 /* Estimate the number of execution states needed to calculate
1235 the address. */
1236 if (register_operand (x, VOIDmode)
1237 || GET_CODE (x) == POST_INC
1238 || GET_CODE (x) == POST_DEC
1239 || CONSTANT_P (x))
1240 *total = 0;
1241 else
1242 *total = COSTS_N_INSNS (1);
1243 return true;
1244 }
1245
1246 switch (code)
1247 {
1248 case CONST_INT:
1249 {
1250 HOST_WIDE_INT n = INTVAL (x);
1251
1252 if (TARGET_H8300SX)
1253 {
1254 /* Constant operands need the same number of processor
1255 states as register operands. Although we could try to
1256 use a size-based cost for !speed, the lack of
1257 of a mode makes the results very unpredictable. */
1258 *total = 0;
1259 return true;
1260 }
1261 if (n >= -4 && n <= 4)
1262 {
1263 switch ((int) n)
1264 {
1265 case 0:
1266 *total = 0;
1267 return true;
1268 case 1:
1269 case 2:
1270 case -1:
1271 case -2:
1272 *total = 0 + (outer_code == SET);
1273 return true;
1274 case 4:
1275 case -4:
1276 if (TARGET_H8300H || TARGET_H8300S)
1277 *total = 0 + (outer_code == SET);
1278 else
1279 *total = 1;
1280 return true;
1281 }
1282 }
1283 *total = 1;
1284 return true;
1285 }
1286
1287 case CONST:
1288 case LABEL_REF:
1289 case SYMBOL_REF:
1290 if (TARGET_H8300SX)
1291 {
1292 /* See comment for CONST_INT. */
1293 *total = 0;
1294 return true;
1295 }
1296 *total = 3;
1297 return true;
1298
1299 case CONST_DOUBLE:
1300 *total = 20;
1301 return true;
1302
1303 case COMPARE:
1304 if (XEXP (x, 1) == const0_rtx)
1305 *total = 0;
1306 return false;
1307
1308 case AND:
1309 if (!h8300_dst_operand (XEXP (x, 0), VOIDmode)
1310 || !h8300_src_operand (XEXP (x, 1), VOIDmode))
1311 return false;
1312 *total = COSTS_N_INSNS (h8300_and_costs (x));
1313 return true;
1314
1315 /* We say that MOD and DIV are so expensive because otherwise we'll
1316 generate some really horrible code for division of a power of two. */
1317 case MOD:
1318 case DIV:
1319 case UMOD:
1320 case UDIV:
1321 if (TARGET_H8300SX)
1322 switch (GET_MODE (x))
1323 {
1324 case E_QImode:
1325 case E_HImode:
1326 *total = COSTS_N_INSNS (!speed ? 4 : 10);
1327 return false;
1328
1329 case E_SImode:
1330 *total = COSTS_N_INSNS (!speed ? 4 : 18);
1331 return false;
1332
1333 default:
1334 break;
1335 }
1336 *total = COSTS_N_INSNS (12);
1337 return true;
1338
1339 case MULT:
1340 if (TARGET_H8300SX)
1341 switch (GET_MODE (x))
1342 {
1343 case E_QImode:
1344 case E_HImode:
1345 *total = COSTS_N_INSNS (2);
1346 return false;
1347
1348 case E_SImode:
1349 *total = COSTS_N_INSNS (5);
1350 return false;
1351
1352 default:
1353 break;
1354 }
1355 *total = COSTS_N_INSNS (4);
1356 return true;
1357
1358 case ASHIFT:
1359 case ASHIFTRT:
1360 case LSHIFTRT:
1361 if (h8sx_binary_shift_operator (x, VOIDmode))
1362 {
1363 *total = COSTS_N_INSNS (2);
1364 return false;
1365 }
1366 else if (h8sx_unary_shift_operator (x, VOIDmode))
1367 {
1368 *total = COSTS_N_INSNS (1);
1369 return false;
1370 }
1371 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1372 return true;
1373
1374 case ROTATE:
1375 case ROTATERT:
1376 if (GET_MODE (x) == HImode)
1377 *total = 2;
1378 else
1379 *total = 8;
1380 return true;
1381
1382 default:
1383 *total = COSTS_N_INSNS (1);
1384 return false;
1385 }
1386 }
1387
1388 /* Documentation for the machine specific operand escapes:
1389
1390 'E' like s but negative.
1391 'F' like t but negative.
1392 'G' constant just the negative
1393 'R' print operand as a byte:8 address if appropriate, else fall back to
1394 'X' handling.
1395 'S' print operand as a long word
1396 'T' print operand as a word
1397 'V' find the set bit, and print its number.
1398 'W' find the clear bit, and print its number.
1399 'X' print operand as a byte
1400 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1401 If this operand isn't a register, fall back to 'R' handling.
1402 'Z' print int & 7.
1403 'c' print the opcode corresponding to rtl
1404 'e' first word of 32-bit value - if reg, then least reg. if mem
1405 then least. if const then most sig word
1406 'f' second word of 32-bit value - if reg, then biggest reg. if mem
1407 then +2. if const then least sig word
1408 'j' print operand as condition code.
1409 'k' print operand as reverse condition code.
1410 'm' convert an integer operand to a size suffix (.b, .w or .l)
1411 'o' print an integer without a leading '#'
1412 's' print as low byte of 16-bit value
1413 't' print as high byte of 16-bit value
1414 'w' print as low byte of 32-bit value
1415 'x' print as 2nd byte of 32-bit value
1416 'y' print as 3rd byte of 32-bit value
1417 'z' print as msb of 32-bit value
1418 */
1419
1420 /* Return assembly language string which identifies a comparison type. */
1421
1422 static const char *
cond_string(enum rtx_code code)1423 cond_string (enum rtx_code code)
1424 {
1425 switch (code)
1426 {
1427 case NE:
1428 return "ne";
1429 case EQ:
1430 return "eq";
1431 case GE:
1432 return "ge";
1433 case GT:
1434 return "gt";
1435 case LE:
1436 return "le";
1437 case LT:
1438 return "lt";
1439 case GEU:
1440 return "hs";
1441 case GTU:
1442 return "hi";
1443 case LEU:
1444 return "ls";
1445 case LTU:
1446 return "lo";
1447 default:
1448 gcc_unreachable ();
1449 }
1450 }
1451
1452 /* Print operand X using operand code CODE to assembly language output file
1453 FILE. */
1454
1455 static void
h8300_print_operand(FILE * file,rtx x,int code)1456 h8300_print_operand (FILE *file, rtx x, int code)
1457 {
1458 /* This is used for communication between codes V,W,Z and Y. */
1459 static int bitint;
1460
1461 switch (code)
1462 {
1463 case 'C':
1464 if (h8300_constant_length (x) == 2)
1465 fprintf (file, ":16");
1466 else
1467 fprintf (file, ":32");
1468 return;
1469 case 'E':
1470 switch (GET_CODE (x))
1471 {
1472 case REG:
1473 fprintf (file, "%sl", names_big[REGNO (x)]);
1474 break;
1475 case CONST_INT:
1476 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1477 break;
1478 default:
1479 gcc_unreachable ();
1480 }
1481 break;
1482 case 'F':
1483 switch (GET_CODE (x))
1484 {
1485 case REG:
1486 fprintf (file, "%sh", names_big[REGNO (x)]);
1487 break;
1488 case CONST_INT:
1489 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1490 break;
1491 default:
1492 gcc_unreachable ();
1493 }
1494 break;
1495 case 'G':
1496 gcc_assert (GET_CODE (x) == CONST_INT);
1497 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1498 break;
1499 case 'S':
1500 if (GET_CODE (x) == REG)
1501 fprintf (file, "%s", names_extended[REGNO (x)]);
1502 else
1503 goto def;
1504 break;
1505 case 'T':
1506 if (GET_CODE (x) == REG)
1507 fprintf (file, "%s", names_big[REGNO (x)]);
1508 else
1509 goto def;
1510 break;
1511 case 'V':
1512 bitint = (INTVAL (x) & 0xffff);
1513 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1)
1514 bitint = exact_log2 (bitint & 0xff);
1515 else
1516 bitint = exact_log2 ((bitint >> 8) & 0xff);
1517 gcc_assert (bitint >= 0);
1518 fprintf (file, "#%d", bitint);
1519 break;
1520 case 'W':
1521 bitint = ((~INTVAL (x)) & 0xffff);
1522 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1 )
1523 bitint = exact_log2 (bitint & 0xff);
1524 else
1525 bitint = (exact_log2 ((bitint >> 8) & 0xff));
1526 gcc_assert (bitint >= 0);
1527 fprintf (file, "#%d", bitint);
1528 break;
1529 case 'R':
1530 case 'X':
1531 if (GET_CODE (x) == REG)
1532 fprintf (file, "%s", byte_reg (x, 0));
1533 else
1534 goto def;
1535 break;
1536 case 'Y':
1537 gcc_assert (bitint >= 0);
1538 if (GET_CODE (x) == REG)
1539 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1540 else
1541 h8300_print_operand (file, x, 'R');
1542 bitint = -1;
1543 break;
1544 case 'Z':
1545 bitint = INTVAL (x);
1546 fprintf (file, "#%d", bitint & 7);
1547 break;
1548 case 'c':
1549 switch (GET_CODE (x))
1550 {
1551 case IOR:
1552 fprintf (file, "or");
1553 break;
1554 case XOR:
1555 fprintf (file, "xor");
1556 break;
1557 case AND:
1558 fprintf (file, "and");
1559 break;
1560 default:
1561 break;
1562 }
1563 break;
1564 case 'e':
1565 switch (GET_CODE (x))
1566 {
1567 case REG:
1568 if (TARGET_H8300)
1569 fprintf (file, "%s", names_big[REGNO (x)]);
1570 else
1571 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1572 break;
1573 case MEM:
1574 h8300_print_operand (file, x, 0);
1575 break;
1576 case CONST_INT:
1577 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1578 break;
1579 case CONST_DOUBLE:
1580 {
1581 long val;
1582 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), val);
1583 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1584 break;
1585 }
1586 default:
1587 gcc_unreachable ();
1588 break;
1589 }
1590 break;
1591 case 'f':
1592 switch (GET_CODE (x))
1593 {
1594 case REG:
1595 if (TARGET_H8300)
1596 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1597 else
1598 fprintf (file, "%s", names_big[REGNO (x)]);
1599 break;
1600 case MEM:
1601 x = adjust_address (x, HImode, 2);
1602 h8300_print_operand (file, x, 0);
1603 break;
1604 case CONST_INT:
1605 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1606 break;
1607 case CONST_DOUBLE:
1608 {
1609 long val;
1610 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), val);
1611 fprintf (file, "#%ld", (val & 0xffff));
1612 break;
1613 }
1614 default:
1615 gcc_unreachable ();
1616 }
1617 break;
1618 case 'j':
1619 fputs (cond_string (GET_CODE (x)), file);
1620 break;
1621 case 'k':
1622 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1623 break;
1624 case 'm':
1625 gcc_assert (GET_CODE (x) == CONST_INT);
1626 switch (INTVAL (x))
1627 {
1628 case 1:
1629 fputs (".b", file);
1630 break;
1631
1632 case 2:
1633 fputs (".w", file);
1634 break;
1635
1636 case 4:
1637 fputs (".l", file);
1638 break;
1639
1640 default:
1641 gcc_unreachable ();
1642 }
1643 break;
1644 case 'o':
1645 h8300_print_operand_address (file, VOIDmode, x);
1646 break;
1647 case 's':
1648 if (GET_CODE (x) == CONST_INT)
1649 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1650 else if (GET_CODE (x) == REG)
1651 fprintf (file, "%s", byte_reg (x, 0));
1652 else
1653 output_operand_lossage ("Expected register or constant integer.");
1654 break;
1655 case 't':
1656 if (GET_CODE (x) == CONST_INT)
1657 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1658 else if (GET_CODE (x) == REG)
1659 fprintf (file, "%s", byte_reg (x, 1));
1660 else
1661 output_operand_lossage ("Expected register or constant integer.");
1662 break;
1663 case 'w':
1664 if (GET_CODE (x) == CONST_INT)
1665 fprintf (file, "#%ld", INTVAL (x) & 0xff);
1666 else if (GET_CODE (x) == REG)
1667 fprintf (file, "%s",
1668 byte_reg (x, TARGET_H8300 ? 2 : 0));
1669 else
1670 output_operand_lossage ("Expected register or constant integer.");
1671 break;
1672 case 'x':
1673 if (GET_CODE (x) == CONST_INT)
1674 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1675 else if (GET_CODE (x) == REG)
1676 fprintf (file, "%s",
1677 byte_reg (x, TARGET_H8300 ? 3 : 1));
1678 else
1679 output_operand_lossage ("Expected register or constant integer.");
1680 break;
1681 case 'y':
1682 if (GET_CODE (x) == CONST_INT)
1683 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1684 else if (GET_CODE (x) == REG)
1685 fprintf (file, "%s", byte_reg (x, 0));
1686 else
1687 output_operand_lossage ("Expected register or constant integer.");
1688 break;
1689 case 'z':
1690 if (GET_CODE (x) == CONST_INT)
1691 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1692 else if (GET_CODE (x) == REG)
1693 fprintf (file, "%s", byte_reg (x, 1));
1694 else
1695 output_operand_lossage ("Expected register or constant integer.");
1696 break;
1697
1698 default:
1699 def:
1700 switch (GET_CODE (x))
1701 {
1702 case REG:
1703 switch (GET_MODE (x))
1704 {
1705 case E_QImode:
1706 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1707 fprintf (file, "%s", byte_reg (x, 0));
1708 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1709 fprintf (file, "%s", names_big[REGNO (x)]);
1710 #endif
1711 break;
1712 case E_HImode:
1713 fprintf (file, "%s", names_big[REGNO (x)]);
1714 break;
1715 case E_SImode:
1716 case E_SFmode:
1717 fprintf (file, "%s", names_extended[REGNO (x)]);
1718 break;
1719 default:
1720 gcc_unreachable ();
1721 }
1722 break;
1723
1724 case MEM:
1725 {
1726 rtx addr = XEXP (x, 0);
1727
1728 fprintf (file, "@");
1729 output_address (GET_MODE (x), addr);
1730
1731 /* Add a length suffix to constant addresses. Although this
1732 is often unnecessary, it helps to avoid ambiguity in the
1733 syntax of mova. If we wrote an insn like:
1734
1735 mova/w.l @(1,@foo.b),er0
1736
1737 then .b would be considered part of the symbol name.
1738 Adding a length after foo will avoid this. */
1739 if (CONSTANT_P (addr))
1740 switch (code)
1741 {
1742 case 'R':
1743 /* Used for mov.b and bit operations. */
1744 if (h8300_eightbit_constant_address_p (addr))
1745 {
1746 fprintf (file, ":8");
1747 break;
1748 }
1749
1750 /* FALLTHRU */
1751
1752 /* We should not get here if we are processing bit
1753 operations on H8/300 or H8/300H because 'U'
1754 constraint does not allow bit operations on the
1755 tiny area on these machines. */
1756
1757 case 'X':
1758 case 'T':
1759 case 'S':
1760 if (h8300_constant_length (addr) == 2)
1761 fprintf (file, ":16");
1762 else
1763 fprintf (file, ":32");
1764 break;
1765 default:
1766 break;
1767 }
1768 }
1769 break;
1770
1771 case CONST_INT:
1772 case SYMBOL_REF:
1773 case CONST:
1774 case LABEL_REF:
1775 fprintf (file, "#");
1776 h8300_print_operand_address (file, VOIDmode, x);
1777 break;
1778 case CONST_DOUBLE:
1779 {
1780 long val;
1781 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), val);
1782 fprintf (file, "#%ld", val);
1783 break;
1784 }
1785 default:
1786 break;
1787 }
1788 }
1789 }
1790
1791 /* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
1792
1793 static bool
h8300_print_operand_punct_valid_p(unsigned char code)1794 h8300_print_operand_punct_valid_p (unsigned char code)
1795 {
1796 return (code == '#');
1797 }
1798
1799 /* Output assembly language output for the address ADDR to FILE. */
1800
1801 static void
h8300_print_operand_address(FILE * file,machine_mode mode,rtx addr)1802 h8300_print_operand_address (FILE *file, machine_mode mode, rtx addr)
1803 {
1804 rtx index;
1805 int size;
1806
1807 switch (GET_CODE (addr))
1808 {
1809 case REG:
1810 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1811 break;
1812
1813 case PRE_DEC:
1814 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1815 break;
1816
1817 case POST_INC:
1818 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1819 break;
1820
1821 case PRE_INC:
1822 fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1823 break;
1824
1825 case POST_DEC:
1826 fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]);
1827 break;
1828
1829 case PLUS:
1830 fprintf (file, "(");
1831
1832 index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size);
1833 if (GET_CODE (index) == REG)
1834 {
1835 /* reg,foo */
1836 h8300_print_operand_address (file, mode, XEXP (addr, 1));
1837 fprintf (file, ",");
1838 switch (size)
1839 {
1840 case 0:
1841 h8300_print_operand_address (file, mode, index);
1842 break;
1843
1844 case 1:
1845 h8300_print_operand (file, index, 'X');
1846 fputs (".b", file);
1847 break;
1848
1849 case 2:
1850 h8300_print_operand (file, index, 'T');
1851 fputs (".w", file);
1852 break;
1853
1854 case 4:
1855 h8300_print_operand (file, index, 'S');
1856 fputs (".l", file);
1857 break;
1858 }
1859 /* h8300_print_operand_address (file, XEXP (addr, 0)); */
1860 }
1861 else
1862 {
1863 /* foo+k */
1864 h8300_print_operand_address (file, mode, XEXP (addr, 0));
1865 fprintf (file, "+");
1866 h8300_print_operand_address (file, mode, XEXP (addr, 1));
1867 }
1868 fprintf (file, ")");
1869 break;
1870
1871 case CONST_INT:
1872 {
1873 /* Since the H8/300 only has 16-bit pointers, negative values are also
1874 those >= 32768. This happens for example with pointer minus a
1875 constant. We don't want to turn (char *p - 2) into
1876 (char *p + 65534) because loop unrolling can build upon this
1877 (IE: char *p + 131068). */
1878 int n = INTVAL (addr);
1879 if (TARGET_H8300)
1880 n = (int) (short) n;
1881 fprintf (file, "%d", n);
1882 break;
1883 }
1884
1885 default:
1886 output_addr_const (file, addr);
1887 break;
1888 }
1889 }
1890
1891 /* Output all insn addresses and their sizes into the assembly language
1892 output file. This is helpful for debugging whether the length attributes
1893 in the md file are correct. This is not meant to be a user selectable
1894 option. */
1895
1896 void
final_prescan_insn(rtx_insn * insn,rtx * operand ATTRIBUTE_UNUSED,int num_operands ATTRIBUTE_UNUSED)1897 final_prescan_insn (rtx_insn *insn, rtx *operand ATTRIBUTE_UNUSED,
1898 int num_operands ATTRIBUTE_UNUSED)
1899 {
1900 /* This holds the last insn address. */
1901 static int last_insn_address = 0;
1902
1903 const int uid = INSN_UID (insn);
1904
1905 if (TARGET_ADDRESSES)
1906 {
1907 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1908 INSN_ADDRESSES (uid) - last_insn_address);
1909 last_insn_address = INSN_ADDRESSES (uid);
1910 }
1911 }
1912
1913 /* Prepare for an SI sized move. */
1914
1915 int
h8300_expand_movsi(rtx operands[])1916 h8300_expand_movsi (rtx operands[])
1917 {
1918 rtx src = operands[1];
1919 rtx dst = operands[0];
1920 if (!reload_in_progress && !reload_completed)
1921 {
1922 if (!register_operand (dst, GET_MODE (dst)))
1923 {
1924 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1925 emit_move_insn (tmp, src);
1926 operands[1] = tmp;
1927 }
1928 }
1929 return 0;
1930 }
1931
1932 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1933 Frame pointer elimination is automatically handled.
1934
1935 For the h8300, if frame pointer elimination is being done, we would like to
1936 convert ap and rp into sp, not fp.
1937
1938 All other eliminations are valid. */
1939
1940 static bool
h8300_can_eliminate(const int from ATTRIBUTE_UNUSED,const int to)1941 h8300_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
1942 {
1943 return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true);
1944 }
1945
1946 /* Conditionally modify register usage based on target flags. */
1947
1948 static void
h8300_conditional_register_usage(void)1949 h8300_conditional_register_usage (void)
1950 {
1951 if (!TARGET_MAC)
1952 fixed_regs[MAC_REG] = call_used_regs[MAC_REG] = 1;
1953 }
1954
1955 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1956 Define the offset between two registers, one to be eliminated, and
1957 the other its replacement, at the start of a routine. */
1958
1959 int
h8300_initial_elimination_offset(int from,int to)1960 h8300_initial_elimination_offset (int from, int to)
1961 {
1962 /* The number of bytes that the return address takes on the stack. */
1963 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
1964
1965 /* The number of bytes that the saved frame pointer takes on the stack. */
1966 int fp_size = frame_pointer_needed * UNITS_PER_WORD;
1967
1968 /* The number of bytes that the saved registers, excluding the frame
1969 pointer, take on the stack. */
1970 int saved_regs_size = 0;
1971
1972 /* The number of bytes that the locals takes on the stack. */
1973 int frame_size = round_frame_size (get_frame_size ());
1974
1975 int regno;
1976
1977 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
1978 if (WORD_REG_USED (regno))
1979 saved_regs_size += UNITS_PER_WORD;
1980
1981 /* Adjust saved_regs_size because the above loop took the frame
1982 pointer int account. */
1983 saved_regs_size -= fp_size;
1984
1985 switch (to)
1986 {
1987 case HARD_FRAME_POINTER_REGNUM:
1988 switch (from)
1989 {
1990 case ARG_POINTER_REGNUM:
1991 return pc_size + fp_size;
1992 case RETURN_ADDRESS_POINTER_REGNUM:
1993 return fp_size;
1994 case FRAME_POINTER_REGNUM:
1995 return -saved_regs_size;
1996 default:
1997 gcc_unreachable ();
1998 }
1999 break;
2000 case STACK_POINTER_REGNUM:
2001 switch (from)
2002 {
2003 case ARG_POINTER_REGNUM:
2004 return pc_size + saved_regs_size + frame_size;
2005 case RETURN_ADDRESS_POINTER_REGNUM:
2006 return saved_regs_size + frame_size;
2007 case FRAME_POINTER_REGNUM:
2008 return frame_size;
2009 default:
2010 gcc_unreachable ();
2011 }
2012 break;
2013 default:
2014 gcc_unreachable ();
2015 }
2016 gcc_unreachable ();
2017 }
2018
2019 /* Worker function for RETURN_ADDR_RTX. */
2020
2021 rtx
h8300_return_addr_rtx(int count,rtx frame)2022 h8300_return_addr_rtx (int count, rtx frame)
2023 {
2024 rtx ret;
2025
2026 if (count == 0)
2027 ret = gen_rtx_MEM (Pmode,
2028 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
2029 else if (flag_omit_frame_pointer)
2030 return (rtx) 0;
2031 else
2032 ret = gen_rtx_MEM (Pmode,
2033 memory_address (Pmode,
2034 plus_constant (Pmode, frame,
2035 UNITS_PER_WORD)));
2036 set_mem_alias_set (ret, get_frame_alias_set ());
2037 return ret;
2038 }
2039
2040 /* Update the condition code from the insn. */
2041
2042 void
notice_update_cc(rtx body,rtx_insn * insn)2043 notice_update_cc (rtx body, rtx_insn *insn)
2044 {
2045 rtx set;
2046
2047 switch (get_attr_cc (insn))
2048 {
2049 case CC_NONE:
2050 /* Insn does not affect CC at all. */
2051 break;
2052
2053 case CC_NONE_0HIT:
2054 /* Insn does not change CC, but the 0'th operand has been changed. */
2055 if (cc_status.value1 != 0
2056 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
2057 cc_status.value1 = 0;
2058 if (cc_status.value2 != 0
2059 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
2060 cc_status.value2 = 0;
2061 break;
2062
2063 case CC_SET_ZN:
2064 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
2065 The V flag is unusable. The C flag may or may not be known but
2066 that's ok because alter_cond will change tests to use EQ/NE. */
2067 CC_STATUS_INIT;
2068 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
2069 set = single_set (insn);
2070 cc_status.value1 = SET_SRC (set);
2071 if (SET_DEST (set) != cc0_rtx)
2072 cc_status.value2 = SET_DEST (set);
2073 break;
2074
2075 case CC_SET_ZNV:
2076 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
2077 The C flag may or may not be known but that's ok because
2078 alter_cond will change tests to use EQ/NE. */
2079 CC_STATUS_INIT;
2080 cc_status.flags |= CC_NO_CARRY;
2081 set = single_set (insn);
2082 cc_status.value1 = SET_SRC (set);
2083 if (SET_DEST (set) != cc0_rtx)
2084 {
2085 /* If the destination is STRICT_LOW_PART, strip off
2086 STRICT_LOW_PART. */
2087 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
2088 cc_status.value2 = XEXP (SET_DEST (set), 0);
2089 else
2090 cc_status.value2 = SET_DEST (set);
2091 }
2092 break;
2093
2094 case CC_COMPARE:
2095 /* The insn is a compare instruction. */
2096 CC_STATUS_INIT;
2097 cc_status.value1 = SET_SRC (body);
2098 break;
2099
2100 case CC_CLOBBER:
2101 /* Insn doesn't leave CC in a usable state. */
2102 CC_STATUS_INIT;
2103 break;
2104 }
2105 }
2106
2107 /* Given that X occurs in an address of the form (plus X constant),
2108 return the part of X that is expected to be a register. There are
2109 four kinds of addressing mode to recognize:
2110
2111 @(dd,Rn)
2112 @(dd,RnL.b)
2113 @(dd,Rn.w)
2114 @(dd,ERn.l)
2115
2116 If SIZE is nonnull, and the address is one of the last three forms,
2117 set *SIZE to the index multiplication factor. Set it to 0 for
2118 plain @(dd,Rn) addresses.
2119
2120 MODE is the mode of the value being accessed. It can be VOIDmode
2121 if the address is known to be valid, but its mode is unknown. */
2122
2123 static rtx
h8300_get_index(rtx x,machine_mode mode,int * size)2124 h8300_get_index (rtx x, machine_mode mode, int *size)
2125 {
2126 int dummy, factor;
2127
2128 if (size == 0)
2129 size = &dummy;
2130
2131 factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode));
2132 if (TARGET_H8300SX
2133 && factor <= 4
2134 && (mode == VOIDmode
2135 || GET_MODE_CLASS (mode) == MODE_INT
2136 || GET_MODE_CLASS (mode) == MODE_FLOAT))
2137 {
2138 if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND)
2139 {
2140 /* When accessing byte-sized values, the index can be
2141 a zero-extended QImode or HImode register. */
2142 *size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0)));
2143 return XEXP (x, 0);
2144 }
2145 else
2146 {
2147 /* We're looking for addresses of the form:
2148
2149 (mult X I)
2150 or (mult (zero_extend X) I)
2151
2152 where I is the size of the operand being accessed.
2153 The canonical form of the second expression is:
2154
2155 (and (mult (subreg X) I) J)
2156
2157 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2158 rtx index;
2159
2160 if (GET_CODE (x) == AND
2161 && GET_CODE (XEXP (x, 1)) == CONST_INT
2162 && (factor == 0
2163 || INTVAL (XEXP (x, 1)) == 0xff * factor
2164 || INTVAL (XEXP (x, 1)) == 0xffff * factor))
2165 {
2166 index = XEXP (x, 0);
2167 *size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1);
2168 }
2169 else
2170 {
2171 index = x;
2172 *size = 4;
2173 }
2174
2175 if (GET_CODE (index) == MULT
2176 && GET_CODE (XEXP (index, 1)) == CONST_INT
2177 && (factor == 0 || factor == INTVAL (XEXP (index, 1))))
2178 return XEXP (index, 0);
2179 }
2180 }
2181 *size = 0;
2182 return x;
2183 }
2184
2185 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
2186
2187 On the H8/300, the predecrement and postincrement address depend thus
2188 (the amount of decrement or increment being the length of the operand). */
2189
2190 static bool
h8300_mode_dependent_address_p(const_rtx addr,addr_space_t as ATTRIBUTE_UNUSED)2191 h8300_mode_dependent_address_p (const_rtx addr,
2192 addr_space_t as ATTRIBUTE_UNUSED)
2193 {
2194 if (GET_CODE (addr) == PLUS
2195 && h8300_get_index (XEXP (addr, 0), VOIDmode, 0) != XEXP (addr, 0))
2196 return true;
2197
2198 return false;
2199 }
2200
2201 static const h8300_length_table addb_length_table =
2202 {
2203 /* #xx Rs @aa @Rs @xx */
2204 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2205 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2206 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2207 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2208 };
2209
2210 static const h8300_length_table addw_length_table =
2211 {
2212 /* #xx Rs @aa @Rs @xx */
2213 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2214 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2215 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2216 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2217 };
2218
2219 static const h8300_length_table addl_length_table =
2220 {
2221 /* #xx Rs @aa @Rs @xx */
2222 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2223 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2224 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2225 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2226 };
2227
2228 #define logicb_length_table addb_length_table
2229 #define logicw_length_table addw_length_table
2230
2231 static const h8300_length_table logicl_length_table =
2232 {
2233 /* #xx Rs @aa @Rs @xx */
2234 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2235 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2236 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2237 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2238 };
2239
2240 static const h8300_length_table movb_length_table =
2241 {
2242 /* #xx Rs @aa @Rs @xx */
2243 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2244 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2245 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2246 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2247 };
2248
2249 #define movw_length_table movb_length_table
2250
2251 static const h8300_length_table movl_length_table =
2252 {
2253 /* #xx Rs @aa @Rs @xx */
2254 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2255 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2256 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2257 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2258 };
2259
2260 /* Return the size of the given address or displacement constant. */
2261
2262 static unsigned int
h8300_constant_length(rtx constant)2263 h8300_constant_length (rtx constant)
2264 {
2265 /* Check for (@d:16,Reg). */
2266 if (GET_CODE (constant) == CONST_INT
2267 && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff))
2268 return 2;
2269
2270 /* Check for (@d:16,Reg) in cases where the displacement is
2271 an absolute address. */
2272 if (Pmode == HImode || h8300_tiny_constant_address_p (constant))
2273 return 2;
2274
2275 return 4;
2276 }
2277
2278 /* Return the size of a displacement field in address ADDR, which should
2279 have the form (plus X constant). SIZE is the number of bytes being
2280 accessed. */
2281
2282 static unsigned int
h8300_displacement_length(rtx addr,int size)2283 h8300_displacement_length (rtx addr, int size)
2284 {
2285 rtx offset;
2286
2287 offset = XEXP (addr, 1);
2288
2289 /* Check for @(d:2,Reg). */
2290 if (register_operand (XEXP (addr, 0), VOIDmode)
2291 && GET_CODE (offset) == CONST_INT
2292 && (INTVAL (offset) == size
2293 || INTVAL (offset) == size * 2
2294 || INTVAL (offset) == size * 3))
2295 return 0;
2296
2297 return h8300_constant_length (offset);
2298 }
2299
2300 /* Store the class of operand OP in *OPCLASS and return the length of any
2301 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
2302 can be null if only the length is needed. */
2303
2304 static unsigned int
h8300_classify_operand(rtx op,int size,enum h8300_operand_class * opclass)2305 h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass)
2306 {
2307 enum h8300_operand_class dummy;
2308
2309 if (opclass == 0)
2310 opclass = &dummy;
2311
2312 if (CONSTANT_P (op))
2313 {
2314 *opclass = H8OP_IMMEDIATE;
2315
2316 /* Byte-sized immediates are stored in the opcode fields. */
2317 if (size == 1)
2318 return 0;
2319
2320 /* If this is a 32-bit instruction, see whether the constant
2321 will fit into a 16-bit immediate field. */
2322 if (TARGET_H8300SX
2323 && size == 4
2324 && GET_CODE (op) == CONST_INT
2325 && IN_RANGE (INTVAL (op), 0, 0xffff))
2326 return 2;
2327
2328 return size;
2329 }
2330 else if (GET_CODE (op) == MEM)
2331 {
2332 op = XEXP (op, 0);
2333 if (CONSTANT_P (op))
2334 {
2335 *opclass = H8OP_MEM_ABSOLUTE;
2336 return h8300_constant_length (op);
2337 }
2338 else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1)))
2339 {
2340 *opclass = H8OP_MEM_COMPLEX;
2341 return h8300_displacement_length (op, size);
2342 }
2343 else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC)
2344 {
2345 *opclass = H8OP_MEM_COMPLEX;
2346 return 0;
2347 }
2348 else if (register_operand (op, VOIDmode))
2349 {
2350 *opclass = H8OP_MEM_BASE;
2351 return 0;
2352 }
2353 }
2354 gcc_assert (register_operand (op, VOIDmode));
2355 *opclass = H8OP_REGISTER;
2356 return 0;
2357 }
2358
2359 /* Return the length of the instruction described by TABLE given that
2360 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2361 and OP2 must be an h8300_src_operand. */
2362
2363 static unsigned int
h8300_length_from_table(rtx op1,rtx op2,const h8300_length_table * table)2364 h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table)
2365 {
2366 enum h8300_operand_class op1_class, op2_class;
2367 unsigned int size, immediate_length;
2368
2369 size = GET_MODE_SIZE (GET_MODE (op1));
2370 immediate_length = (h8300_classify_operand (op1, size, &op1_class)
2371 + h8300_classify_operand (op2, size, &op2_class));
2372 return immediate_length + (*table)[op1_class - 1][op2_class];
2373 }
2374
2375 /* Return the length of a unary instruction such as neg or not given that
2376 its operand is OP. */
2377
2378 unsigned int
h8300_unary_length(rtx op)2379 h8300_unary_length (rtx op)
2380 {
2381 enum h8300_operand_class opclass;
2382 unsigned int size, operand_length;
2383
2384 size = GET_MODE_SIZE (GET_MODE (op));
2385 operand_length = h8300_classify_operand (op, size, &opclass);
2386 switch (opclass)
2387 {
2388 case H8OP_REGISTER:
2389 return 2;
2390
2391 case H8OP_MEM_BASE:
2392 return (size == 4 ? 6 : 4);
2393
2394 case H8OP_MEM_ABSOLUTE:
2395 return operand_length + (size == 4 ? 6 : 4);
2396
2397 case H8OP_MEM_COMPLEX:
2398 return operand_length + 6;
2399
2400 default:
2401 gcc_unreachable ();
2402 }
2403 }
2404
2405 /* Likewise short immediate instructions such as add.w #xx:3,OP. */
2406
2407 static unsigned int
h8300_short_immediate_length(rtx op)2408 h8300_short_immediate_length (rtx op)
2409 {
2410 enum h8300_operand_class opclass;
2411 unsigned int size, operand_length;
2412
2413 size = GET_MODE_SIZE (GET_MODE (op));
2414 operand_length = h8300_classify_operand (op, size, &opclass);
2415
2416 switch (opclass)
2417 {
2418 case H8OP_REGISTER:
2419 return 2;
2420
2421 case H8OP_MEM_BASE:
2422 case H8OP_MEM_ABSOLUTE:
2423 case H8OP_MEM_COMPLEX:
2424 return 4 + operand_length;
2425
2426 default:
2427 gcc_unreachable ();
2428 }
2429 }
2430
2431 /* Likewise bitfield load and store instructions. */
2432
2433 static unsigned int
h8300_bitfield_length(rtx op,rtx op2)2434 h8300_bitfield_length (rtx op, rtx op2)
2435 {
2436 enum h8300_operand_class opclass;
2437 unsigned int size, operand_length;
2438
2439 if (GET_CODE (op) == REG)
2440 op = op2;
2441 gcc_assert (GET_CODE (op) != REG);
2442
2443 size = GET_MODE_SIZE (GET_MODE (op));
2444 operand_length = h8300_classify_operand (op, size, &opclass);
2445
2446 switch (opclass)
2447 {
2448 case H8OP_MEM_BASE:
2449 case H8OP_MEM_ABSOLUTE:
2450 case H8OP_MEM_COMPLEX:
2451 return 4 + operand_length;
2452
2453 default:
2454 gcc_unreachable ();
2455 }
2456 }
2457
2458 /* Calculate the length of general binary instruction INSN using TABLE. */
2459
2460 static unsigned int
h8300_binary_length(rtx_insn * insn,const h8300_length_table * table)2461 h8300_binary_length (rtx_insn *insn, const h8300_length_table *table)
2462 {
2463 rtx set;
2464
2465 set = single_set (insn);
2466 gcc_assert (set);
2467
2468 if (BINARY_P (SET_SRC (set)))
2469 return h8300_length_from_table (XEXP (SET_SRC (set), 0),
2470 XEXP (SET_SRC (set), 1), table);
2471 else
2472 {
2473 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY);
2474 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0),
2475 XEXP (XEXP (SET_SRC (set), 1), 1),
2476 table);
2477 }
2478 }
2479
2480 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2481 memory reference and either (1) it has the form @(d:16,Rn) or
2482 (2) its address has the code given by INC_CODE. */
2483
2484 static bool
h8300_short_move_mem_p(rtx op,enum rtx_code inc_code)2485 h8300_short_move_mem_p (rtx op, enum rtx_code inc_code)
2486 {
2487 rtx addr;
2488 unsigned int size;
2489
2490 if (GET_CODE (op) != MEM)
2491 return false;
2492
2493 addr = XEXP (op, 0);
2494 size = GET_MODE_SIZE (GET_MODE (op));
2495 if (size != 1 && size != 2)
2496 return false;
2497
2498 return (GET_CODE (addr) == inc_code
2499 || (GET_CODE (addr) == PLUS
2500 && GET_CODE (XEXP (addr, 0)) == REG
2501 && h8300_displacement_length (addr, size) == 2));
2502 }
2503
2504 /* Calculate the length of move instruction INSN using the given length
2505 table. Although the tables are correct for most cases, there is some
2506 irregularity in the length of mov.b and mov.w. The following forms:
2507
2508 mov @ERs+, Rd
2509 mov @(d:16,ERs), Rd
2510 mov Rs, @-ERd
2511 mov Rs, @(d:16,ERd)
2512
2513 are two bytes shorter than most other "mov Rs, @complex" or
2514 "mov @complex,Rd" combinations. */
2515
2516 static unsigned int
h8300_move_length(rtx * operands,const h8300_length_table * table)2517 h8300_move_length (rtx *operands, const h8300_length_table *table)
2518 {
2519 unsigned int size;
2520
2521 size = h8300_length_from_table (operands[0], operands[1], table);
2522 if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC))
2523 size -= 2;
2524 if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC))
2525 size -= 2;
2526 return size;
2527 }
2528
2529 /* Return the length of a mova instruction with the given operands.
2530 DEST is the register destination, SRC is the source address and
2531 OFFSET is the 16-bit or 32-bit displacement. */
2532
2533 static unsigned int
h8300_mova_length(rtx dest,rtx src,rtx offset)2534 h8300_mova_length (rtx dest, rtx src, rtx offset)
2535 {
2536 unsigned int size;
2537
2538 size = (2
2539 + h8300_constant_length (offset)
2540 + h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0));
2541 if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest))
2542 size += 2;
2543 return size;
2544 }
2545
2546 /* Compute the length of INSN based on its length_table attribute.
2547 OPERANDS is the array of its operands. */
2548
2549 unsigned int
h8300_insn_length_from_table(rtx_insn * insn,rtx * operands)2550 h8300_insn_length_from_table (rtx_insn *insn, rtx * operands)
2551 {
2552 switch (get_attr_length_table (insn))
2553 {
2554 case LENGTH_TABLE_NONE:
2555 gcc_unreachable ();
2556
2557 case LENGTH_TABLE_ADD:
2558 if (GET_MODE (operands[0]) == QImode)
2559 return h8300_binary_length (insn, &addb_length_table);
2560 else if (GET_MODE (operands[0]) == HImode)
2561 return h8300_binary_length (insn, &addw_length_table);
2562 else if (GET_MODE (operands[0]) == SImode)
2563 return h8300_binary_length (insn, &addl_length_table);
2564 gcc_unreachable ();
2565
2566 case LENGTH_TABLE_LOGICB:
2567 return h8300_binary_length (insn, &logicb_length_table);
2568
2569 case LENGTH_TABLE_MOVB:
2570 return h8300_move_length (operands, &movb_length_table);
2571
2572 case LENGTH_TABLE_MOVW:
2573 return h8300_move_length (operands, &movw_length_table);
2574
2575 case LENGTH_TABLE_MOVL:
2576 return h8300_move_length (operands, &movl_length_table);
2577
2578 case LENGTH_TABLE_MOVA:
2579 return h8300_mova_length (operands[0], operands[1], operands[2]);
2580
2581 case LENGTH_TABLE_MOVA_ZERO:
2582 return h8300_mova_length (operands[0], operands[1], const0_rtx);
2583
2584 case LENGTH_TABLE_UNARY:
2585 return h8300_unary_length (operands[0]);
2586
2587 case LENGTH_TABLE_MOV_IMM4:
2588 return 2 + h8300_classify_operand (operands[0], 0, 0);
2589
2590 case LENGTH_TABLE_SHORT_IMMEDIATE:
2591 return h8300_short_immediate_length (operands[0]);
2592
2593 case LENGTH_TABLE_BITFIELD:
2594 return h8300_bitfield_length (operands[0], operands[1]);
2595
2596 case LENGTH_TABLE_BITBRANCH:
2597 return h8300_bitfield_length (operands[1], operands[2]) - 2;
2598
2599 default:
2600 gcc_unreachable ();
2601 }
2602 }
2603
2604 /* Return true if LHS and RHS are memory references that can be mapped
2605 to the same h8sx assembly operand. LHS appears as the destination of
2606 an instruction and RHS appears as a source.
2607
2608 Three cases are allowed:
2609
2610 - RHS is @+Rn or @-Rn, LHS is @Rn
2611 - RHS is @Rn, LHS is @Rn+ or @Rn-
2612 - RHS and LHS have the same address and neither has side effects. */
2613
2614 bool
h8sx_mergeable_memrefs_p(rtx lhs,rtx rhs)2615 h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs)
2616 {
2617 if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM)
2618 {
2619 rhs = XEXP (rhs, 0);
2620 lhs = XEXP (lhs, 0);
2621
2622 if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC)
2623 return rtx_equal_p (XEXP (rhs, 0), lhs);
2624
2625 if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC)
2626 return rtx_equal_p (rhs, XEXP (lhs, 0));
2627
2628 if (rtx_equal_p (rhs, lhs))
2629 return true;
2630 }
2631 return false;
2632 }
2633
2634 /* Return true if OPERANDS[1] can be mapped to the same assembly
2635 operand as OPERANDS[0]. */
2636
2637 bool
h8300_operands_match_p(rtx * operands)2638 h8300_operands_match_p (rtx *operands)
2639 {
2640 if (register_operand (operands[0], VOIDmode)
2641 && register_operand (operands[1], VOIDmode))
2642 return true;
2643
2644 if (h8sx_mergeable_memrefs_p (operands[0], operands[1]))
2645 return true;
2646
2647 return false;
2648 }
2649
2650 /* Return the length of mov instruction. */
2651
2652 unsigned int
compute_mov_length(rtx * operands)2653 compute_mov_length (rtx *operands)
2654 {
2655 /* If the mov instruction involves a memory operand, we compute the
2656 length, assuming the largest addressing mode is used, and then
2657 adjust later in the function. Otherwise, we compute and return
2658 the exact length in one step. */
2659 machine_mode mode = GET_MODE (operands[0]);
2660 rtx dest = operands[0];
2661 rtx src = operands[1];
2662 rtx addr;
2663
2664 if (GET_CODE (src) == MEM)
2665 addr = XEXP (src, 0);
2666 else if (GET_CODE (dest) == MEM)
2667 addr = XEXP (dest, 0);
2668 else
2669 addr = NULL_RTX;
2670
2671 if (TARGET_H8300)
2672 {
2673 unsigned int base_length;
2674
2675 switch (mode)
2676 {
2677 case E_QImode:
2678 if (addr == NULL_RTX)
2679 return 2;
2680
2681 /* The eightbit addressing is available only in QImode, so
2682 go ahead and take care of it. */
2683 if (h8300_eightbit_constant_address_p (addr))
2684 return 2;
2685
2686 base_length = 4;
2687 break;
2688
2689 case E_HImode:
2690 if (addr == NULL_RTX)
2691 {
2692 if (REG_P (src))
2693 return 2;
2694
2695 if (src == const0_rtx)
2696 return 2;
2697
2698 return 4;
2699 }
2700
2701 base_length = 4;
2702 break;
2703
2704 case E_SImode:
2705 if (addr == NULL_RTX)
2706 {
2707 if (REG_P (src))
2708 return 4;
2709
2710 if (GET_CODE (src) == CONST_INT)
2711 {
2712 if (src == const0_rtx)
2713 return 4;
2714
2715 if ((INTVAL (src) & 0xffff) == 0)
2716 return 6;
2717
2718 if ((INTVAL (src) & 0xffff) == 0)
2719 return 6;
2720
2721 if ((INTVAL (src) & 0xffff)
2722 == ((INTVAL (src) >> 16) & 0xffff))
2723 return 6;
2724 }
2725 return 8;
2726 }
2727
2728 base_length = 8;
2729 break;
2730
2731 case E_SFmode:
2732 if (addr == NULL_RTX)
2733 {
2734 if (REG_P (src))
2735 return 4;
2736
2737 if (satisfies_constraint_G (src))
2738 return 4;
2739
2740 return 8;
2741 }
2742
2743 base_length = 8;
2744 break;
2745
2746 default:
2747 gcc_unreachable ();
2748 }
2749
2750 /* Adjust the length based on the addressing mode used.
2751 Specifically, we subtract the difference between the actual
2752 length and the longest one, which is @(d:16,Rs). For SImode
2753 and SFmode, we double the adjustment because two mov.w are
2754 used to do the job. */
2755
2756 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2757 if (GET_CODE (addr) == PRE_DEC
2758 || GET_CODE (addr) == POST_INC)
2759 {
2760 if (mode == QImode || mode == HImode)
2761 return base_length - 2;
2762 else
2763 /* In SImode and SFmode, we use two mov.w instructions, so
2764 double the adjustment. */
2765 return base_length - 4;
2766 }
2767
2768 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2769 in SImode and SFmode, the second mov.w involves an address
2770 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2771 only 2 bytes. */
2772 if (GET_CODE (addr) == REG)
2773 return base_length - 2;
2774
2775 return base_length;
2776 }
2777 else
2778 {
2779 unsigned int base_length;
2780
2781 switch (mode)
2782 {
2783 case E_QImode:
2784 if (addr == NULL_RTX)
2785 return 2;
2786
2787 /* The eightbit addressing is available only in QImode, so
2788 go ahead and take care of it. */
2789 if (h8300_eightbit_constant_address_p (addr))
2790 return 2;
2791
2792 base_length = 8;
2793 break;
2794
2795 case E_HImode:
2796 if (addr == NULL_RTX)
2797 {
2798 if (REG_P (src))
2799 return 2;
2800
2801 if (src == const0_rtx)
2802 return 2;
2803
2804 return 4;
2805 }
2806
2807 base_length = 8;
2808 break;
2809
2810 case E_SImode:
2811 if (addr == NULL_RTX)
2812 {
2813 if (REG_P (src))
2814 {
2815 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
2816 return 4;
2817 else
2818 return 2;
2819 }
2820
2821 if (GET_CODE (src) == CONST_INT)
2822 {
2823 int val = INTVAL (src);
2824
2825 if (val == 0)
2826 return 2;
2827
2828 if (val == (val & 0x00ff) || val == (val & 0xff00))
2829 return 4;
2830
2831 switch (val & 0xffffffff)
2832 {
2833 case 0xffffffff:
2834 case 0xfffffffe:
2835 case 0xfffffffc:
2836 case 0x0000ffff:
2837 case 0x0000fffe:
2838 case 0xffff0000:
2839 case 0xfffe0000:
2840 case 0x00010000:
2841 case 0x00020000:
2842 return 4;
2843 }
2844 }
2845 return 6;
2846 }
2847
2848 base_length = 10;
2849 break;
2850
2851 case E_SFmode:
2852 if (addr == NULL_RTX)
2853 {
2854 if (REG_P (src))
2855 return 2;
2856
2857 if (satisfies_constraint_G (src))
2858 return 2;
2859
2860 return 6;
2861 }
2862
2863 base_length = 10;
2864 break;
2865
2866 default:
2867 gcc_unreachable ();
2868 }
2869
2870 /* Adjust the length based on the addressing mode used.
2871 Specifically, we subtract the difference between the actual
2872 length and the longest one, which is @(d:24,ERs). */
2873
2874 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
2875 if (GET_CODE (addr) == PRE_DEC
2876 || GET_CODE (addr) == POST_INC)
2877 return base_length - 6;
2878
2879 /* @ERs and @ERd are 6 bytes shorter than the longest. */
2880 if (GET_CODE (addr) == REG)
2881 return base_length - 6;
2882
2883 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
2884 longest. */
2885 if (GET_CODE (addr) == PLUS
2886 && GET_CODE (XEXP (addr, 0)) == REG
2887 && GET_CODE (XEXP (addr, 1)) == CONST_INT
2888 && INTVAL (XEXP (addr, 1)) > -32768
2889 && INTVAL (XEXP (addr, 1)) < 32767)
2890 return base_length - 4;
2891
2892 /* @aa:16 is 4 bytes shorter than the longest. */
2893 if (h8300_tiny_constant_address_p (addr))
2894 return base_length - 4;
2895
2896 /* @aa:24 is 2 bytes shorter than the longest. */
2897 if (CONSTANT_P (addr))
2898 return base_length - 2;
2899
2900 return base_length;
2901 }
2902 }
2903
2904 /* Output an addition insn. */
2905
2906 const char *
output_plussi(rtx * operands)2907 output_plussi (rtx *operands)
2908 {
2909 machine_mode mode = GET_MODE (operands[0]);
2910
2911 gcc_assert (mode == SImode);
2912
2913 if (TARGET_H8300)
2914 {
2915 if (GET_CODE (operands[2]) == REG)
2916 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2917
2918 if (GET_CODE (operands[2]) == CONST_INT)
2919 {
2920 HOST_WIDE_INT n = INTVAL (operands[2]);
2921
2922 if ((n & 0xffffff) == 0)
2923 return "add\t%z2,%z0";
2924 if ((n & 0xffff) == 0)
2925 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
2926 if ((n & 0xff) == 0)
2927 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2928 }
2929
2930 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2931 }
2932 else
2933 {
2934 if (GET_CODE (operands[2]) == CONST_INT
2935 && register_operand (operands[1], VOIDmode))
2936 {
2937 HOST_WIDE_INT intval = INTVAL (operands[2]);
2938
2939 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
2940 return "add.l\t%S2,%S0";
2941 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
2942 return "sub.l\t%G2,%S0";
2943
2944 /* See if we can finish with 2 bytes. */
2945
2946 switch ((unsigned int) intval & 0xffffffff)
2947 {
2948 case 0x00000001:
2949 case 0x00000002:
2950 case 0x00000004:
2951 return "adds\t%2,%S0";
2952
2953 case 0xffffffff:
2954 case 0xfffffffe:
2955 case 0xfffffffc:
2956 return "subs\t%G2,%S0";
2957
2958 case 0x00010000:
2959 case 0x00020000:
2960 operands[2] = GEN_INT (intval >> 16);
2961 return "inc.w\t%2,%e0";
2962
2963 case 0xffff0000:
2964 case 0xfffe0000:
2965 operands[2] = GEN_INT (intval >> 16);
2966 return "dec.w\t%G2,%e0";
2967 }
2968
2969 /* See if we can finish with 4 bytes. */
2970 if ((intval & 0xffff) == 0)
2971 {
2972 operands[2] = GEN_INT (intval >> 16);
2973 return "add.w\t%2,%e0";
2974 }
2975 }
2976
2977 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
2978 {
2979 operands[2] = GEN_INT (-INTVAL (operands[2]));
2980 return "sub.l\t%S2,%S0";
2981 }
2982 return "add.l\t%S2,%S0";
2983 }
2984 }
2985
2986 /* ??? It would be much easier to add the h8sx stuff if a single function
2987 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
2988 /* Compute the length of an addition insn. */
2989
2990 unsigned int
compute_plussi_length(rtx * operands)2991 compute_plussi_length (rtx *operands)
2992 {
2993 machine_mode mode = GET_MODE (operands[0]);
2994
2995 gcc_assert (mode == SImode);
2996
2997 if (TARGET_H8300)
2998 {
2999 if (GET_CODE (operands[2]) == REG)
3000 return 6;
3001
3002 if (GET_CODE (operands[2]) == CONST_INT)
3003 {
3004 HOST_WIDE_INT n = INTVAL (operands[2]);
3005
3006 if ((n & 0xffffff) == 0)
3007 return 2;
3008 if ((n & 0xffff) == 0)
3009 return 4;
3010 if ((n & 0xff) == 0)
3011 return 6;
3012 }
3013
3014 return 8;
3015 }
3016 else
3017 {
3018 if (GET_CODE (operands[2]) == CONST_INT
3019 && register_operand (operands[1], VOIDmode))
3020 {
3021 HOST_WIDE_INT intval = INTVAL (operands[2]);
3022
3023 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3024 return 2;
3025 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3026 return 2;
3027
3028 /* See if we can finish with 2 bytes. */
3029
3030 switch ((unsigned int) intval & 0xffffffff)
3031 {
3032 case 0x00000001:
3033 case 0x00000002:
3034 case 0x00000004:
3035 return 2;
3036
3037 case 0xffffffff:
3038 case 0xfffffffe:
3039 case 0xfffffffc:
3040 return 2;
3041
3042 case 0x00010000:
3043 case 0x00020000:
3044 return 2;
3045
3046 case 0xffff0000:
3047 case 0xfffe0000:
3048 return 2;
3049 }
3050
3051 /* See if we can finish with 4 bytes. */
3052 if ((intval & 0xffff) == 0)
3053 return 4;
3054 }
3055
3056 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3057 return h8300_length_from_table (operands[0],
3058 GEN_INT (-INTVAL (operands[2])),
3059 &addl_length_table);
3060 else
3061 return h8300_length_from_table (operands[0], operands[2],
3062 &addl_length_table);
3063 return 6;
3064 }
3065 }
3066
3067 /* Compute which flag bits are valid after an addition insn. */
3068
3069 enum attr_cc
compute_plussi_cc(rtx * operands)3070 compute_plussi_cc (rtx *operands)
3071 {
3072 machine_mode mode = GET_MODE (operands[0]);
3073
3074 gcc_assert (mode == SImode);
3075
3076 if (TARGET_H8300)
3077 {
3078 return CC_CLOBBER;
3079 }
3080 else
3081 {
3082 if (GET_CODE (operands[2]) == CONST_INT
3083 && register_operand (operands[1], VOIDmode))
3084 {
3085 HOST_WIDE_INT intval = INTVAL (operands[2]);
3086
3087 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3088 return CC_SET_ZN;
3089 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3090 return CC_SET_ZN;
3091
3092 /* See if we can finish with 2 bytes. */
3093
3094 switch ((unsigned int) intval & 0xffffffff)
3095 {
3096 case 0x00000001:
3097 case 0x00000002:
3098 case 0x00000004:
3099 return CC_NONE_0HIT;
3100
3101 case 0xffffffff:
3102 case 0xfffffffe:
3103 case 0xfffffffc:
3104 return CC_NONE_0HIT;
3105
3106 case 0x00010000:
3107 case 0x00020000:
3108 return CC_CLOBBER;
3109
3110 case 0xffff0000:
3111 case 0xfffe0000:
3112 return CC_CLOBBER;
3113 }
3114
3115 /* See if we can finish with 4 bytes. */
3116 if ((intval & 0xffff) == 0)
3117 return CC_CLOBBER;
3118 }
3119
3120 return CC_SET_ZN;
3121 }
3122 }
3123
3124 /* Output a logical insn. */
3125
3126 const char *
output_logical_op(machine_mode mode,rtx * operands)3127 output_logical_op (machine_mode mode, rtx *operands)
3128 {
3129 /* Figure out the logical op that we need to perform. */
3130 enum rtx_code code = GET_CODE (operands[3]);
3131 /* Pretend that every byte is affected if both operands are registers. */
3132 const unsigned HOST_WIDE_INT intval =
3133 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3134 /* Always use the full instruction if the
3135 first operand is in memory. It is better
3136 to use define_splits to generate the shorter
3137 sequence where valid. */
3138 && register_operand (operands[1], VOIDmode)
3139 ? INTVAL (operands[2]) : 0x55555555);
3140 /* The determinant of the algorithm. If we perform an AND, 0
3141 affects a bit. Otherwise, 1 affects a bit. */
3142 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3143 /* Break up DET into pieces. */
3144 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3145 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3146 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3147 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
3148 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3149 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3150 int lower_half_easy_p = 0;
3151 int upper_half_easy_p = 0;
3152 /* The name of an insn. */
3153 const char *opname;
3154 char insn_buf[100];
3155
3156 switch (code)
3157 {
3158 case AND:
3159 opname = "and";
3160 break;
3161 case IOR:
3162 opname = "or";
3163 break;
3164 case XOR:
3165 opname = "xor";
3166 break;
3167 default:
3168 gcc_unreachable ();
3169 }
3170
3171 switch (mode)
3172 {
3173 case E_HImode:
3174 /* First, see if we can finish with one insn. */
3175 if ((TARGET_H8300H || TARGET_H8300S)
3176 && b0 != 0
3177 && b1 != 0)
3178 {
3179 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
3180 output_asm_insn (insn_buf, operands);
3181 }
3182 else
3183 {
3184 /* Take care of the lower byte. */
3185 if (b0 != 0)
3186 {
3187 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
3188 output_asm_insn (insn_buf, operands);
3189 }
3190 /* Take care of the upper byte. */
3191 if (b1 != 0)
3192 {
3193 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
3194 output_asm_insn (insn_buf, operands);
3195 }
3196 }
3197 break;
3198 case E_SImode:
3199 if (TARGET_H8300H || TARGET_H8300S)
3200 {
3201 /* Determine if the lower half can be taken care of in no more
3202 than two bytes. */
3203 lower_half_easy_p = (b0 == 0
3204 || b1 == 0
3205 || (code != IOR && w0 == 0xffff));
3206
3207 /* Determine if the upper half can be taken care of in no more
3208 than two bytes. */
3209 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3210 || (code == AND && w1 == 0xff00));
3211 }
3212
3213 /* Check if doing everything with one insn is no worse than
3214 using multiple insns. */
3215 if ((TARGET_H8300H || TARGET_H8300S)
3216 && w0 != 0 && w1 != 0
3217 && !(lower_half_easy_p && upper_half_easy_p)
3218 && !(code == IOR && w1 == 0xffff
3219 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3220 {
3221 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
3222 output_asm_insn (insn_buf, operands);
3223 }
3224 else
3225 {
3226 /* Take care of the lower and upper words individually. For
3227 each word, we try different methods in the order of
3228
3229 1) the special insn (in case of AND or XOR),
3230 2) the word-wise insn, and
3231 3) The byte-wise insn. */
3232 if (w0 == 0xffff
3233 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3234 output_asm_insn ((code == AND)
3235 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
3236 operands);
3237 else if ((TARGET_H8300H || TARGET_H8300S)
3238 && (b0 != 0)
3239 && (b1 != 0))
3240 {
3241 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
3242 output_asm_insn (insn_buf, operands);
3243 }
3244 else
3245 {
3246 if (b0 != 0)
3247 {
3248 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
3249 output_asm_insn (insn_buf, operands);
3250 }
3251 if (b1 != 0)
3252 {
3253 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
3254 output_asm_insn (insn_buf, operands);
3255 }
3256 }
3257
3258 if ((w1 == 0xffff)
3259 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3260 output_asm_insn ((code == AND)
3261 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
3262 operands);
3263 else if ((TARGET_H8300H || TARGET_H8300S)
3264 && code == IOR
3265 && w1 == 0xffff
3266 && (w0 & 0x8000) != 0)
3267 {
3268 output_asm_insn ("exts.l\t%S0", operands);
3269 }
3270 else if ((TARGET_H8300H || TARGET_H8300S)
3271 && code == AND
3272 && w1 == 0xff00)
3273 {
3274 output_asm_insn ("extu.w\t%e0", operands);
3275 }
3276 else if (TARGET_H8300H || TARGET_H8300S)
3277 {
3278 if (w1 != 0)
3279 {
3280 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
3281 output_asm_insn (insn_buf, operands);
3282 }
3283 }
3284 else
3285 {
3286 if (b2 != 0)
3287 {
3288 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
3289 output_asm_insn (insn_buf, operands);
3290 }
3291 if (b3 != 0)
3292 {
3293 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
3294 output_asm_insn (insn_buf, operands);
3295 }
3296 }
3297 }
3298 break;
3299 default:
3300 gcc_unreachable ();
3301 }
3302 return "";
3303 }
3304
3305 /* Compute the length of a logical insn. */
3306
3307 unsigned int
compute_logical_op_length(machine_mode mode,rtx * operands)3308 compute_logical_op_length (machine_mode mode, rtx *operands)
3309 {
3310 /* Figure out the logical op that we need to perform. */
3311 enum rtx_code code = GET_CODE (operands[3]);
3312 /* Pretend that every byte is affected if both operands are registers. */
3313 const unsigned HOST_WIDE_INT intval =
3314 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3315 /* Always use the full instruction if the
3316 first operand is in memory. It is better
3317 to use define_splits to generate the shorter
3318 sequence where valid. */
3319 && register_operand (operands[1], VOIDmode)
3320 ? INTVAL (operands[2]) : 0x55555555);
3321 /* The determinant of the algorithm. If we perform an AND, 0
3322 affects a bit. Otherwise, 1 affects a bit. */
3323 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3324 /* Break up DET into pieces. */
3325 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3326 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3327 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3328 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
3329 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3330 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3331 int lower_half_easy_p = 0;
3332 int upper_half_easy_p = 0;
3333 /* Insn length. */
3334 unsigned int length = 0;
3335
3336 switch (mode)
3337 {
3338 case E_HImode:
3339 /* First, see if we can finish with one insn. */
3340 if ((TARGET_H8300H || TARGET_H8300S)
3341 && b0 != 0
3342 && b1 != 0)
3343 {
3344 length = h8300_length_from_table (operands[1], operands[2],
3345 &logicw_length_table);
3346 }
3347 else
3348 {
3349 /* Take care of the lower byte. */
3350 if (b0 != 0)
3351 length += 2;
3352
3353 /* Take care of the upper byte. */
3354 if (b1 != 0)
3355 length += 2;
3356 }
3357 break;
3358 case E_SImode:
3359 if (TARGET_H8300H || TARGET_H8300S)
3360 {
3361 /* Determine if the lower half can be taken care of in no more
3362 than two bytes. */
3363 lower_half_easy_p = (b0 == 0
3364 || b1 == 0
3365 || (code != IOR && w0 == 0xffff));
3366
3367 /* Determine if the upper half can be taken care of in no more
3368 than two bytes. */
3369 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3370 || (code == AND && w1 == 0xff00));
3371 }
3372
3373 /* Check if doing everything with one insn is no worse than
3374 using multiple insns. */
3375 if ((TARGET_H8300H || TARGET_H8300S)
3376 && w0 != 0 && w1 != 0
3377 && !(lower_half_easy_p && upper_half_easy_p)
3378 && !(code == IOR && w1 == 0xffff
3379 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3380 {
3381 length = h8300_length_from_table (operands[1], operands[2],
3382 &logicl_length_table);
3383 }
3384 else
3385 {
3386 /* Take care of the lower and upper words individually. For
3387 each word, we try different methods in the order of
3388
3389 1) the special insn (in case of AND or XOR),
3390 2) the word-wise insn, and
3391 3) The byte-wise insn. */
3392 if (w0 == 0xffff
3393 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3394 {
3395 length += 2;
3396 }
3397 else if ((TARGET_H8300H || TARGET_H8300S)
3398 && (b0 != 0)
3399 && (b1 != 0))
3400 {
3401 length += 4;
3402 }
3403 else
3404 {
3405 if (b0 != 0)
3406 length += 2;
3407
3408 if (b1 != 0)
3409 length += 2;
3410 }
3411
3412 if (w1 == 0xffff
3413 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3414 {
3415 length += 2;
3416 }
3417 else if ((TARGET_H8300H || TARGET_H8300S)
3418 && code == IOR
3419 && w1 == 0xffff
3420 && (w0 & 0x8000) != 0)
3421 {
3422 length += 2;
3423 }
3424 else if ((TARGET_H8300H || TARGET_H8300S)
3425 && code == AND
3426 && w1 == 0xff00)
3427 {
3428 length += 2;
3429 }
3430 else if (TARGET_H8300H || TARGET_H8300S)
3431 {
3432 if (w1 != 0)
3433 length += 4;
3434 }
3435 else
3436 {
3437 if (b2 != 0)
3438 length += 2;
3439
3440 if (b3 != 0)
3441 length += 2;
3442 }
3443 }
3444 break;
3445 default:
3446 gcc_unreachable ();
3447 }
3448 return length;
3449 }
3450
3451 /* Compute which flag bits are valid after a logical insn. */
3452
3453 enum attr_cc
compute_logical_op_cc(machine_mode mode,rtx * operands)3454 compute_logical_op_cc (machine_mode mode, rtx *operands)
3455 {
3456 /* Figure out the logical op that we need to perform. */
3457 enum rtx_code code = GET_CODE (operands[3]);
3458 /* Pretend that every byte is affected if both operands are registers. */
3459 const unsigned HOST_WIDE_INT intval =
3460 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3461 /* Always use the full instruction if the
3462 first operand is in memory. It is better
3463 to use define_splits to generate the shorter
3464 sequence where valid. */
3465 && register_operand (operands[1], VOIDmode)
3466 ? INTVAL (operands[2]) : 0x55555555);
3467 /* The determinant of the algorithm. If we perform an AND, 0
3468 affects a bit. Otherwise, 1 affects a bit. */
3469 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3470 /* Break up DET into pieces. */
3471 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3472 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3473 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3474 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3475 int lower_half_easy_p = 0;
3476 int upper_half_easy_p = 0;
3477 /* Condition code. */
3478 enum attr_cc cc = CC_CLOBBER;
3479
3480 switch (mode)
3481 {
3482 case E_HImode:
3483 /* First, see if we can finish with one insn. */
3484 if ((TARGET_H8300H || TARGET_H8300S)
3485 && b0 != 0
3486 && b1 != 0)
3487 {
3488 cc = CC_SET_ZNV;
3489 }
3490 break;
3491 case E_SImode:
3492 if (TARGET_H8300H || TARGET_H8300S)
3493 {
3494 /* Determine if the lower half can be taken care of in no more
3495 than two bytes. */
3496 lower_half_easy_p = (b0 == 0
3497 || b1 == 0
3498 || (code != IOR && w0 == 0xffff));
3499
3500 /* Determine if the upper half can be taken care of in no more
3501 than two bytes. */
3502 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3503 || (code == AND && w1 == 0xff00));
3504 }
3505
3506 /* Check if doing everything with one insn is no worse than
3507 using multiple insns. */
3508 if ((TARGET_H8300H || TARGET_H8300S)
3509 && w0 != 0 && w1 != 0
3510 && !(lower_half_easy_p && upper_half_easy_p)
3511 && !(code == IOR && w1 == 0xffff
3512 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3513 {
3514 cc = CC_SET_ZNV;
3515 }
3516 else
3517 {
3518 if ((TARGET_H8300H || TARGET_H8300S)
3519 && code == IOR
3520 && w1 == 0xffff
3521 && (w0 & 0x8000) != 0)
3522 {
3523 cc = CC_SET_ZNV;
3524 }
3525 }
3526 break;
3527 default:
3528 gcc_unreachable ();
3529 }
3530 return cc;
3531 }
3532
3533 /* Expand a conditional branch. */
3534
3535 void
h8300_expand_branch(rtx operands[])3536 h8300_expand_branch (rtx operands[])
3537 {
3538 enum rtx_code code = GET_CODE (operands[0]);
3539 rtx op0 = operands[1];
3540 rtx op1 = operands[2];
3541 rtx label = operands[3];
3542 rtx tmp;
3543
3544 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3545 emit_insn (gen_rtx_SET (cc0_rtx, tmp));
3546
3547 tmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
3548 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
3549 gen_rtx_LABEL_REF (VOIDmode, label),
3550 pc_rtx);
3551 emit_jump_insn (gen_rtx_SET (pc_rtx, tmp));
3552 }
3553
3554
3555 /* Expand a conditional store. */
3556
3557 void
h8300_expand_store(rtx operands[])3558 h8300_expand_store (rtx operands[])
3559 {
3560 rtx dest = operands[0];
3561 enum rtx_code code = GET_CODE (operands[1]);
3562 rtx op0 = operands[2];
3563 rtx op1 = operands[3];
3564 rtx tmp;
3565
3566 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3567 emit_insn (gen_rtx_SET (cc0_rtx, tmp));
3568
3569 tmp = gen_rtx_fmt_ee (code, GET_MODE (dest), cc0_rtx, const0_rtx);
3570 emit_insn (gen_rtx_SET (dest, tmp));
3571 }
3572
3573 /* Shifts.
3574
3575 We devote a fair bit of code to getting efficient shifts since we
3576 can only shift one bit at a time on the H8/300 and H8/300H and only
3577 one or two bits at a time on the H8S.
3578
3579 All shift code falls into one of the following ways of
3580 implementation:
3581
3582 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3583 when a straight line shift is about the same size or smaller than
3584 a loop.
3585
3586 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3587 off the bits we don't need. This is used when only a few of the
3588 bits in the original value will survive in the shifted value.
3589
3590 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3591 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3592 shifts can be added if the shift count is slightly more than 8 or
3593 16. This case also includes other oddballs that are not worth
3594 explaining here.
3595
3596 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
3597
3598 For each shift count, we try to use code that has no trade-off
3599 between code size and speed whenever possible.
3600
3601 If the trade-off is unavoidable, we try to be reasonable.
3602 Specifically, the fastest version is one instruction longer than
3603 the shortest version, we take the fastest version. We also provide
3604 the use a way to switch back to the shortest version with -Os.
3605
3606 For the details of the shift algorithms for various shift counts,
3607 refer to shift_alg_[qhs]i. */
3608
3609 /* Classify a shift with the given mode and code. OP is the shift amount. */
3610
3611 enum h8sx_shift_type
h8sx_classify_shift(machine_mode mode,enum rtx_code code,rtx op)3612 h8sx_classify_shift (machine_mode mode, enum rtx_code code, rtx op)
3613 {
3614 if (!TARGET_H8300SX)
3615 return H8SX_SHIFT_NONE;
3616
3617 switch (code)
3618 {
3619 case ASHIFT:
3620 case LSHIFTRT:
3621 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3622 if (GET_CODE (op) != CONST_INT)
3623 return H8SX_SHIFT_BINARY;
3624
3625 /* Reject out-of-range shift amounts. */
3626 if (INTVAL (op) <= 0 || INTVAL (op) >= GET_MODE_BITSIZE (mode))
3627 return H8SX_SHIFT_NONE;
3628
3629 /* Power-of-2 shifts are effectively unary operations. */
3630 if (exact_log2 (INTVAL (op)) >= 0)
3631 return H8SX_SHIFT_UNARY;
3632
3633 return H8SX_SHIFT_BINARY;
3634
3635 case ASHIFTRT:
3636 if (op == const1_rtx || op == const2_rtx)
3637 return H8SX_SHIFT_UNARY;
3638 return H8SX_SHIFT_NONE;
3639
3640 case ROTATE:
3641 if (GET_CODE (op) == CONST_INT
3642 && (INTVAL (op) == 1
3643 || INTVAL (op) == 2
3644 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2
3645 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 1))
3646 return H8SX_SHIFT_UNARY;
3647 return H8SX_SHIFT_NONE;
3648
3649 default:
3650 return H8SX_SHIFT_NONE;
3651 }
3652 }
3653
3654 /* Return the asm template for a single h8sx shift instruction.
3655 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3656 is the source and OPERANDS[3] is the shift. SUFFIX is the
3657 size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand
3658 prefix for the destination operand. */
3659
3660 const char *
output_h8sx_shift(rtx * operands,int suffix,int optype)3661 output_h8sx_shift (rtx *operands, int suffix, int optype)
3662 {
3663 static char buffer[16];
3664 const char *stem;
3665
3666 switch (GET_CODE (operands[3]))
3667 {
3668 case ASHIFT:
3669 stem = "shll";
3670 break;
3671
3672 case ASHIFTRT:
3673 stem = "shar";
3674 break;
3675
3676 case LSHIFTRT:
3677 stem = "shlr";
3678 break;
3679
3680 case ROTATE:
3681 stem = "rotl";
3682 if (INTVAL (operands[2]) > 2)
3683 {
3684 /* This is really a right rotate. */
3685 operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[0]))
3686 - INTVAL (operands[2]));
3687 stem = "rotr";
3688 }
3689 break;
3690
3691 default:
3692 gcc_unreachable ();
3693 }
3694 if (operands[2] == const1_rtx)
3695 sprintf (buffer, "%s.%c\t%%%c0", stem, suffix, optype);
3696 else
3697 sprintf (buffer, "%s.%c\t%%X2,%%%c0", stem, suffix, optype);
3698 return buffer;
3699 }
3700
3701 /* Emit code to do shifts. */
3702
3703 bool
expand_a_shift(machine_mode mode,enum rtx_code code,rtx operands[])3704 expand_a_shift (machine_mode mode, enum rtx_code code, rtx operands[])
3705 {
3706 switch (h8sx_classify_shift (mode, code, operands[2]))
3707 {
3708 case H8SX_SHIFT_BINARY:
3709 operands[1] = force_reg (mode, operands[1]);
3710 return false;
3711
3712 case H8SX_SHIFT_UNARY:
3713 return false;
3714
3715 case H8SX_SHIFT_NONE:
3716 break;
3717 }
3718
3719 emit_move_insn (copy_rtx (operands[0]), operands[1]);
3720
3721 /* Need a loop to get all the bits we want - we generate the
3722 code at emit time, but need to allocate a scratch reg now. */
3723
3724 emit_insn (gen_rtx_PARALLEL
3725 (VOIDmode,
3726 gen_rtvec (2,
3727 gen_rtx_SET (copy_rtx (operands[0]),
3728 gen_rtx_fmt_ee (code, mode,
3729 copy_rtx (operands[0]), operands[2])),
3730 gen_rtx_CLOBBER (VOIDmode,
3731 gen_rtx_SCRATCH (QImode)))));
3732 return true;
3733 }
3734
3735 /* Symbols of the various modes which can be used as indices. */
3736
3737 enum shift_mode
3738 {
3739 QIshift, HIshift, SIshift
3740 };
3741
3742 /* For single bit shift insns, record assembler and what bits of the
3743 condition code are valid afterwards (represented as various CC_FOO
3744 bits, 0 means CC isn't left in a usable state). */
3745
3746 struct shift_insn
3747 {
3748 const char *const assembler;
3749 const enum attr_cc cc_valid;
3750 };
3751
3752 /* Assembler instruction shift table.
3753
3754 These tables are used to look up the basic shifts.
3755 They are indexed by cpu, shift_type, and mode. */
3756
3757 static const struct shift_insn shift_one[2][3][3] =
3758 {
3759 /* H8/300 */
3760 {
3761 /* SHIFT_ASHIFT */
3762 {
3763 { "shll\t%X0", CC_SET_ZNV },
3764 { "add.w\t%T0,%T0", CC_SET_ZN },
3765 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
3766 },
3767 /* SHIFT_LSHIFTRT */
3768 {
3769 { "shlr\t%X0", CC_SET_ZNV },
3770 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3771 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
3772 },
3773 /* SHIFT_ASHIFTRT */
3774 {
3775 { "shar\t%X0", CC_SET_ZNV },
3776 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3777 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
3778 }
3779 },
3780 /* H8/300H */
3781 {
3782 /* SHIFT_ASHIFT */
3783 {
3784 { "shll.b\t%X0", CC_SET_ZNV },
3785 { "shll.w\t%T0", CC_SET_ZNV },
3786 { "shll.l\t%S0", CC_SET_ZNV }
3787 },
3788 /* SHIFT_LSHIFTRT */
3789 {
3790 { "shlr.b\t%X0", CC_SET_ZNV },
3791 { "shlr.w\t%T0", CC_SET_ZNV },
3792 { "shlr.l\t%S0", CC_SET_ZNV }
3793 },
3794 /* SHIFT_ASHIFTRT */
3795 {
3796 { "shar.b\t%X0", CC_SET_ZNV },
3797 { "shar.w\t%T0", CC_SET_ZNV },
3798 { "shar.l\t%S0", CC_SET_ZNV }
3799 }
3800 }
3801 };
3802
3803 static const struct shift_insn shift_two[3][3] =
3804 {
3805 /* SHIFT_ASHIFT */
3806 {
3807 { "shll.b\t#2,%X0", CC_SET_ZNV },
3808 { "shll.w\t#2,%T0", CC_SET_ZNV },
3809 { "shll.l\t#2,%S0", CC_SET_ZNV }
3810 },
3811 /* SHIFT_LSHIFTRT */
3812 {
3813 { "shlr.b\t#2,%X0", CC_SET_ZNV },
3814 { "shlr.w\t#2,%T0", CC_SET_ZNV },
3815 { "shlr.l\t#2,%S0", CC_SET_ZNV }
3816 },
3817 /* SHIFT_ASHIFTRT */
3818 {
3819 { "shar.b\t#2,%X0", CC_SET_ZNV },
3820 { "shar.w\t#2,%T0", CC_SET_ZNV },
3821 { "shar.l\t#2,%S0", CC_SET_ZNV }
3822 }
3823 };
3824
3825 /* Rotates are organized by which shift they'll be used in implementing.
3826 There's no need to record whether the cc is valid afterwards because
3827 it is the AND insn that will decide this. */
3828
3829 static const char *const rotate_one[2][3][3] =
3830 {
3831 /* H8/300 */
3832 {
3833 /* SHIFT_ASHIFT */
3834 {
3835 "rotr\t%X0",
3836 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
3837 0
3838 },
3839 /* SHIFT_LSHIFTRT */
3840 {
3841 "rotl\t%X0",
3842 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3843 0
3844 },
3845 /* SHIFT_ASHIFTRT */
3846 {
3847 "rotl\t%X0",
3848 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3849 0
3850 }
3851 },
3852 /* H8/300H */
3853 {
3854 /* SHIFT_ASHIFT */
3855 {
3856 "rotr.b\t%X0",
3857 "rotr.w\t%T0",
3858 "rotr.l\t%S0"
3859 },
3860 /* SHIFT_LSHIFTRT */
3861 {
3862 "rotl.b\t%X0",
3863 "rotl.w\t%T0",
3864 "rotl.l\t%S0"
3865 },
3866 /* SHIFT_ASHIFTRT */
3867 {
3868 "rotl.b\t%X0",
3869 "rotl.w\t%T0",
3870 "rotl.l\t%S0"
3871 }
3872 }
3873 };
3874
3875 static const char *const rotate_two[3][3] =
3876 {
3877 /* SHIFT_ASHIFT */
3878 {
3879 "rotr.b\t#2,%X0",
3880 "rotr.w\t#2,%T0",
3881 "rotr.l\t#2,%S0"
3882 },
3883 /* SHIFT_LSHIFTRT */
3884 {
3885 "rotl.b\t#2,%X0",
3886 "rotl.w\t#2,%T0",
3887 "rotl.l\t#2,%S0"
3888 },
3889 /* SHIFT_ASHIFTRT */
3890 {
3891 "rotl.b\t#2,%X0",
3892 "rotl.w\t#2,%T0",
3893 "rotl.l\t#2,%S0"
3894 }
3895 };
3896
3897 struct shift_info {
3898 /* Shift algorithm. */
3899 enum shift_alg alg;
3900
3901 /* The number of bits to be shifted by shift1 and shift2. Valid
3902 when ALG is SHIFT_SPECIAL. */
3903 unsigned int remainder;
3904
3905 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
3906 const char *special;
3907
3908 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
3909 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
3910 const char *shift1;
3911
3912 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
3913 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
3914 const char *shift2;
3915
3916 /* CC status for SHIFT_INLINE. */
3917 enum attr_cc cc_inline;
3918
3919 /* CC status for SHIFT_SPECIAL. */
3920 enum attr_cc cc_special;
3921 };
3922
3923 static void get_shift_alg (enum shift_type,
3924 enum shift_mode, unsigned int,
3925 struct shift_info *);
3926
3927 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
3928 best algorithm for doing the shift. The assembler code is stored
3929 in the pointers in INFO. We achieve the maximum efficiency in most
3930 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
3931 SImode in particular have a lot of room to optimize.
3932
3933 We first determine the strategy of the shift algorithm by a table
3934 lookup. If that tells us to use a hand crafted assembly code, we
3935 go into the big switch statement to find what that is. Otherwise,
3936 we resort to a generic way, such as inlining. In either case, the
3937 result is returned through INFO. */
3938
3939 static void
get_shift_alg(enum shift_type shift_type,enum shift_mode shift_mode,unsigned int count,struct shift_info * info)3940 get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
3941 unsigned int count, struct shift_info *info)
3942 {
3943 enum h8_cpu cpu;
3944
3945 /* Find the target CPU. */
3946 if (TARGET_H8300)
3947 cpu = H8_300;
3948 else if (TARGET_H8300S)
3949 cpu = H8_S;
3950 else
3951 cpu = H8_300H;
3952
3953 /* Find the shift algorithm. */
3954 info->alg = SHIFT_LOOP;
3955 switch (shift_mode)
3956 {
3957 case QIshift:
3958 if (count < GET_MODE_BITSIZE (QImode))
3959 info->alg = shift_alg_qi[cpu][shift_type][count];
3960 break;
3961
3962 case HIshift:
3963 if (count < GET_MODE_BITSIZE (HImode))
3964 info->alg = shift_alg_hi[cpu][shift_type][count];
3965 break;
3966
3967 case SIshift:
3968 if (count < GET_MODE_BITSIZE (SImode))
3969 info->alg = shift_alg_si[cpu][shift_type][count];
3970 break;
3971
3972 default:
3973 gcc_unreachable ();
3974 }
3975
3976 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
3977 switch (info->alg)
3978 {
3979 case SHIFT_INLINE:
3980 info->remainder = count;
3981 /* Fall through. */
3982
3983 case SHIFT_LOOP:
3984 /* It is up to the caller to know that looping clobbers cc. */
3985 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
3986 info->shift2 = shift_two[shift_type][shift_mode].assembler;
3987 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
3988 goto end;
3989
3990 case SHIFT_ROT_AND:
3991 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
3992 info->shift2 = rotate_two[shift_type][shift_mode];
3993 info->cc_inline = CC_CLOBBER;
3994 goto end;
3995
3996 case SHIFT_SPECIAL:
3997 /* REMAINDER is 0 for most cases, so initialize it to 0. */
3998 info->remainder = 0;
3999 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4000 info->shift2 = shift_two[shift_type][shift_mode].assembler;
4001 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
4002 info->cc_special = CC_CLOBBER;
4003 break;
4004 }
4005
4006 /* Here we only deal with SHIFT_SPECIAL. */
4007 switch (shift_mode)
4008 {
4009 case QIshift:
4010 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4011 through the entire value. */
4012 gcc_assert (shift_type == SHIFT_ASHIFTRT && count == 7);
4013 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
4014 goto end;
4015
4016 case HIshift:
4017 if (count == 7)
4018 {
4019 switch (shift_type)
4020 {
4021 case SHIFT_ASHIFT:
4022 if (TARGET_H8300)
4023 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4024 else
4025 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
4026 goto end;
4027 case SHIFT_LSHIFTRT:
4028 if (TARGET_H8300)
4029 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4030 else
4031 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
4032 goto end;
4033 case SHIFT_ASHIFTRT:
4034 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
4035 goto end;
4036 }
4037 }
4038 else if ((count >= 8 && count <= 13)
4039 || (TARGET_H8300S && count == 14))
4040 {
4041 info->remainder = count - 8;
4042
4043 switch (shift_type)
4044 {
4045 case SHIFT_ASHIFT:
4046 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
4047 goto end;
4048 case SHIFT_LSHIFTRT:
4049 if (TARGET_H8300)
4050 {
4051 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4052 info->shift1 = "shlr.b\t%s0";
4053 info->cc_inline = CC_SET_ZNV;
4054 }
4055 else
4056 {
4057 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
4058 info->cc_special = CC_SET_ZNV;
4059 }
4060 goto end;
4061 case SHIFT_ASHIFTRT:
4062 if (TARGET_H8300)
4063 {
4064 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4065 info->shift1 = "shar.b\t%s0";
4066 }
4067 else
4068 {
4069 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
4070 info->cc_special = CC_SET_ZNV;
4071 }
4072 goto end;
4073 }
4074 }
4075 else if (count == 14)
4076 {
4077 switch (shift_type)
4078 {
4079 case SHIFT_ASHIFT:
4080 if (TARGET_H8300)
4081 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4082 goto end;
4083 case SHIFT_LSHIFTRT:
4084 if (TARGET_H8300)
4085 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4086 goto end;
4087 case SHIFT_ASHIFTRT:
4088 if (TARGET_H8300)
4089 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4090 else if (TARGET_H8300H)
4091 {
4092 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4093 info->cc_special = CC_SET_ZNV;
4094 }
4095 else /* TARGET_H8300S */
4096 gcc_unreachable ();
4097 goto end;
4098 }
4099 }
4100 else if (count == 15)
4101 {
4102 switch (shift_type)
4103 {
4104 case SHIFT_ASHIFT:
4105 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4106 goto end;
4107 case SHIFT_LSHIFTRT:
4108 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4109 goto end;
4110 case SHIFT_ASHIFTRT:
4111 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4112 goto end;
4113 }
4114 }
4115 gcc_unreachable ();
4116
4117 case SIshift:
4118 if (TARGET_H8300 && count >= 8 && count <= 9)
4119 {
4120 info->remainder = count - 8;
4121
4122 switch (shift_type)
4123 {
4124 case SHIFT_ASHIFT:
4125 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
4126 goto end;
4127 case SHIFT_LSHIFTRT:
4128 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
4129 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
4130 goto end;
4131 case SHIFT_ASHIFTRT:
4132 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
4133 goto end;
4134 }
4135 }
4136 else if (count == 8 && !TARGET_H8300)
4137 {
4138 switch (shift_type)
4139 {
4140 case SHIFT_ASHIFT:
4141 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
4142 goto end;
4143 case SHIFT_LSHIFTRT:
4144 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
4145 goto end;
4146 case SHIFT_ASHIFTRT:
4147 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
4148 goto end;
4149 }
4150 }
4151 else if (count == 15 && TARGET_H8300)
4152 {
4153 switch (shift_type)
4154 {
4155 case SHIFT_ASHIFT:
4156 gcc_unreachable ();
4157 case SHIFT_LSHIFTRT:
4158 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
4159 goto end;
4160 case SHIFT_ASHIFTRT:
4161 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4162 goto end;
4163 }
4164 }
4165 else if (count == 15 && !TARGET_H8300)
4166 {
4167 switch (shift_type)
4168 {
4169 case SHIFT_ASHIFT:
4170 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
4171 info->cc_special = CC_SET_ZNV;
4172 goto end;
4173 case SHIFT_LSHIFTRT:
4174 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
4175 info->cc_special = CC_SET_ZNV;
4176 goto end;
4177 case SHIFT_ASHIFTRT:
4178 gcc_unreachable ();
4179 }
4180 }
4181 else if ((TARGET_H8300 && count >= 16 && count <= 20)
4182 || (TARGET_H8300H && count >= 16 && count <= 19)
4183 || (TARGET_H8300S && count >= 16 && count <= 21))
4184 {
4185 info->remainder = count - 16;
4186
4187 switch (shift_type)
4188 {
4189 case SHIFT_ASHIFT:
4190 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4191 if (TARGET_H8300)
4192 info->shift1 = "add.w\t%e0,%e0";
4193 goto end;
4194 case SHIFT_LSHIFTRT:
4195 if (TARGET_H8300)
4196 {
4197 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4198 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
4199 }
4200 else
4201 {
4202 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
4203 info->cc_special = CC_SET_ZNV;
4204 }
4205 goto end;
4206 case SHIFT_ASHIFTRT:
4207 if (TARGET_H8300)
4208 {
4209 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4210 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
4211 }
4212 else
4213 {
4214 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
4215 info->cc_special = CC_SET_ZNV;
4216 }
4217 goto end;
4218 }
4219 }
4220 else if (TARGET_H8300 && count >= 24 && count <= 28)
4221 {
4222 info->remainder = count - 24;
4223
4224 switch (shift_type)
4225 {
4226 case SHIFT_ASHIFT:
4227 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4228 info->shift1 = "shll.b\t%z0";
4229 info->cc_inline = CC_SET_ZNV;
4230 goto end;
4231 case SHIFT_LSHIFTRT:
4232 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4233 info->shift1 = "shlr.b\t%w0";
4234 info->cc_inline = CC_SET_ZNV;
4235 goto end;
4236 case SHIFT_ASHIFTRT:
4237 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4238 info->shift1 = "shar.b\t%w0";
4239 info->cc_inline = CC_SET_ZNV;
4240 goto end;
4241 }
4242 }
4243 else if ((TARGET_H8300H && count == 24)
4244 || (TARGET_H8300S && count >= 24 && count <= 25))
4245 {
4246 info->remainder = count - 24;
4247
4248 switch (shift_type)
4249 {
4250 case SHIFT_ASHIFT:
4251 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4252 goto end;
4253 case SHIFT_LSHIFTRT:
4254 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
4255 info->cc_special = CC_SET_ZNV;
4256 goto end;
4257 case SHIFT_ASHIFTRT:
4258 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
4259 info->cc_special = CC_SET_ZNV;
4260 goto end;
4261 }
4262 }
4263 else if (!TARGET_H8300 && count == 28)
4264 {
4265 switch (shift_type)
4266 {
4267 case SHIFT_ASHIFT:
4268 if (TARGET_H8300H)
4269 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4270 else
4271 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4272 goto end;
4273 case SHIFT_LSHIFTRT:
4274 if (TARGET_H8300H)
4275 {
4276 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4277 info->cc_special = CC_SET_ZNV;
4278 }
4279 else
4280 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4281 goto end;
4282 case SHIFT_ASHIFTRT:
4283 gcc_unreachable ();
4284 }
4285 }
4286 else if (!TARGET_H8300 && count == 29)
4287 {
4288 switch (shift_type)
4289 {
4290 case SHIFT_ASHIFT:
4291 if (TARGET_H8300H)
4292 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4293 else
4294 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4295 goto end;
4296 case SHIFT_LSHIFTRT:
4297 if (TARGET_H8300H)
4298 {
4299 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4300 info->cc_special = CC_SET_ZNV;
4301 }
4302 else
4303 {
4304 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4305 info->cc_special = CC_SET_ZNV;
4306 }
4307 goto end;
4308 case SHIFT_ASHIFTRT:
4309 gcc_unreachable ();
4310 }
4311 }
4312 else if (!TARGET_H8300 && count == 30)
4313 {
4314 switch (shift_type)
4315 {
4316 case SHIFT_ASHIFT:
4317 if (TARGET_H8300H)
4318 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4319 else
4320 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4321 goto end;
4322 case SHIFT_LSHIFTRT:
4323 if (TARGET_H8300H)
4324 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4325 else
4326 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4327 goto end;
4328 case SHIFT_ASHIFTRT:
4329 gcc_unreachable ();
4330 }
4331 }
4332 else if (count == 31)
4333 {
4334 if (TARGET_H8300)
4335 {
4336 switch (shift_type)
4337 {
4338 case SHIFT_ASHIFT:
4339 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4340 goto end;
4341 case SHIFT_LSHIFTRT:
4342 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4343 goto end;
4344 case SHIFT_ASHIFTRT:
4345 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4346 goto end;
4347 }
4348 }
4349 else
4350 {
4351 switch (shift_type)
4352 {
4353 case SHIFT_ASHIFT:
4354 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
4355 info->cc_special = CC_SET_ZNV;
4356 goto end;
4357 case SHIFT_LSHIFTRT:
4358 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
4359 info->cc_special = CC_SET_ZNV;
4360 goto end;
4361 case SHIFT_ASHIFTRT:
4362 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
4363 info->cc_special = CC_SET_ZNV;
4364 goto end;
4365 }
4366 }
4367 }
4368 gcc_unreachable ();
4369
4370 default:
4371 gcc_unreachable ();
4372 }
4373
4374 end:
4375 if (!TARGET_H8300S)
4376 info->shift2 = NULL;
4377 }
4378
4379 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4380 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4381
4382 int
h8300_shift_needs_scratch_p(int count,machine_mode mode)4383 h8300_shift_needs_scratch_p (int count, machine_mode mode)
4384 {
4385 enum h8_cpu cpu;
4386 int a, lr, ar;
4387
4388 if (GET_MODE_BITSIZE (mode) <= count)
4389 return 1;
4390
4391 /* Find out the target CPU. */
4392 if (TARGET_H8300)
4393 cpu = H8_300;
4394 else if (TARGET_H8300S)
4395 cpu = H8_S;
4396 else
4397 cpu = H8_300H;
4398
4399 /* Find the shift algorithm. */
4400 switch (mode)
4401 {
4402 case E_QImode:
4403 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
4404 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
4405 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
4406 break;
4407
4408 case E_HImode:
4409 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
4410 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
4411 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
4412 break;
4413
4414 case E_SImode:
4415 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
4416 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
4417 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
4418 break;
4419
4420 default:
4421 gcc_unreachable ();
4422 }
4423
4424 /* On H8/300H, count == 8 uses a scratch register. */
4425 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
4426 || (TARGET_H8300H && mode == SImode && count == 8));
4427 }
4428
4429 /* Output the assembler code for doing shifts. */
4430
4431 const char *
output_a_shift(rtx * operands)4432 output_a_shift (rtx *operands)
4433 {
4434 static int loopend_lab;
4435 rtx shift = operands[3];
4436 machine_mode mode = GET_MODE (shift);
4437 enum rtx_code code = GET_CODE (shift);
4438 enum shift_type shift_type;
4439 enum shift_mode shift_mode;
4440 struct shift_info info;
4441 int n;
4442
4443 loopend_lab++;
4444
4445 switch (mode)
4446 {
4447 case E_QImode:
4448 shift_mode = QIshift;
4449 break;
4450 case E_HImode:
4451 shift_mode = HIshift;
4452 break;
4453 case E_SImode:
4454 shift_mode = SIshift;
4455 break;
4456 default:
4457 gcc_unreachable ();
4458 }
4459
4460 switch (code)
4461 {
4462 case ASHIFTRT:
4463 shift_type = SHIFT_ASHIFTRT;
4464 break;
4465 case LSHIFTRT:
4466 shift_type = SHIFT_LSHIFTRT;
4467 break;
4468 case ASHIFT:
4469 shift_type = SHIFT_ASHIFT;
4470 break;
4471 default:
4472 gcc_unreachable ();
4473 }
4474
4475 /* This case must be taken care of by one of the two splitters
4476 that convert a variable shift into a loop. */
4477 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4478
4479 n = INTVAL (operands[2]);
4480
4481 /* If the count is negative, make it 0. */
4482 if (n < 0)
4483 n = 0;
4484 /* If the count is too big, truncate it.
4485 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4486 do the intuitive thing. */
4487 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4488 n = GET_MODE_BITSIZE (mode);
4489
4490 get_shift_alg (shift_type, shift_mode, n, &info);
4491
4492 switch (info.alg)
4493 {
4494 case SHIFT_SPECIAL:
4495 output_asm_insn (info.special, operands);
4496 /* Fall through. */
4497
4498 case SHIFT_INLINE:
4499 n = info.remainder;
4500
4501 /* Emit two bit shifts first. */
4502 if (info.shift2 != NULL)
4503 {
4504 for (; n > 1; n -= 2)
4505 output_asm_insn (info.shift2, operands);
4506 }
4507
4508 /* Now emit one bit shifts for any residual. */
4509 for (; n > 0; n--)
4510 output_asm_insn (info.shift1, operands);
4511 return "";
4512
4513 case SHIFT_ROT_AND:
4514 {
4515 int m = GET_MODE_BITSIZE (mode) - n;
4516 const int mask = (shift_type == SHIFT_ASHIFT
4517 ? ((1 << m) - 1) << n
4518 : (1 << m) - 1);
4519 char insn_buf[200];
4520
4521 /* Not all possibilities of rotate are supported. They shouldn't
4522 be generated, but let's watch for 'em. */
4523 gcc_assert (info.shift1);
4524
4525 /* Emit two bit rotates first. */
4526 if (info.shift2 != NULL)
4527 {
4528 for (; m > 1; m -= 2)
4529 output_asm_insn (info.shift2, operands);
4530 }
4531
4532 /* Now single bit rotates for any residual. */
4533 for (; m > 0; m--)
4534 output_asm_insn (info.shift1, operands);
4535
4536 /* Now mask off the high bits. */
4537 switch (mode)
4538 {
4539 case E_QImode:
4540 sprintf (insn_buf, "and\t#%d,%%X0", mask);
4541 break;
4542
4543 case E_HImode:
4544 gcc_assert (TARGET_H8300H || TARGET_H8300S);
4545 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
4546 break;
4547
4548 default:
4549 gcc_unreachable ();
4550 }
4551
4552 output_asm_insn (insn_buf, operands);
4553 return "";
4554 }
4555
4556 case SHIFT_LOOP:
4557 /* A loop to shift by a "large" constant value.
4558 If we have shift-by-2 insns, use them. */
4559 if (info.shift2 != NULL)
4560 {
4561 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
4562 names_big[REGNO (operands[4])]);
4563 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4564 output_asm_insn (info.shift2, operands);
4565 output_asm_insn ("add #0xff,%X4", operands);
4566 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4567 if (n % 2)
4568 output_asm_insn (info.shift1, operands);
4569 }
4570 else
4571 {
4572 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
4573 names_big[REGNO (operands[4])]);
4574 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4575 output_asm_insn (info.shift1, operands);
4576 output_asm_insn ("add #0xff,%X4", operands);
4577 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4578 }
4579 return "";
4580
4581 default:
4582 gcc_unreachable ();
4583 }
4584 }
4585
4586 /* Count the number of assembly instructions in a string TEMPL. */
4587
4588 static unsigned int
h8300_asm_insn_count(const char * templ)4589 h8300_asm_insn_count (const char *templ)
4590 {
4591 unsigned int count = 1;
4592
4593 for (; *templ; templ++)
4594 if (*templ == '\n')
4595 count++;
4596
4597 return count;
4598 }
4599
4600 /* Compute the length of a shift insn. */
4601
4602 unsigned int
compute_a_shift_length(rtx insn ATTRIBUTE_UNUSED,rtx * operands)4603 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
4604 {
4605 rtx shift = operands[3];
4606 machine_mode mode = GET_MODE (shift);
4607 enum rtx_code code = GET_CODE (shift);
4608 enum shift_type shift_type;
4609 enum shift_mode shift_mode;
4610 struct shift_info info;
4611 unsigned int wlength = 0;
4612
4613 switch (mode)
4614 {
4615 case E_QImode:
4616 shift_mode = QIshift;
4617 break;
4618 case E_HImode:
4619 shift_mode = HIshift;
4620 break;
4621 case E_SImode:
4622 shift_mode = SIshift;
4623 break;
4624 default:
4625 gcc_unreachable ();
4626 }
4627
4628 switch (code)
4629 {
4630 case ASHIFTRT:
4631 shift_type = SHIFT_ASHIFTRT;
4632 break;
4633 case LSHIFTRT:
4634 shift_type = SHIFT_LSHIFTRT;
4635 break;
4636 case ASHIFT:
4637 shift_type = SHIFT_ASHIFT;
4638 break;
4639 default:
4640 gcc_unreachable ();
4641 }
4642
4643 if (GET_CODE (operands[2]) != CONST_INT)
4644 {
4645 /* Get the assembler code to do one shift. */
4646 get_shift_alg (shift_type, shift_mode, 1, &info);
4647
4648 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
4649 }
4650 else
4651 {
4652 int n = INTVAL (operands[2]);
4653
4654 /* If the count is negative, make it 0. */
4655 if (n < 0)
4656 n = 0;
4657 /* If the count is too big, truncate it.
4658 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4659 do the intuitive thing. */
4660 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4661 n = GET_MODE_BITSIZE (mode);
4662
4663 get_shift_alg (shift_type, shift_mode, n, &info);
4664
4665 switch (info.alg)
4666 {
4667 case SHIFT_SPECIAL:
4668 wlength += h8300_asm_insn_count (info.special);
4669
4670 /* Every assembly instruction used in SHIFT_SPECIAL case
4671 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4672 see xor.l, we just pretend that xor.l counts as two insns
4673 so that the insn length will be computed correctly. */
4674 if (strstr (info.special, "xor.l") != NULL)
4675 wlength++;
4676
4677 /* Fall through. */
4678
4679 case SHIFT_INLINE:
4680 n = info.remainder;
4681
4682 if (info.shift2 != NULL)
4683 {
4684 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
4685 n = n % 2;
4686 }
4687
4688 wlength += h8300_asm_insn_count (info.shift1) * n;
4689
4690 return 2 * wlength;
4691
4692 case SHIFT_ROT_AND:
4693 {
4694 int m = GET_MODE_BITSIZE (mode) - n;
4695
4696 /* Not all possibilities of rotate are supported. They shouldn't
4697 be generated, but let's watch for 'em. */
4698 gcc_assert (info.shift1);
4699
4700 if (info.shift2 != NULL)
4701 {
4702 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
4703 m = m % 2;
4704 }
4705
4706 wlength += h8300_asm_insn_count (info.shift1) * m;
4707
4708 /* Now mask off the high bits. */
4709 switch (mode)
4710 {
4711 case E_QImode:
4712 wlength += 1;
4713 break;
4714 case E_HImode:
4715 wlength += 2;
4716 break;
4717 case E_SImode:
4718 gcc_assert (!TARGET_H8300);
4719 wlength += 3;
4720 break;
4721 default:
4722 gcc_unreachable ();
4723 }
4724 return 2 * wlength;
4725 }
4726
4727 case SHIFT_LOOP:
4728 /* A loop to shift by a "large" constant value.
4729 If we have shift-by-2 insns, use them. */
4730 if (info.shift2 != NULL)
4731 {
4732 wlength += 3 + h8300_asm_insn_count (info.shift2);
4733 if (n % 2)
4734 wlength += h8300_asm_insn_count (info.shift1);
4735 }
4736 else
4737 {
4738 wlength += 3 + h8300_asm_insn_count (info.shift1);
4739 }
4740 return 2 * wlength;
4741
4742 default:
4743 gcc_unreachable ();
4744 }
4745 }
4746 }
4747
4748 /* Compute which flag bits are valid after a shift insn. */
4749
4750 enum attr_cc
compute_a_shift_cc(rtx insn ATTRIBUTE_UNUSED,rtx * operands)4751 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
4752 {
4753 rtx shift = operands[3];
4754 machine_mode mode = GET_MODE (shift);
4755 enum rtx_code code = GET_CODE (shift);
4756 enum shift_type shift_type;
4757 enum shift_mode shift_mode;
4758 struct shift_info info;
4759 int n;
4760
4761 switch (mode)
4762 {
4763 case E_QImode:
4764 shift_mode = QIshift;
4765 break;
4766 case E_HImode:
4767 shift_mode = HIshift;
4768 break;
4769 case E_SImode:
4770 shift_mode = SIshift;
4771 break;
4772 default:
4773 gcc_unreachable ();
4774 }
4775
4776 switch (code)
4777 {
4778 case ASHIFTRT:
4779 shift_type = SHIFT_ASHIFTRT;
4780 break;
4781 case LSHIFTRT:
4782 shift_type = SHIFT_LSHIFTRT;
4783 break;
4784 case ASHIFT:
4785 shift_type = SHIFT_ASHIFT;
4786 break;
4787 default:
4788 gcc_unreachable ();
4789 }
4790
4791 /* This case must be taken care of by one of the two splitters
4792 that convert a variable shift into a loop. */
4793 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4794
4795 n = INTVAL (operands[2]);
4796
4797 /* If the count is negative, make it 0. */
4798 if (n < 0)
4799 n = 0;
4800 /* If the count is too big, truncate it.
4801 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4802 do the intuitive thing. */
4803 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4804 n = GET_MODE_BITSIZE (mode);
4805
4806 get_shift_alg (shift_type, shift_mode, n, &info);
4807
4808 switch (info.alg)
4809 {
4810 case SHIFT_SPECIAL:
4811 if (info.remainder == 0)
4812 return info.cc_special;
4813
4814 /* Fall through. */
4815
4816 case SHIFT_INLINE:
4817 return info.cc_inline;
4818
4819 case SHIFT_ROT_AND:
4820 /* This case always ends with an and instruction. */
4821 return CC_SET_ZNV;
4822
4823 case SHIFT_LOOP:
4824 /* A loop to shift by a "large" constant value.
4825 If we have shift-by-2 insns, use them. */
4826 if (info.shift2 != NULL)
4827 {
4828 if (n % 2)
4829 return info.cc_inline;
4830 }
4831 return CC_CLOBBER;
4832
4833 default:
4834 gcc_unreachable ();
4835 }
4836 }
4837
4838 /* A rotation by a non-constant will cause a loop to be generated, in
4839 which a rotation by one bit is used. A rotation by a constant,
4840 including the one in the loop, will be taken care of by
4841 output_a_rotate () at the insn emit time. */
4842
4843 int
expand_a_rotate(rtx operands[])4844 expand_a_rotate (rtx operands[])
4845 {
4846 rtx dst = operands[0];
4847 rtx src = operands[1];
4848 rtx rotate_amount = operands[2];
4849 machine_mode mode = GET_MODE (dst);
4850
4851 if (h8sx_classify_shift (mode, ROTATE, rotate_amount) == H8SX_SHIFT_UNARY)
4852 return false;
4853
4854 /* We rotate in place. */
4855 emit_move_insn (dst, src);
4856
4857 if (GET_CODE (rotate_amount) != CONST_INT)
4858 {
4859 rtx counter = gen_reg_rtx (QImode);
4860 rtx_code_label *start_label = gen_label_rtx ();
4861 rtx_code_label *end_label = gen_label_rtx ();
4862
4863 /* If the rotate amount is less than or equal to 0,
4864 we go out of the loop. */
4865 emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX,
4866 QImode, 0, end_label);
4867
4868 /* Initialize the loop counter. */
4869 emit_move_insn (counter, rotate_amount);
4870
4871 emit_label (start_label);
4872
4873 /* Rotate by one bit. */
4874 switch (mode)
4875 {
4876 case E_QImode:
4877 emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx));
4878 break;
4879 case E_HImode:
4880 emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx));
4881 break;
4882 case E_SImode:
4883 emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx));
4884 break;
4885 default:
4886 gcc_unreachable ();
4887 }
4888
4889 /* Decrement the counter by 1. */
4890 emit_insn (gen_addqi3 (counter, counter, constm1_rtx));
4891
4892 /* If the loop counter is nonzero, we go back to the beginning
4893 of the loop. */
4894 emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1,
4895 start_label);
4896
4897 emit_label (end_label);
4898 }
4899 else
4900 {
4901 /* Rotate by AMOUNT bits. */
4902 switch (mode)
4903 {
4904 case E_QImode:
4905 emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount));
4906 break;
4907 case E_HImode:
4908 emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount));
4909 break;
4910 case E_SImode:
4911 emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount));
4912 break;
4913 default:
4914 gcc_unreachable ();
4915 }
4916 }
4917
4918 return 1;
4919 }
4920
4921 /* Output a rotate insn. */
4922
4923 const char *
output_a_rotate(enum rtx_code code,rtx * operands)4924 output_a_rotate (enum rtx_code code, rtx *operands)
4925 {
4926 rtx dst = operands[0];
4927 rtx rotate_amount = operands[2];
4928 enum shift_mode rotate_mode;
4929 enum shift_type rotate_type;
4930 const char *insn_buf;
4931 int bits;
4932 int amount;
4933 machine_mode mode = GET_MODE (dst);
4934
4935 gcc_assert (GET_CODE (rotate_amount) == CONST_INT);
4936
4937 switch (mode)
4938 {
4939 case E_QImode:
4940 rotate_mode = QIshift;
4941 break;
4942 case E_HImode:
4943 rotate_mode = HIshift;
4944 break;
4945 case E_SImode:
4946 rotate_mode = SIshift;
4947 break;
4948 default:
4949 gcc_unreachable ();
4950 }
4951
4952 switch (code)
4953 {
4954 case ROTATERT:
4955 rotate_type = SHIFT_ASHIFT;
4956 break;
4957 case ROTATE:
4958 rotate_type = SHIFT_LSHIFTRT;
4959 break;
4960 default:
4961 gcc_unreachable ();
4962 }
4963
4964 amount = INTVAL (rotate_amount);
4965
4966 /* Clean up AMOUNT. */
4967 if (amount < 0)
4968 amount = 0;
4969 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
4970 amount = GET_MODE_BITSIZE (mode);
4971
4972 /* Determine the faster direction. After this phase, amount will be
4973 at most a half of GET_MODE_BITSIZE (mode). */
4974 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
4975 {
4976 /* Flip the direction. */
4977 amount = GET_MODE_BITSIZE (mode) - amount;
4978 rotate_type =
4979 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
4980 }
4981
4982 /* See if a byte swap (in HImode) or a word swap (in SImode) can
4983 boost up the rotation. */
4984 if ((mode == HImode && TARGET_H8300 && amount >= 5)
4985 || (mode == HImode && TARGET_H8300H && amount >= 6)
4986 || (mode == HImode && TARGET_H8300S && amount == 8)
4987 || (mode == SImode && TARGET_H8300H && amount >= 10)
4988 || (mode == SImode && TARGET_H8300S && amount >= 13))
4989 {
4990 switch (mode)
4991 {
4992 case E_HImode:
4993 /* This code works on any family. */
4994 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
4995 output_asm_insn (insn_buf, operands);
4996 break;
4997
4998 case E_SImode:
4999 /* This code works on the H8/300H and H8S. */
5000 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5001 output_asm_insn (insn_buf, operands);
5002 break;
5003
5004 default:
5005 gcc_unreachable ();
5006 }
5007
5008 /* Adjust AMOUNT and flip the direction. */
5009 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5010 rotate_type =
5011 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5012 }
5013
5014 /* Output rotate insns. */
5015 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
5016 {
5017 if (bits == 2)
5018 insn_buf = rotate_two[rotate_type][rotate_mode];
5019 else
5020 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
5021
5022 for (; amount >= bits; amount -= bits)
5023 output_asm_insn (insn_buf, operands);
5024 }
5025
5026 return "";
5027 }
5028
5029 /* Compute the length of a rotate insn. */
5030
5031 unsigned int
compute_a_rotate_length(rtx * operands)5032 compute_a_rotate_length (rtx *operands)
5033 {
5034 rtx src = operands[1];
5035 rtx amount_rtx = operands[2];
5036 machine_mode mode = GET_MODE (src);
5037 int amount;
5038 unsigned int length = 0;
5039
5040 gcc_assert (GET_CODE (amount_rtx) == CONST_INT);
5041
5042 amount = INTVAL (amount_rtx);
5043
5044 /* Clean up AMOUNT. */
5045 if (amount < 0)
5046 amount = 0;
5047 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5048 amount = GET_MODE_BITSIZE (mode);
5049
5050 /* Determine the faster direction. After this phase, amount
5051 will be at most a half of GET_MODE_BITSIZE (mode). */
5052 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
5053 /* Flip the direction. */
5054 amount = GET_MODE_BITSIZE (mode) - amount;
5055
5056 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5057 boost up the rotation. */
5058 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5059 || (mode == HImode && TARGET_H8300H && amount >= 6)
5060 || (mode == HImode && TARGET_H8300S && amount == 8)
5061 || (mode == SImode && TARGET_H8300H && amount >= 10)
5062 || (mode == SImode && TARGET_H8300S && amount >= 13))
5063 {
5064 /* Adjust AMOUNT and flip the direction. */
5065 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5066 length += 6;
5067 }
5068
5069 /* We use 2-bit rotations on the H8S. */
5070 if (TARGET_H8300S)
5071 amount = amount / 2 + amount % 2;
5072
5073 /* The H8/300 uses three insns to rotate one bit, taking 6
5074 length. */
5075 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
5076
5077 return length;
5078 }
5079
5080 /* Fix the operands of a gen_xxx so that it could become a bit
5081 operating insn. */
5082
5083 int
fix_bit_operand(rtx * operands,enum rtx_code code)5084 fix_bit_operand (rtx *operands, enum rtx_code code)
5085 {
5086 /* The bit_operand predicate accepts any memory during RTL generation, but
5087 only 'U' memory afterwards, so if this is a MEM operand, we must force
5088 it to be valid for 'U' by reloading the address. */
5089
5090 if (code == AND
5091 ? single_zero_operand (operands[2], QImode)
5092 : single_one_operand (operands[2], QImode))
5093 {
5094 /* OK to have a memory dest. */
5095 if (GET_CODE (operands[0]) == MEM
5096 && !satisfies_constraint_U (operands[0]))
5097 {
5098 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
5099 copy_to_mode_reg (Pmode,
5100 XEXP (operands[0], 0)));
5101 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5102 operands[0] = mem;
5103 }
5104
5105 if (GET_CODE (operands[1]) == MEM
5106 && !satisfies_constraint_U (operands[1]))
5107 {
5108 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
5109 copy_to_mode_reg (Pmode,
5110 XEXP (operands[1], 0)));
5111 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5112 operands[1] = mem;
5113 }
5114 return 0;
5115 }
5116
5117 /* Dest and src op must be register. */
5118
5119 operands[1] = force_reg (QImode, operands[1]);
5120 {
5121 rtx res = gen_reg_rtx (QImode);
5122 switch (code)
5123 {
5124 case AND:
5125 emit_insn (gen_andqi3_1 (res, operands[1], operands[2]));
5126 break;
5127 case IOR:
5128 emit_insn (gen_iorqi3_1 (res, operands[1], operands[2]));
5129 break;
5130 case XOR:
5131 emit_insn (gen_xorqi3_1 (res, operands[1], operands[2]));
5132 break;
5133 default:
5134 gcc_unreachable ();
5135 }
5136 emit_insn (gen_movqi (operands[0], res));
5137 }
5138 return 1;
5139 }
5140
5141 /* Return nonzero if FUNC is an interrupt function as specified
5142 by the "interrupt" attribute. */
5143
5144 static int
h8300_interrupt_function_p(tree func)5145 h8300_interrupt_function_p (tree func)
5146 {
5147 tree a;
5148
5149 if (TREE_CODE (func) != FUNCTION_DECL)
5150 return 0;
5151
5152 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
5153 return a != NULL_TREE;
5154 }
5155
5156 /* Return nonzero if FUNC is a saveall function as specified by the
5157 "saveall" attribute. */
5158
5159 static int
h8300_saveall_function_p(tree func)5160 h8300_saveall_function_p (tree func)
5161 {
5162 tree a;
5163
5164 if (TREE_CODE (func) != FUNCTION_DECL)
5165 return 0;
5166
5167 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
5168 return a != NULL_TREE;
5169 }
5170
5171 /* Return nonzero if FUNC is an OS_Task function as specified
5172 by the "OS_Task" attribute. */
5173
5174 static int
h8300_os_task_function_p(tree func)5175 h8300_os_task_function_p (tree func)
5176 {
5177 tree a;
5178
5179 if (TREE_CODE (func) != FUNCTION_DECL)
5180 return 0;
5181
5182 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
5183 return a != NULL_TREE;
5184 }
5185
5186 /* Return nonzero if FUNC is a monitor function as specified
5187 by the "monitor" attribute. */
5188
5189 static int
h8300_monitor_function_p(tree func)5190 h8300_monitor_function_p (tree func)
5191 {
5192 tree a;
5193
5194 if (TREE_CODE (func) != FUNCTION_DECL)
5195 return 0;
5196
5197 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
5198 return a != NULL_TREE;
5199 }
5200
5201 /* Return nonzero if FUNC is a function that should be called
5202 through the function vector. */
5203
5204 int
h8300_funcvec_function_p(tree func)5205 h8300_funcvec_function_p (tree func)
5206 {
5207 tree a;
5208
5209 if (TREE_CODE (func) != FUNCTION_DECL)
5210 return 0;
5211
5212 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
5213 return a != NULL_TREE;
5214 }
5215
5216 /* Return nonzero if DECL is a variable that's in the eight bit
5217 data area. */
5218
5219 int
h8300_eightbit_data_p(tree decl)5220 h8300_eightbit_data_p (tree decl)
5221 {
5222 tree a;
5223
5224 if (TREE_CODE (decl) != VAR_DECL)
5225 return 0;
5226
5227 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
5228 return a != NULL_TREE;
5229 }
5230
5231 /* Return nonzero if DECL is a variable that's in the tiny
5232 data area. */
5233
5234 int
h8300_tiny_data_p(tree decl)5235 h8300_tiny_data_p (tree decl)
5236 {
5237 tree a;
5238
5239 if (TREE_CODE (decl) != VAR_DECL)
5240 return 0;
5241
5242 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
5243 return a != NULL_TREE;
5244 }
5245
5246 /* Generate an 'interrupt_handler' attribute for decls. We convert
5247 all the pragmas to corresponding attributes. */
5248
5249 static void
h8300_insert_attributes(tree node,tree * attributes)5250 h8300_insert_attributes (tree node, tree *attributes)
5251 {
5252 if (TREE_CODE (node) == FUNCTION_DECL)
5253 {
5254 if (pragma_interrupt)
5255 {
5256 pragma_interrupt = 0;
5257
5258 /* Add an 'interrupt_handler' attribute. */
5259 *attributes = tree_cons (get_identifier ("interrupt_handler"),
5260 NULL, *attributes);
5261 }
5262
5263 if (pragma_saveall)
5264 {
5265 pragma_saveall = 0;
5266
5267 /* Add an 'saveall' attribute. */
5268 *attributes = tree_cons (get_identifier ("saveall"),
5269 NULL, *attributes);
5270 }
5271 }
5272 }
5273
5274 /* Supported attributes:
5275
5276 interrupt_handler: output a prologue and epilogue suitable for an
5277 interrupt handler.
5278
5279 saveall: output a prologue and epilogue that saves and restores
5280 all registers except the stack pointer.
5281
5282 function_vector: This function should be called through the
5283 function vector.
5284
5285 eightbit_data: This variable lives in the 8-bit data area and can
5286 be referenced with 8-bit absolute memory addresses.
5287
5288 tiny_data: This variable lives in the tiny data area and can be
5289 referenced with 16-bit absolute memory references. */
5290
5291 static const struct attribute_spec h8300_attribute_table[] =
5292 {
5293 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
5294 affects_type_identity, handler, exclude } */
5295 { "interrupt_handler", 0, 0, true, false, false, false,
5296 h8300_handle_fndecl_attribute, NULL },
5297 { "saveall", 0, 0, true, false, false, false,
5298 h8300_handle_fndecl_attribute, NULL },
5299 { "OS_Task", 0, 0, true, false, false, false,
5300 h8300_handle_fndecl_attribute, NULL },
5301 { "monitor", 0, 0, true, false, false, false,
5302 h8300_handle_fndecl_attribute, NULL },
5303 { "function_vector", 0, 0, true, false, false, false,
5304 h8300_handle_fndecl_attribute, NULL },
5305 { "eightbit_data", 0, 0, true, false, false, false,
5306 h8300_handle_eightbit_data_attribute, NULL },
5307 { "tiny_data", 0, 0, true, false, false, false,
5308 h8300_handle_tiny_data_attribute, NULL },
5309 { NULL, 0, 0, false, false, false, false, NULL, NULL }
5310 };
5311
5312
5313 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5314 struct attribute_spec.handler. */
5315 static tree
h8300_handle_fndecl_attribute(tree * node,tree name,tree args ATTRIBUTE_UNUSED,int flags ATTRIBUTE_UNUSED,bool * no_add_attrs)5316 h8300_handle_fndecl_attribute (tree *node, tree name,
5317 tree args ATTRIBUTE_UNUSED,
5318 int flags ATTRIBUTE_UNUSED,
5319 bool *no_add_attrs)
5320 {
5321 if (TREE_CODE (*node) != FUNCTION_DECL)
5322 {
5323 warning (OPT_Wattributes, "%qE attribute only applies to functions",
5324 name);
5325 *no_add_attrs = true;
5326 }
5327
5328 return NULL_TREE;
5329 }
5330
5331 /* Handle an "eightbit_data" attribute; arguments as in
5332 struct attribute_spec.handler. */
5333 static tree
h8300_handle_eightbit_data_attribute(tree * node,tree name,tree args ATTRIBUTE_UNUSED,int flags ATTRIBUTE_UNUSED,bool * no_add_attrs)5334 h8300_handle_eightbit_data_attribute (tree *node, tree name,
5335 tree args ATTRIBUTE_UNUSED,
5336 int flags ATTRIBUTE_UNUSED,
5337 bool *no_add_attrs)
5338 {
5339 tree decl = *node;
5340
5341 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
5342 {
5343 set_decl_section_name (decl, ".eight");
5344 }
5345 else
5346 {
5347 warning (OPT_Wattributes, "%qE attribute ignored",
5348 name);
5349 *no_add_attrs = true;
5350 }
5351
5352 return NULL_TREE;
5353 }
5354
5355 /* Handle an "tiny_data" attribute; arguments as in
5356 struct attribute_spec.handler. */
5357 static tree
h8300_handle_tiny_data_attribute(tree * node,tree name,tree args ATTRIBUTE_UNUSED,int flags ATTRIBUTE_UNUSED,bool * no_add_attrs)5358 h8300_handle_tiny_data_attribute (tree *node, tree name,
5359 tree args ATTRIBUTE_UNUSED,
5360 int flags ATTRIBUTE_UNUSED,
5361 bool *no_add_attrs)
5362 {
5363 tree decl = *node;
5364
5365 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
5366 {
5367 set_decl_section_name (decl, ".tiny");
5368 }
5369 else
5370 {
5371 warning (OPT_Wattributes, "%qE attribute ignored",
5372 name);
5373 *no_add_attrs = true;
5374 }
5375
5376 return NULL_TREE;
5377 }
5378
5379 /* Mark function vectors, and various small data objects. */
5380
5381 static void
h8300_encode_section_info(tree decl,rtx rtl,int first)5382 h8300_encode_section_info (tree decl, rtx rtl, int first)
5383 {
5384 int extra_flags = 0;
5385
5386 default_encode_section_info (decl, rtl, first);
5387
5388 if (TREE_CODE (decl) == FUNCTION_DECL
5389 && h8300_funcvec_function_p (decl))
5390 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
5391 else if (TREE_CODE (decl) == VAR_DECL
5392 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
5393 {
5394 if (h8300_eightbit_data_p (decl))
5395 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
5396 else if (first && h8300_tiny_data_p (decl))
5397 extra_flags = SYMBOL_FLAG_TINY_DATA;
5398 }
5399
5400 if (extra_flags)
5401 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
5402 }
5403
5404 /* Output a single-bit extraction. */
5405
5406 const char *
output_simode_bld(int bild,rtx operands[])5407 output_simode_bld (int bild, rtx operands[])
5408 {
5409 if (TARGET_H8300)
5410 {
5411 /* Clear the destination register. */
5412 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
5413
5414 /* Now output the bit load or bit inverse load, and store it in
5415 the destination. */
5416 if (bild)
5417 output_asm_insn ("bild\t%Z2,%Y1", operands);
5418 else
5419 output_asm_insn ("bld\t%Z2,%Y1", operands);
5420
5421 output_asm_insn ("bst\t#0,%w0", operands);
5422 }
5423 else
5424 {
5425 /* Determine if we can clear the destination first. */
5426 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
5427 && REGNO (operands[0]) != REGNO (operands[1]));
5428
5429 if (clear_first)
5430 output_asm_insn ("sub.l\t%S0,%S0", operands);
5431
5432 /* Output the bit load or bit inverse load. */
5433 if (bild)
5434 output_asm_insn ("bild\t%Z2,%Y1", operands);
5435 else
5436 output_asm_insn ("bld\t%Z2,%Y1", operands);
5437
5438 if (!clear_first)
5439 output_asm_insn ("xor.l\t%S0,%S0", operands);
5440
5441 /* Perform the bit store. */
5442 output_asm_insn ("rotxl.l\t%S0", operands);
5443 }
5444
5445 /* All done. */
5446 return "";
5447 }
5448
5449 /* Delayed-branch scheduling is more effective if we have some idea
5450 how long each instruction will be. Use a shorten_branches pass
5451 to get an initial estimate. */
5452
5453 static void
h8300_reorg(void)5454 h8300_reorg (void)
5455 {
5456 if (flag_delayed_branch)
5457 shorten_branches (get_insns ());
5458 }
5459
5460 #ifndef OBJECT_FORMAT_ELF
5461 static void
h8300_asm_named_section(const char * name,unsigned int flags ATTRIBUTE_UNUSED,tree decl)5462 h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED,
5463 tree decl)
5464 {
5465 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5466 fprintf (asm_out_file, "\t.section %s\n", name);
5467 }
5468 #endif /* ! OBJECT_FORMAT_ELF */
5469
5470 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
5471 which is a special case of the 'R' operand. */
5472
5473 int
h8300_eightbit_constant_address_p(rtx x)5474 h8300_eightbit_constant_address_p (rtx x)
5475 {
5476 /* The ranges of the 8-bit area. */
5477 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
5478 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
5479 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
5480 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
5481 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
5482 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
5483
5484 unsigned HOST_WIDE_INT addr;
5485
5486 /* We accept symbols declared with eightbit_data. */
5487 if (GET_CODE (x) == SYMBOL_REF)
5488 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
5489
5490 if (GET_CODE (x) == CONST
5491 && GET_CODE (XEXP (x, 0)) == PLUS
5492 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
5493 && (SYMBOL_REF_FLAGS (XEXP (XEXP (x, 0), 0)) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0)
5494 return 1;
5495
5496 if (GET_CODE (x) != CONST_INT)
5497 return 0;
5498
5499 addr = INTVAL (x);
5500
5501 return (0
5502 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
5503 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
5504 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
5505 }
5506
5507 /* Nonzero if X is a constant address suitable as an 16-bit absolute
5508 on H8/300H and H8S. */
5509
5510 int
h8300_tiny_constant_address_p(rtx x)5511 h8300_tiny_constant_address_p (rtx x)
5512 {
5513 /* The ranges of the 16-bit area. */
5514 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
5515 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
5516 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
5517 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
5518 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
5519 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
5520 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
5521 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
5522
5523 unsigned HOST_WIDE_INT addr;
5524
5525 switch (GET_CODE (x))
5526 {
5527 case SYMBOL_REF:
5528 /* In the normal mode, any symbol fits in the 16-bit absolute
5529 address range. We also accept symbols declared with
5530 tiny_data. */
5531 return (TARGET_NORMAL_MODE
5532 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0);
5533
5534 case CONST_INT:
5535 addr = INTVAL (x);
5536 return (TARGET_NORMAL_MODE
5537 || (TARGET_H8300H
5538 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
5539 || (TARGET_H8300S
5540 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
5541
5542 case CONST:
5543 return TARGET_NORMAL_MODE;
5544
5545 default:
5546 return 0;
5547 }
5548
5549 }
5550
5551 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5552 locations that can be accessed as a 16-bit word. */
5553
5554 int
byte_accesses_mergeable_p(rtx addr1,rtx addr2)5555 byte_accesses_mergeable_p (rtx addr1, rtx addr2)
5556 {
5557 HOST_WIDE_INT offset1, offset2;
5558 rtx reg1, reg2;
5559
5560 if (REG_P (addr1))
5561 {
5562 reg1 = addr1;
5563 offset1 = 0;
5564 }
5565 else if (GET_CODE (addr1) == PLUS
5566 && REG_P (XEXP (addr1, 0))
5567 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
5568 {
5569 reg1 = XEXP (addr1, 0);
5570 offset1 = INTVAL (XEXP (addr1, 1));
5571 }
5572 else
5573 return 0;
5574
5575 if (REG_P (addr2))
5576 {
5577 reg2 = addr2;
5578 offset2 = 0;
5579 }
5580 else if (GET_CODE (addr2) == PLUS
5581 && REG_P (XEXP (addr2, 0))
5582 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
5583 {
5584 reg2 = XEXP (addr2, 0);
5585 offset2 = INTVAL (XEXP (addr2, 1));
5586 }
5587 else
5588 return 0;
5589
5590 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
5591 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
5592 && offset1 % 2 == 0
5593 && offset1 + 1 == offset2)
5594 return 1;
5595
5596 return 0;
5597 }
5598
5599 /* Return nonzero if we have the same comparison insn as I3 two insns
5600 before I3. I3 is assumed to be a comparison insn. */
5601
5602 int
same_cmp_preceding_p(rtx_insn * i3)5603 same_cmp_preceding_p (rtx_insn *i3)
5604 {
5605 rtx_insn *i1, *i2;
5606
5607 /* Make sure we have a sequence of three insns. */
5608 i2 = prev_nonnote_insn (i3);
5609 if (i2 == NULL)
5610 return 0;
5611 i1 = prev_nonnote_insn (i2);
5612 if (i1 == NULL)
5613 return 0;
5614
5615 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5616 && any_condjump_p (i2) && onlyjump_p (i2));
5617 }
5618
5619 /* Return nonzero if we have the same comparison insn as I1 two insns
5620 after I1. I1 is assumed to be a comparison insn. */
5621
5622 int
same_cmp_following_p(rtx_insn * i1)5623 same_cmp_following_p (rtx_insn *i1)
5624 {
5625 rtx_insn *i2, *i3;
5626
5627 /* Make sure we have a sequence of three insns. */
5628 i2 = next_nonnote_insn (i1);
5629 if (i2 == NULL)
5630 return 0;
5631 i3 = next_nonnote_insn (i2);
5632 if (i3 == NULL)
5633 return 0;
5634
5635 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5636 && any_condjump_p (i2) && onlyjump_p (i2));
5637 }
5638
5639 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
5640 (or pops) N registers. OPERANDS are assumed to be an array of
5641 registers. */
5642
5643 int
h8300_regs_ok_for_stm(int n,rtx operands[])5644 h8300_regs_ok_for_stm (int n, rtx operands[])
5645 {
5646 switch (n)
5647 {
5648 case 2:
5649 return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
5650 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
5651 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5));
5652 case 3:
5653 return ((REGNO (operands[0]) == 0
5654 && REGNO (operands[1]) == 1
5655 && REGNO (operands[2]) == 2)
5656 || (REGNO (operands[0]) == 4
5657 && REGNO (operands[1]) == 5
5658 && REGNO (operands[2]) == 6));
5659
5660 case 4:
5661 return (REGNO (operands[0]) == 0
5662 && REGNO (operands[1]) == 1
5663 && REGNO (operands[2]) == 2
5664 && REGNO (operands[3]) == 3);
5665 default:
5666 gcc_unreachable ();
5667 }
5668 }
5669
5670 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5671
5672 int
h8300_hard_regno_rename_ok(unsigned int old_reg ATTRIBUTE_UNUSED,unsigned int new_reg)5673 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
5674 unsigned int new_reg)
5675 {
5676 /* Interrupt functions can only use registers that have already been
5677 saved by the prologue, even if they would normally be
5678 call-clobbered. */
5679
5680 if (h8300_current_function_interrupt_function_p ()
5681 && !df_regs_ever_live_p (new_reg))
5682 return 0;
5683
5684 return 1;
5685 }
5686
5687 /* Returns true if register REGNO is safe to be allocated as a scratch
5688 register in the current function. */
5689
5690 static bool
h8300_hard_regno_scratch_ok(unsigned int regno)5691 h8300_hard_regno_scratch_ok (unsigned int regno)
5692 {
5693 if (h8300_current_function_interrupt_function_p ()
5694 && ! WORD_REG_USED (regno))
5695 return false;
5696
5697 return true;
5698 }
5699
5700
5701 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5702
5703 static int
h8300_rtx_ok_for_base_p(rtx x,int strict)5704 h8300_rtx_ok_for_base_p (rtx x, int strict)
5705 {
5706 /* Strip off SUBREG if any. */
5707 if (GET_CODE (x) == SUBREG)
5708 x = SUBREG_REG (x);
5709
5710 return (REG_P (x)
5711 && (strict
5712 ? REG_OK_FOR_BASE_STRICT_P (x)
5713 : REG_OK_FOR_BASE_NONSTRICT_P (x)));
5714 }
5715
5716 /* Return nozero if X is a legitimate address. On the H8/300, a
5717 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5718 CONSTANT_ADDRESS. */
5719
5720 static bool
h8300_legitimate_address_p(machine_mode mode,rtx x,bool strict)5721 h8300_legitimate_address_p (machine_mode mode, rtx x, bool strict)
5722 {
5723 /* The register indirect addresses like @er0 is always valid. */
5724 if (h8300_rtx_ok_for_base_p (x, strict))
5725 return 1;
5726
5727 if (CONSTANT_ADDRESS_P (x))
5728 return 1;
5729
5730 if (TARGET_H8300SX
5731 && ( GET_CODE (x) == PRE_INC
5732 || GET_CODE (x) == PRE_DEC
5733 || GET_CODE (x) == POST_INC
5734 || GET_CODE (x) == POST_DEC)
5735 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict))
5736 return 1;
5737
5738 if (GET_CODE (x) == PLUS
5739 && CONSTANT_ADDRESS_P (XEXP (x, 1))
5740 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x, 0),
5741 mode, 0), strict))
5742 return 1;
5743
5744 return 0;
5745 }
5746
5747 /* Implement TARGET_HARD_REGNO_MODE_OK. */
5748
5749 static bool
h8300_hard_regno_mode_ok(unsigned int regno,machine_mode mode)5750 h8300_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
5751 {
5752 if (TARGET_H8300)
5753 /* If an even reg, then anything goes. Otherwise the mode must be
5754 QI or HI. */
5755 return ((regno & 1) == 0) || (mode == HImode) || (mode == QImode);
5756 else
5757 /* MAC register can only be of SImode. Otherwise, anything
5758 goes. */
5759 return regno == MAC_REG ? mode == SImode : 1;
5760 }
5761
5762 /* Implement TARGET_MODES_TIEABLE_P. */
5763
5764 static bool
h8300_modes_tieable_p(machine_mode mode1,machine_mode mode2)5765 h8300_modes_tieable_p (machine_mode mode1, machine_mode mode2)
5766 {
5767 return (mode1 == mode2
5768 || ((mode1 == QImode
5769 || mode1 == HImode
5770 || ((TARGET_H8300H || TARGET_H8300S) && mode1 == SImode))
5771 && (mode2 == QImode
5772 || mode2 == HImode
5773 || ((TARGET_H8300H || TARGET_H8300S) && mode2 == SImode))));
5774 }
5775
5776 /* Helper function for the move patterns. Make sure a move is legitimate. */
5777
5778 bool
h8300_move_ok(rtx dest,rtx src)5779 h8300_move_ok (rtx dest, rtx src)
5780 {
5781 rtx addr, other;
5782
5783 /* Validate that at least one operand is a register. */
5784 if (MEM_P (dest))
5785 {
5786 if (MEM_P (src) || CONSTANT_P (src))
5787 return false;
5788 addr = XEXP (dest, 0);
5789 other = src;
5790 }
5791 else if (MEM_P (src))
5792 {
5793 addr = XEXP (src, 0);
5794 other = dest;
5795 }
5796 else
5797 return true;
5798
5799 /* Validate that auto-inc doesn't affect OTHER. */
5800 if (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC)
5801 return true;
5802 addr = XEXP (addr, 0);
5803
5804 if (addr == stack_pointer_rtx)
5805 return register_no_sp_elim_operand (other, VOIDmode);
5806 else
5807 return !reg_overlap_mentioned_p(other, addr);
5808 }
5809
5810 /* Perform target dependent optabs initialization. */
5811 static void
h8300_init_libfuncs(void)5812 h8300_init_libfuncs (void)
5813 {
5814 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
5815 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
5816 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
5817 set_optab_libfunc (smod_optab, HImode, "__modhi3");
5818 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
5819 }
5820
5821 /* Worker function for TARGET_FUNCTION_VALUE.
5822
5823 On the H8 the return value is in R0/R1. */
5824
5825 static rtx
h8300_function_value(const_tree ret_type,const_tree fn_decl_or_type ATTRIBUTE_UNUSED,bool outgoing ATTRIBUTE_UNUSED)5826 h8300_function_value (const_tree ret_type,
5827 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
5828 bool outgoing ATTRIBUTE_UNUSED)
5829 {
5830 return gen_rtx_REG (TYPE_MODE (ret_type), R0_REG);
5831 }
5832
5833 /* Worker function for TARGET_LIBCALL_VALUE.
5834
5835 On the H8 the return value is in R0/R1. */
5836
5837 static rtx
h8300_libcall_value(machine_mode mode,const_rtx fun ATTRIBUTE_UNUSED)5838 h8300_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5839 {
5840 return gen_rtx_REG (mode, R0_REG);
5841 }
5842
5843 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
5844
5845 On the H8, R0 is the only register thus used. */
5846
5847 static bool
h8300_function_value_regno_p(const unsigned int regno)5848 h8300_function_value_regno_p (const unsigned int regno)
5849 {
5850 return (regno == R0_REG);
5851 }
5852
5853 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5854
5855 static bool
h8300_return_in_memory(const_tree type,const_tree fntype ATTRIBUTE_UNUSED)5856 h8300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
5857 {
5858 return (TYPE_MODE (type) == BLKmode
5859 || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8));
5860 }
5861
5862 /* We emit the entire trampoline here. Depending on the pointer size,
5863 we use a different trampoline.
5864
5865 Pmode == HImode
5866 vvvv context
5867 1 0000 7903xxxx mov.w #0x1234,r3
5868 2 0004 5A00xxxx jmp @0x1234
5869 ^^^^ function
5870
5871 Pmode == SImode
5872 vvvvvvvv context
5873 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
5874 3 0006 5Axxxxxx jmp @0x123456
5875 ^^^^^^ function
5876 */
5877
5878 static void
h8300_trampoline_init(rtx m_tramp,tree fndecl,rtx cxt)5879 h8300_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
5880 {
5881 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
5882 rtx mem;
5883
5884 if (Pmode == HImode)
5885 {
5886 mem = adjust_address (m_tramp, HImode, 0);
5887 emit_move_insn (mem, GEN_INT (0x7903));
5888 mem = adjust_address (m_tramp, Pmode, 2);
5889 emit_move_insn (mem, cxt);
5890 mem = adjust_address (m_tramp, HImode, 4);
5891 emit_move_insn (mem, GEN_INT (0x5a00));
5892 mem = adjust_address (m_tramp, Pmode, 6);
5893 emit_move_insn (mem, fnaddr);
5894 }
5895 else
5896 {
5897 rtx tem;
5898
5899 mem = adjust_address (m_tramp, HImode, 0);
5900 emit_move_insn (mem, GEN_INT (0x7a03));
5901 mem = adjust_address (m_tramp, Pmode, 2);
5902 emit_move_insn (mem, cxt);
5903
5904 tem = copy_to_reg (fnaddr);
5905 emit_insn (gen_andsi3 (tem, tem, GEN_INT (0x00ffffff)));
5906 emit_insn (gen_iorsi3 (tem, tem, GEN_INT (0x5a000000)));
5907 mem = adjust_address (m_tramp, SImode, 6);
5908 emit_move_insn (mem, tem);
5909 }
5910 }
5911
5912 /* Implement PUSH_ROUNDING.
5913
5914 On the H8/300, @-sp really pushes a byte if you ask it to - but that's
5915 dangerous, so we claim that it always pushes a word, then we catch
5916 the mov.b rx,@-sp and turn it into a mov.w rx,@-sp on output.
5917
5918 On the H8/300H, we simplify TARGET_QUICKCALL by setting this to 4
5919 and doing a similar thing. */
5920
5921 poly_int64
h8300_push_rounding(poly_int64 bytes)5922 h8300_push_rounding (poly_int64 bytes)
5923 {
5924 return ((bytes + PARM_BOUNDARY / 8 - 1) & (-PARM_BOUNDARY / 8));
5925 }
5926
5927 /* Initialize the GCC target structure. */
5928 #undef TARGET_ATTRIBUTE_TABLE
5929 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
5930
5931 #undef TARGET_ASM_ALIGNED_HI_OP
5932 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
5933
5934 #undef TARGET_ASM_FILE_START
5935 #define TARGET_ASM_FILE_START h8300_file_start
5936 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
5937 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
5938
5939 #undef TARGET_ASM_FILE_END
5940 #define TARGET_ASM_FILE_END h8300_file_end
5941
5942 #undef TARGET_PRINT_OPERAND
5943 #define TARGET_PRINT_OPERAND h8300_print_operand
5944 #undef TARGET_PRINT_OPERAND_ADDRESS
5945 #define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address
5946 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
5947 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p
5948
5949 #undef TARGET_ENCODE_SECTION_INFO
5950 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
5951
5952 #undef TARGET_INSERT_ATTRIBUTES
5953 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
5954
5955 #undef TARGET_REGISTER_MOVE_COST
5956 #define TARGET_REGISTER_MOVE_COST h8300_register_move_cost
5957
5958 #undef TARGET_RTX_COSTS
5959 #define TARGET_RTX_COSTS h8300_rtx_costs
5960
5961 #undef TARGET_INIT_LIBFUNCS
5962 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
5963
5964 #undef TARGET_FUNCTION_VALUE
5965 #define TARGET_FUNCTION_VALUE h8300_function_value
5966
5967 #undef TARGET_LIBCALL_VALUE
5968 #define TARGET_LIBCALL_VALUE h8300_libcall_value
5969
5970 #undef TARGET_FUNCTION_VALUE_REGNO_P
5971 #define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p
5972
5973 #undef TARGET_RETURN_IN_MEMORY
5974 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
5975
5976 #undef TARGET_FUNCTION_ARG
5977 #define TARGET_FUNCTION_ARG h8300_function_arg
5978
5979 #undef TARGET_FUNCTION_ARG_ADVANCE
5980 #define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance
5981
5982 #undef TARGET_MACHINE_DEPENDENT_REORG
5983 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
5984
5985 #undef TARGET_HARD_REGNO_SCRATCH_OK
5986 #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
5987
5988 #undef TARGET_HARD_REGNO_MODE_OK
5989 #define TARGET_HARD_REGNO_MODE_OK h8300_hard_regno_mode_ok
5990
5991 #undef TARGET_MODES_TIEABLE_P
5992 #define TARGET_MODES_TIEABLE_P h8300_modes_tieable_p
5993
5994 #undef TARGET_LRA_P
5995 #define TARGET_LRA_P hook_bool_void_false
5996
5997 #undef TARGET_LEGITIMATE_ADDRESS_P
5998 #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
5999
6000 #undef TARGET_CAN_ELIMINATE
6001 #define TARGET_CAN_ELIMINATE h8300_can_eliminate
6002
6003 #undef TARGET_CONDITIONAL_REGISTER_USAGE
6004 #define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage
6005
6006 #undef TARGET_TRAMPOLINE_INIT
6007 #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
6008
6009 #undef TARGET_OPTION_OVERRIDE
6010 #define TARGET_OPTION_OVERRIDE h8300_option_override
6011
6012 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
6013 #define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p
6014
6015 #undef TARGET_HAVE_SPECULATION_SAFE_VALUE
6016 #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed
6017
6018 struct gcc_target targetm = TARGET_INITIALIZER;
6019